JP3744780B2 - Oscillator circuit - Google Patents

Description

ここで、Ｖｓａｔは、トランジスタのコレクタエミッタ間の飽和電圧を意味し、ＶｓａｔＱ４＝ＶｓａｔＱ５＝Ｖｓａｔとする。
【００１８】
このように、充放電の振幅Ｖｗは、Ｖ１依存性がある。このため、発振周波数は、Ｖ１依存性を有し、電源電圧Ｖ１が変動すると、変動することになる。そこで、発振周波数を安定させるためには、レギュレータなどを設け、Ｖ１を安定化する必要がある。さらに、振幅Ｖｗは、Ｖｓａｔの項を含む。Ｖｓａｔは、トランジスタの特性であり、温度の影響を受けやすく、従って発振周波数が温度に依存して変化しやすいという問題があった。
【００１９】
また、電圧ＶＨは、トランジスタＱ２，Ｑ３のオン動作に支障のないように、次の条件を満たす必要がある。
【００２０】
ＶＨ＜Ｖ１−ＶｂｅＱ３−ＶｃｅＱ２＋ＶｂｅＱ２＝Ｖ１−ＶｃｅＱ２
ここで、Ｖｂｅはベースエミッタ間電圧であり、ＶｂｅＱ３＝ＶｂｅＱ２とする。
【００２１】
同様に、ＶＬもＶＬ＞ＶｂｅＱ２＋ＶｃｅＱ９という制約を受ける。また、充放電の振幅はＶｗであり、ＶＬ＋Ｖｗ＝ＶＨ＜Ｖ１ーＶｃｅＱ２である。
【００２２】
従って、Ｖ１＞ＶＬ＋Ｖｗ＋ＶｃｅＱ２＞ＶｂｅＱ２＋ＶｃｅＱ９＋Ｖｗ＋ＶｃｅＱ２＝Ｖｗ＋Ｖｂｅ＋２Ｖｃｅ
を満たす必要がある。従って、Ｖｗを大きくとろうとすると、Ｖ１としてかなり大きな電圧が必要であった。さらに、レギュレータを設けるレギュレートされた電圧は、電源電圧Ｖ１に比べ低くなる。従って、電池駆動、特に１．５Ｖを電源電圧としようとすると、Ｖｗを十分とることができず、回路を十分動作させることが難しかった。
【００２３】
本発明は、上記課題に鑑みなされたものであり、安定した発振が行えるとともに、電源電圧が低くても動作が可能な発振回路を提供することを目的とする。
【００２４】
【課題を解決するための手段】
本発明は、第１定電流源に接続され、第１および第２差動トランジスタを含む差動アンプと、前記第１差動トランジスタの電流経路に設けられた第１抵抗を含み、前記第１差動トランジスタのオンまたはオフに応じて前記第１抵抗に前記第１定電流源に流れる定電流が流れるか流れないかにより発生する電圧降下の差を反映した電圧を第２差動トランジスタのベースに印加する第１電圧制御手段と、前記第２差動トランジスタのオン時において定電流を流し、前記第２差動トランジスタのオフ時において定電流を流さない第２定電流手段と、この第２定電流手段の定電流が供給される並列接続された第２抵抗およびコンデンサと、を含み、前記第２差動トランジスタのオン時において前記第２定電流手段の定電流に応じて前記コンデンサに充電し、第２差動トランジスタのオフ時において前記第２抵抗を介し前記コンデンサの放電を行い、このコンデンサの充放電に伴い変化する電圧を前記第１差動トランジスタのベースに印加する第２電圧制御手段と、を有し、前記第１および第２電圧制御手段により前記第２および第１差動トランジスタを制御して、前記第２差動トランジスタのベースに印加される電圧差を前記第１定電流源に流れる定電流値と前記第１抵抗の抵抗値の積により決定される電源電圧に依存しない値とし、これによって第１差動トランジスタのベースに印加される前記コンデンサの充放電による電圧差も電源電圧に依存しない値とすることにより、前記差動アンプの出力に電源電圧に依存しない所定周波数の発振信号を得ることを特徴とする。
【００２５】
これによって、第２差動トランジスタのベースに設定される電圧の差は、第１の差動トランジスタがオンの際に第１抵抗において発生される電圧降下に対応する電圧になる。従って、その値は、第１抵抗の抵抗値と第１差動トランジスタのオン時に流れる電流値の積で決定され、電源電圧に依存しない。これによって、回路の発振周波数に電源電圧の依存性がなく、従って電源電圧を一定にするためのレギュレータなどが不要であり、回路が簡単になる。また、レギュレータが不要であるため、電源電圧をそのまま利用でき、電圧についての制限が緩和され低電圧電源での動作が容易になる。さらに、抵抗値と定電流で上記電圧差が決定されるため、発振周波数がトランジスタの特性の影響を受けず、安定した動作が確保できる。
【００２６】
さらに、前記第１差動トランジスタの電流経路に設けられた抵抗に常時所定の電流を流す第３定電流手段を有し、この第３定電流手段の電流に伴う電圧降下した電圧を前記第２差動トランジスタのベースに加算して印加することが好適である。これによって、電源投入時において、第３定電流手段に流れる電流により第２差動トランジスタをオフし、第１差動トランジスタをオンすることができ、安定した動作が保証される。
【００２７】
【発明の実施の形態】
以下、本発明の実施の形態（以下実施形態という）について、図面に基づいて説明する。
【００２８】
図１は、実施形態の電圧制御発振回路の一例を示す図である。ＮＰＮ型の差動トランジスタ（第１および第２差動トランジスタ）Ｑ１１，Ｑ１２は、そのエミッタ同士が接続され、そのエミッタはＮＰＮトランジスタＱ２０を介し、グランドに接続されている。このトランジスタＱ２０のベースには、コレクタ・ベースがショートされているＮＰＮトランジスタＱ１９のベースが接続されており、このトランジスタＱ１９のエミッタはグランドに接続され、コレクタは定電流Ｉ１１を流す定電流源Ｉ１１を介し電源Ｖ１に接続されている。従って、トランジスタＱ１９は、定電流源（第１定電流源）Ｉ１１の定電流Ｉ１１を流し、この電流がトランジスタＱ２０に流れる。
【００２９】
トランジスタＱ１２のコレクタは、ＰＮＰトランジスタＱ１７のコレクタに接続され、このトランジスタＱ１７のエミッタは電源Ｖ１に接続されている。また、トランジスタＱ１７は、ベースコレクタ間がショートされている。トランジスタＱ１７のベースにはＰＮＰトランジスタＱ１８のベースが接続され、トランジスタＱ１８のエミッタは電源Ｖ１に接続されている。従って、トランジスタＱ１７，Ｑ１８はカレントミラーを構成している。
【００３０】
トランジスタＱ１８のコレクタには、コレクタベースがショートしたＮＰＮトランジスタＱ１６のコレクタが接続されている。このトランジスタＱ１６のエミッタはグランドに接続されている。
【００３１】
このトランジスタＱ１６のベースには、ＮＰＮトランジスタＱ１５のベースが接続されており、このトランジスタＱ１５のエミッタはグランドに接続されており、トランジスタＱ１６，Ｑ１５はカレントミラーを構成する。このため、トランジスタＱ１２がオンしたとき、その電流がＱ１７，Ｑ１８，Ｑ１６，Ｑ１５に流れる。
【００３２】
トランジスタＱ１５のコレクタには、ＮＰＮトランジスタＱ１４，Ｑ１３のベースが接続されている。従って、トランジスタＱ１５がオンすることによって、トランジスタＱ１４，Ｑ１３がオフする。
【００３３】
トランジスタＱ１３はコレクタベースがショートされており、エミッタがグランドに接続され、コレクタが定電流源（第２定電流源）Ｉ１０を介し電源Ｖ１に接続されている。また、トランジスタＱ１４のエミッタはグランドに接続されており、コレクタは、抵抗Ｒ（第２抵抗）１１およびコンデンサＣ１１を介し電源Ｖ１に接続されている。また、トランジスタＱ１４のコレクタと、コンデンサＣ１１および抵抗Ｒ１１との接続点であるＢ点がトランジスタＱ１１のベースに接続されている。
【００３４】
従って、トランジスタＱ１５がオフのときにトランジスタＱ１３，Ｑ１４はオンし、トランジスタＱ１４に流れる電流によって、コンデンサＣ１１が充電されＢ点の電位が下がり、トランジスタＱ１５がオンのときにトランジスタＱ１３，Ｑ１４はオフし、コンデンサＣ１１は、抵抗Ｒ１１を介し電源Ｖ１からの電流で放電され、Ｂ点電圧が上昇する。
【００３５】
トランジスタＱ１１のコレクタは抵抗（第１抵抗）Ｒ１２を介し、電源Ｖ１に接続されており、トランジスタＱ１１のコレクタと抵抗１２の中間点は、トランジスタＱ１２のベースに接続されるとともに定電流Ｉ１２を流す定電流源（第３定電流源）Ｉ１２を介しグランドに接続されている。
【００３６】
従って、トランジスタＱ１２のベース電位であるＡ点電位は、トランジスタＱ１１がオフの際に、
ＶＨ＝Ｖ１−Ｒ１２＊Ｉ１２
となり、
トランジスタＱ１１がオフの際に、
ＶＬ＝Ｖ１−Ｒ１２＊（Ｉ１１＋Ｉ１２）
となる。
【００３７】
また、トランジスタＱ１７，Ｑ１８のベースには、ＰＮＰトランジスタＱ２２のベースが接続されており、トランジスタＱ２２のエミッタは電源Ｖ１に接続され、コレクタは抵抗Ｒ１３を介しグランドに接続されている。従って、トランジスタＱ２２は、トランジスタＱ１２，Ｑ１７と同じ電流を流す。そして、トランジスタＱ２２と抵抗Ｒ１３の中間点が出力端になっており、トランジスタＱ２２がオフのときに出力はグランド電圧（Ｌ）となり、トランジスタＱ２２がオンのときに、電圧は、Ｉ１１＊Ｒ１３（Ｈ）となる。
【００３８】
このような回路において、（ｉ）電源を投入すると、Ｂ点電圧ＶＢは、定電流源Ｉ１２の電流による電圧降下があるＡ点電圧より高くなる。（ｉｉ）そこで、トランジスタＱ１１がオンし、トランジスタＱ１２，Ｑ１７，Ｑ１８，Ｑ１５がオフする。これによって、トランジスタＱ１３，Ｑ１４がオンし、コンデンサＣ１１の下側に当たるＢ点電位が下がりコンデンサＣ１１の充電が始まる。充電電流は、トランジスタＱ１４に流れる電流Ｉ１０から抵抗Ｒ１１に流れる電流（Ｖ１−ＶＢ）／Ｒ１１を差し引いた電流となる。
【００３９】
（ｉｉｉ）コンデンサＣ１の充電によって、ＶＢは下降する。（ｉｖ）電圧ＶＢがＶＬに達すると、トランジスタＱ１１がオフしトランジスタＱ１２がオンする。そして、トランジスタＱ１７，Ｑ１８，Ｑ１５がオンし、トランジスタＱ１３，Ｑ１４がオフする。また、トランジスタＱ１１がオフすることによって、Ａ点電圧ＶＡは、ＶＨに設定される。（ｉｖ）トランジスタＱ１４のオフによって、コンデンサＣ１１への充電が停止され、抵抗Ｒに流れる電流によって徐々に放電し、Ｂ点電圧は徐々に上昇する。（ｖｉ）Ｂ点電圧が上昇してＶＨに達すると、（ｉｉ）の動作に戻り、これを繰り返し回路は発振する。
【００４０】
従って、図２に示すように、Ｂ点電圧は、ＶＨ→ＶＬ→ＶＨ→・・・・を繰り返すことになり、電圧が下降するとき（コンデンサＣ１１の充電時）に、出力がＬ、電圧が上昇するとき（コンデンサＣ１１の放電時）に、出力がＨとなる。
【００４１】
このような回路において、発振は、コンデンサＣ１１の充放電によって行われ、その発振周波数は、充放電の振幅Ｖｗ＝ＶＨ−ＶＬ、充電電流値、コンデンサＣ１１の容量値Ｃ１１，抵抗値Ｒ１１によって、決定される。
【００４２】
ここで、充放電の振幅、Ｖｗは、Ｖｗ＝ＶＨ−ＶＬ＝Ｖ１−Ｒ１１＊Ｉ１２−｛Ｖ１−Ｒ１１＊（Ｉ１１＋Ｉ１２）｝
＝Ｉ１１＊Ｒ１１となる。従って、充放電の振幅Ｖｗには、電源電圧Ｖ１の依存性がなくなる。従って、発振周波数の電源電圧Ｖ１依存性がなくなり、電源電圧の変動の影響を除去するためのレギュレータが不要になる。さらに、トランジスタのコレクタエミッタ間の飽和電圧の影響もない。従って、トランジスタの特性の影響がなくなり、温度依存性の排除も容易になる。
【００４３】
さらに、電圧ＶＨおよびＶＬからくる制約は、
ＶＨ＜Ｖ１−ＶｂｅＱ７−ＶｃｅＱ２＋ＶｂｅＱ２＝Ｖ１−ＶｃｅＱ２
ここで、ＶｂｅＱ７＝ＶｂｅＱ２とする。
【００４４】
同様に、ＶＬもＶＬ＞ＶｂｅＱ１＋ＶｃｅＱ１０＝ＶｂｅＱ１＋ＶｃｅＱ１０という制約を受ける。また、充放電の振幅はＶｗであり、
ＶＬ＋Ｖｗ＝ＶＨ＜Ｖ１ーＶｃｅＱ２である。
【００４５】
従って、Ｖ１＞ＶＬ＋Ｖｗ＋ＶｃｅＱ２＞Ｖｗ＋ＶｂｅＱ２＋ＶｃｅＱ１０＋ＶｃｅＱ２＝Ｖｗ＋Ｖｂｅ＋２Ｖｃｅ
となり、満たすべき条件は図３の従来例の回路と同一になる。しかし、上述のようにレギュレータが不要であり、電源電圧がより定電圧でも利用が可能になる。例えば、電源電圧を乾電池１本の電圧である１．５Ｖとする回路にも好適に適用できる。
【００４６】
なお、上述の回路において、定電流源Ｉ１２を設けたが、これを省略することも可能である。これを省略した場合、ＶＨ＝Ｖ１となり、電源投入時にトランジスタＱ１１がオンすることが保証されず当初動作が不安定になるが、通常の動作が始まればその後は問題ない。
【００４７】
また、定電流源Ｉ１１を入力電圧に応じて変更することによって、電圧制御発振器としての動作が行われる。
【００４８】
以上のように、本実施形態の回路によれば、発振周波数に電源電圧の依存性がない。従って、電圧を一定にするためのレギュレータなどが不要であり、回路が簡単になる。また、レギュレータが不要であるため、電源電圧をそのまま利用でき、電圧についての制限が緩和され定電圧電源での動作が容易になる。さらに、発振周波数がトランジスタの特性の影響を受けず、安定した動作が確保できる。
【００４９】
【発明の効果】
以上説明したように、本発明によれば、第１差動トランジスタのベースに設定される電圧の差は、第２の差動トランジスタがオンの際に抵抗において発生される電圧降下に対応する電圧になる。従って、その値は、抵抗値と差動アンプの電流値の積で決定され、電源電圧に依存しない。これによって、回路の発振周波数に電源電圧の依存性がなく、従って電源電圧を一定にするためのレギュレータなどが不要であり、回路が簡単になる。また、レギュレータが不要であるため、電源電圧をそのまま利用でき、電圧についての制限が緩和され定電圧電源での動作が容易になる。さらに、抵抗値と定電流で上記電圧差が決定されるため、発振周波数がトランジスタの特性の影響を受けず、安定した動作が確保できる。
【００５０】
さらに、第２定電流手段を設け、この第２定電流手段の電流に伴う電圧降下した電圧を前記第２トランジスタのベースに加算して印加することで、電源投入時において、第２定電流手段に流れる電流により第２差動トランジスタをオフし、第１差動トランジスタをオンすることができ、安定した動作が保証される。
【図面の簡単な説明】
【図１】 実施形態の回路構成を示す図である。
【図２】 実施形態の回路の動作を説明する図である。
【図３】 従来例の回路構成を示す図である。
【図４】 従来例の回路の動作を説明する図である。
【符号の説明】
Ｑ１１〜Ｑ２２ トランジスタ、Ｉ１０〜Ｉ１３ 定電流源、Ｃ１１ コンデンサ、Ｒ１１〜Ｒ１３ 抵抗。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillation circuit that obtains an oscillation signal having a predetermined frequency by using charging and discharging of a capacitor.
[0002]
[Prior art]
Conventionally, various oscillation circuits have been used in digital processing circuits and the like. Among such oscillation circuits, there is a voltage-controlled oscillation circuit in which the oscillation frequency is controlled in accordance with the input voltage value, which is used for a PLL (phase lock loop) circuit or the like.
[0003]
FIG. 3 is a diagram illustrating an example of a conventional voltage controlled oscillation circuit. The NPN differential transistors Q1 and Q2 have their emitters connected to each other, and the emitter is connected to the ground via a constant current source I0. The collector of the transistor Q2 is connected to the collector of the PNP transistor Q3, and the emitter of the transistor Q3 is connected to the power supply V1. The transistor Q3 has a shorted base collector. The base of the transistor Q3 is connected to the base of the PNP transistor Q4, and the emitter of the transistor Q4 is connected to the power supply V1. Therefore, the transistors Q3 and Q4 constitute a current mirror.
[0004]
The emitter is connected to the power source V1, and the collector of the always-on PNP transistor Q5 is connected to the ground via resistors R1, R2, and R3. Therefore, a voltage divided at the intermediate point of the resistors R1, R2, and R3 is obtained. The collector of the transistor Q4 is connected to the middle point of the resistors R1 and R2, and the point A that is the middle point of the resistors R2 and R3 is connected to the base of the transistor Q2.
[0005]
When the transistor Q2 is turned on, the current flows through the transistors Q3 and Q4, and further flows through the resistors R2 and R3. Therefore, the voltage value of the base of the transistor Q2 varies depending on whether the transistor Q2 is on or off.
[0006]
That is, the point A voltage VL when the transistor Q2 is off is
VL = (V1-VsatQ5) * R3 / (R1 + R2 + R3)
A point voltage VH when the transistor Q2 is ON is
VH = (V1-VsatQ4) * R3 / (R2 + R3)
It becomes.
[0007]
The collector of the transistor Q1 is connected to the collector of the PNP transistor Q6 whose base collector is short-circuited, and the emitter of the transistor Q6 is connected to the power source V1. The base of the transistor Q6 is connected to the base of the PNP transistor Q7, and the emitter of the transistor Q7 is connected to the power source V1. Therefore, transistors Q6 and Q7 constitute a current mirror.
[0008]
The collector of the transistor Q7 is connected to the base of the PNP transistor Q8, the emitter of the transistor Q8 is connected to the power supply V1, and the collector is connected to the ground via the resistor R0 and the capacitor C1. A point B, which is a connection point between the collector of the transistor Q8, the resistor R0, and the capacitor C1, is connected to the base of the transistor Q1.
[0009]
The collector of transistor Q7 and the base of transistor Q8 are connected to the bases of transistors Q3 and Q4 and to the base of PNP transistor Q9. The emitter of the transistor Q9 is connected to the power supply V1, and the collector of the transistor Q9 is connected to the ground via the resistor R4. Then, an output is taken out from an intermediate point between the collector of the transistor Q9 and the resistor R2.
[0010]
Therefore, when the transistor Q2 is on, the current flows through the transistor Q3, and therefore the same current flows through the transistors Q4, Q8, and Q9. On the other hand, when the transistor Q1 is on, the current flows to the transistor Q6, and the transistor Q7 is turned on, so that the transistors Q8 and Q9 are turned off.
[0011]
The output voltage becomes H corresponding to the voltage drop due to the resistor R4 when the transistor Q9 is turned on, and becomes L when the transistor Q9 is turned off.
[0012]
Here, (i) when the power is turned on, the B point potential VB is 0 V because it is connected to the ground by the resistor R0. On the other hand, since the transistor Q5 is always on, the potential at the point A is higher than 0 V by the voltage at the resistor R3, so that the transistor Q2 is turned on and the transistor Q1 is turned off. (Ii) When the transistor Q2 is turned on, the transistors Q3, Q4, Q8, and Q9 are turned on. Thus, charging of the capacitor C1 is started by turning on the transistor Q8. At the same time, the potential VA at the point A is set to VH. Further, when the transistor Q9 is turned on, the output becomes H.
[0013]
(Iii) The B point voltage VB gradually increases due to the charging of the capacitor C1. (Iv) When the potential VB reaches VH due to charging of the capacitor C1, the transistors Q1, Q6, Q7 are turned on, whereby the transistors Q2, Q3, Q4, Q8, Q9 are turned off, Charging stops and the output becomes L. (V) Thereby, the capacitor C1 is discharged through the resistor R0, and the voltage VB gradually decreases. (Vi) When the voltage VB reaches VL and becomes lower than the point A voltage VA than the point B voltage VB, the transistor Q2 is turned on, the transistor Q1 is turned off, and the state returns to the state (ii) described above.
[0014]
Thereby, the circuit repeatedly oscillates the states (ii) to (vi), and an oscillation signal is obtained at the output. That is, as shown in FIG. 4, the voltage VB increases from VL to VH from (ii) → (iv), decreases from VH to VL from (iv) → (vi), and this is repeated, and the output is ( The period H is (ii) → (iv), and the period L is (iv) → (vi).
[0015]
Therefore, with this circuit, a signal that oscillates at an oscillation frequency corresponding to the amount of current of the constant current source I0 can be obtained.
[0016]
[Problems to be solved by the invention]
Thus, in the above conventional example, the oscillation is performed by charging and discharging the capacitor C1. Therefore, the oscillation frequency is determined by the charge / discharge amplitude Vw = VH−VL, the charging current value, the capacitor capacity C1, and the resistance value R1. The charge / discharge amplitude Vw is expressed by the following equation.
[0017]

Here, Vsat means a saturation voltage between the collector and emitter of the transistor, and VsatQ4 = VsatQ5 = Vsat.
[0018]
Thus, the charge / discharge amplitude Vw has V1 dependency. For this reason, the oscillation frequency has V1 dependency and fluctuates when the power supply voltage V1 fluctuates. Therefore, in order to stabilize the oscillation frequency, it is necessary to provide a regulator and stabilize V1. Further, the amplitude Vw includes a term of Vsat. Vsat is a characteristic of the transistor, and is easily affected by temperature. Therefore, there is a problem that the oscillation frequency is likely to change depending on the temperature.
[0019]
The voltage VH must satisfy the following condition so as not to hinder the on operation of the transistors Q2 and Q3.
[0020]
VH <V1-VbeQ3-VceQ2 + VbeQ2 = V1-VceQ2
Here, Vbe is a base-emitter voltage, and VbeQ3 = VbeQ2.
[0021]
Similarly, VL is also restricted by VL> VbeQ2 + VceQ9. Further, the amplitude of charge / discharge is Vw, and VL + Vw = VH <V1−VceQ2.
[0022]
Therefore, V1> VL + Vw + VceQ2> VbeQ2 + VceQ9 + Vw + VceQ2 = Vw + Vbe + 2Vce
It is necessary to satisfy. Therefore, if Vw is to be increased, a considerably large voltage is required as V1. Furthermore, the regulated voltage provided with the regulator is lower than the power supply voltage V1. Therefore, when battery driving, especially 1.5V is used as the power supply voltage, Vw cannot be sufficiently obtained, and it is difficult to sufficiently operate the circuit.
[0023]
The present invention has been made in view of the above problems, and an object of the present invention is to provide an oscillation circuit that can perform stable oscillation and can operate even when the power supply voltage is low.
[0024]
[Means for Solving the Problems]
The present invention includes a differential amplifier connected to a first constant current source and including first and second differential transistors, and a first resistor provided in a current path of the first differential transistor, A voltage reflecting a difference in voltage drop generated depending on whether a constant current flowing in the first constant current source flows or not flows in the first resistor according to ON or OFF of the differential transistor is set to a base of the second differential transistor. a first voltage control means for applying to, flowing a constant current during oN of the second differential transistor, a second current regulating means does not flow a constant current during off of the second differential transistor, the second includes a second resistor and a capacitor connected in parallel a constant current of the constant current means is supplied, a charge in the capacitor in accordance with the constant current of said second constant current means during the on of the second differential transistor And performs discharging of the capacitor via the second resistor during the off of the second differential transistor, a second voltage control to apply a voltage that varies with the charge and discharge of the capacitor to the base of the first differential transistor Means for controlling the second and first differential transistors by the first and second voltage control means to determine a voltage difference applied to a base of the second differential transistor. A voltage difference due to charging / discharging of the capacitor applied to the base of the first differential transistor is set to a value independent of the power supply voltage determined by the product of the constant current value flowing through the current source and the resistance value of the first resistor. Also, by setting the value to be independent of the power supply voltage, an oscillation signal having a predetermined frequency independent of the power supply voltage is obtained from the output of the differential amplifier.
[0025]
Thus, the difference between the voltage set to the base of the second differential transistor becomes a voltage corresponding to the voltage drop across the first differential transistor is generated in the first resistor when on. Therefore, the value is determined by the product of the resistance value of the first resistor and the current value that flows when the first differential transistor is turned on, and does not depend on the power supply voltage. As a result, the oscillation frequency of the circuit does not depend on the power supply voltage, and therefore a regulator or the like for making the power supply voltage constant is unnecessary, and the circuit is simplified. In addition, since a regulator is not required, the power supply voltage can be used as it is, restrictions on the voltage are relaxed, and operation with a low voltage power supply becomes easy. Furthermore, since the voltage difference is determined by the resistance value and the constant current, the oscillation frequency is not affected by the characteristics of the transistor, and a stable operation can be ensured.
[0026]
Furthermore, there is provided a third constant current means for always passing a predetermined current through a resistor provided in the current path of the first differential transistor, and a voltage drop caused by the current of the third constant current means is applied to the second constant current means. It is preferable to add and apply to the base of the differential transistor. Thus, when the power is turned on, the second differential transistor can be turned off and the first differential transistor can be turned on by the current flowing through the third constant current means, so that stable operation is guaranteed.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0028]
FIG. 1 is a diagram illustrating an example of a voltage controlled oscillation circuit according to the embodiment. NPN-type differential transistors (first and second differential transistors) Q11 and Q12 have their emitters connected to each other, and the emitters connected to the ground via an NPN transistor Q20. The base of this transistor Q20 is connected to the base of an NPN transistor Q19 whose collector and base are short-circuited. The emitter of this transistor Q19 is connected to the ground, and the collector is connected to a constant current source I11 for supplying a constant current I11. Via a power source V1. Accordingly, the transistor Q19 causes the constant current I11 of the constant current source (first constant current source) I11 to flow, and this current flows to the transistor Q20.
[0029]
The collector of the transistor Q12 is connected to the collector of the PNP transistor Q17, and the emitter of the transistor Q17 is connected to the power source V1. In the transistor Q17, the base collector is short-circuited. The base of the transistor Q17 is connected to the base of the PNP transistor Q18, and the emitter of the transistor Q18 is connected to the power supply V1. Therefore, the transistors Q17 and Q18 constitute a current mirror.
[0030]
The collector of the transistor Q18 is connected to the collector of an NPN transistor Q16 whose collector base is short-circuited. The emitter of the transistor Q16 is connected to the ground.
[0031]
The base of this transistor Q16 is connected to the base of an NPN transistor Q15, the emitter of this transistor Q15 is connected to the ground, and the transistors Q16 and Q15 constitute a current mirror. Therefore, when the transistor Q12 is turned on, the current flows through Q17, Q18, Q16, and Q15.
[0032]
The bases of the NPN transistors Q14 and Q13 are connected to the collector of the transistor Q15. Accordingly, when the transistor Q15 is turned on, the transistors Q14 and Q13 are turned off.
[0033]
The transistor Q13 has a collector base that is short-circuited, an emitter connected to the ground, and a collector connected to a power source V1 via a constant current source (second constant current source) I10. The emitter of the transistor Q14 is connected to the ground, and the collector is connected to the power source V1 via the resistor R (second resistor) 11 and the capacitor C11. Further, a point B, which is a connection point between the collector of the transistor Q14 and the capacitor C11 and the resistor R11, is connected to the base of the transistor Q11.
[0034]
Accordingly, the transistors Q13 and Q14 are turned on when the transistor Q15 is off, the capacitor C11 is charged by the current flowing through the transistor Q14, the potential at the point B is lowered, and the transistors Q13 and Q14 are turned off when the transistor Q15 is on. The capacitor C11 is discharged by the current from the power source V1 through the resistor R11, and the B point voltage rises.
[0035]
The collector of the transistor Q11 is connected to the power source V1 via a resistor (first resistor) R12, and the intermediate point between the collector of the transistor Q11 and the resistor 12 is connected to the base of the transistor Q12 and a constant current I12 flows. Current source (third constant current source) I12 is connected to the ground.
[0036]
Accordingly, the point A potential, which is the base potential of the transistor Q12, is set when the transistor Q11 is off.
VH = V1-R12 * I12
And
When transistor Q11 is off,
VL = V1-R12 * (I11 + I12)
It becomes.
[0037]
The bases of the transistors Q17 and Q18 are connected to the base of the PNP transistor Q22. The emitter of the transistor Q22 is connected to the power supply V1, and the collector is connected to the ground via the resistor R13. Therefore, the transistor Q22 passes the same current as the transistors Q12 and Q17. An intermediate point between the transistor Q22 and the resistor R13 is an output terminal. When the transistor Q22 is off, the output is the ground voltage (L). When the transistor Q22 is on, the voltage is I11 * R13 (H )
[0038]
In such a circuit, (i) when the power is turned on, the point B voltage VB becomes higher than the point A voltage where there is a voltage drop due to the current of the constant current source I12. (Ii) Therefore, the transistor Q11 is turned on, and the transistors Q12, Q17, Q18, and Q15 are turned off. As a result, the transistors Q13 and Q14 are turned on, the potential at the point B corresponding to the lower side of the capacitor C11 is lowered, and charging of the capacitor C11 is started. The charging current is a current obtained by subtracting the current (V1−VB) / R11 flowing through the resistor R11 from the current I10 flowing through the transistor Q14.
[0039]
(Iii) VB falls due to the charging of the capacitor C1. (Iv) When the voltage VB reaches VL, the transistor Q11 is turned off and the transistor Q12 is turned on. Transistors Q17, Q18, and Q15 are turned on, and transistors Q13 and Q14 are turned off. Further, when the transistor Q11 is turned off, the point A voltage VA is set to VH. (Iv) When the transistor Q14 is turned off, charging of the capacitor C11 is stopped, and the current flowing through the resistor R is gradually discharged, and the voltage at the point B gradually increases. (Vi) When the point B voltage rises and reaches VH, the operation returns to (ii), and the circuit oscillates repeatedly.
[0040]
Therefore, as shown in FIG. 2, the point B voltage repeats VH → VL → VH →..., And when the voltage drops (when the capacitor C11 is charged), the output is L and the voltage is When rising (during discharging of the capacitor C11), the output becomes H.
[0041]
In such a circuit, oscillation is performed by charging / discharging of the capacitor C11, and the oscillation frequency is determined by the charging / discharging amplitude Vw = VH−VL, the charging current value, the capacitance value C11 of the capacitor C11, and the resistance value R11. Is done.
[0042]
Here, the amplitude of charge / discharge , Vw, is Vw = VH−VL = V1−R11 * I12− {V1−R11 * (I11 + I12)}
= I11 * R11. Accordingly, the dependency of the power supply voltage V1 on the charge / discharge amplitude Vw is eliminated. Therefore, the dependency of the oscillation frequency on the power supply voltage V1 is eliminated, and a regulator for eliminating the influence of fluctuations in the power supply voltage becomes unnecessary. Further, there is no influence of the saturation voltage between the collector and emitter of the transistor. Therefore, the influence of the transistor characteristics is eliminated, and the temperature dependence can be easily eliminated.
[0043]
Furthermore, the constraints coming from the voltages VH and VL are
VH <V1-VbeQ7-VceQ2 + VbeQ2 = V1-VceQ2
Here, VbeQ7 = VbeQ2.
[0044]
Similarly, VL is also constrained by VL> VbeQ1 + VceQ10 = VbeQ1 + VceQ10. Moreover, the amplitude of charging / discharging is Vw,
VL + Vw = VH <V1−VceQ2.
[0045]
Therefore, V1> VL + Vw + VceQ2> Vw + VbeQ2 + VceQ10 + VceQ2 = Vw + Vbe + 2Vce
Thus, the conditions to be satisfied are the same as those of the conventional circuit of FIG. However, as described above, a regulator is not necessary, and it can be used even when the power supply voltage is more constant. For example, the present invention can be suitably applied to a circuit in which the power supply voltage is 1.5 V, which is the voltage of one dry cell.
[0046]
In the above circuit, the constant current source I12 is provided, but it may be omitted. If this is omitted, VH = V1 and the transistor Q11 is not guaranteed to be turned on when the power is turned on, and the initial operation becomes unstable. However, there is no problem after the normal operation starts.
[0047]
Further, by changing the constant current source I11 according to the input voltage, an operation as a voltage controlled oscillator is performed.
[0048]
As described above, according to the circuit of the present embodiment, the oscillation frequency does not depend on the power supply voltage. Therefore, a regulator for making the voltage constant is unnecessary, and the circuit is simplified. In addition, since a regulator is not required, the power supply voltage can be used as it is, the restriction on the voltage is relaxed, and the operation with the constant voltage power supply becomes easy. Further, the oscillation frequency is not affected by the characteristics of the transistor, and stable operation can be ensured.
[0049]
【The invention's effect】
As described above, according to the present invention, the difference in voltage set at the base of the first differential transistor is the voltage corresponding to the voltage drop generated in the resistor when the second differential transistor is on. become. Therefore, the value is determined by the product of the resistance value and the current value of the differential amplifier, and does not depend on the power supply voltage. As a result, the oscillation frequency of the circuit does not depend on the power supply voltage, and therefore a regulator or the like for making the power supply voltage constant is unnecessary, and the circuit is simplified. In addition, since a regulator is not required, the power supply voltage can be used as it is, the restriction on the voltage is relaxed, and the operation with the constant voltage power supply becomes easy. Furthermore, since the voltage difference is determined by the resistance value and the constant current, the oscillation frequency is not affected by the characteristics of the transistor, and a stable operation can be ensured.
[0050]
Furthermore, a second constant current means is provided, and a voltage that has dropped due to the current of the second constant current means is added to the base of the second transistor and applied to the second constant current means when the power is turned on. The second differential transistor can be turned off and the first differential transistor can be turned on by the current flowing in the circuit, so that stable operation is guaranteed.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a circuit configuration of an embodiment.
FIG. 2 is a diagram illustrating the operation of the circuit of the embodiment.
FIG. 3 is a diagram illustrating a circuit configuration of a conventional example.
FIG. 4 is a diagram for explaining the operation of a conventional circuit.
[Explanation of symbols]
Q11 to Q22 transistors, I10 to I13 constant current sources, C11 capacitors, R11 to R13 resistors.

Claims (2)

A differential amplifier connected to the first constant current source and including first and second differential transistors;
Whether a constant current flowing through the first constant current source flows through the first resistor in response to ON or OFF of the first differential transistor, including a first resistor provided in a current path of the first differential transistor First voltage control means for applying a voltage reflecting a difference in voltage drop caused by whether or not to flow to the base of the second differential transistor;
Flowing a constant current during ON of the second differential transistor, and a second constant current means during off of the second differential transistor does not flow a constant current, the constant current of the second constant current means is supplied includes a second resistor and a capacitor connected in parallel, and to charge the capacitor in accordance with the constant current of said second constant current means during the on of the second differential transistor, when turned off in the second differential transistor said second resistor via performs discharging of the capacitor, the second voltage control means for applying a voltage that changes with the charging and discharging of the capacitor to the base of the first differential transistor at,
Have
Controlling the second and first differential transistors by the first and second voltage control means ;
The voltage difference applied to the base of the second differential transistor is set to a value that does not depend on the power supply voltage determined by the product of the constant current value flowing through the first constant current source and the resistance value of the first resistor. By setting the voltage difference due to charging / discharging of the capacitor applied to the base of the first differential transistor to a value independent of the power supply voltage, an oscillation signal having a predetermined frequency independent of the power supply voltage is obtained at the output of the differential amplifier. Oscillator circuit. The circuit of claim 1, wherein
And third constant current means for constantly flowing a predetermined current through a resistor provided in the current path of the first differential transistor,
An oscillation circuit for adding a voltage dropped due to the current of the third constant current means to the base of the second differential transistor and applying it.

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