JPH0685625A - Oscillator - Google Patents

Abstract

PURPOSE:To provide a voltage control oscillator which can output the stable oscillation frequency regardless of the change of the power voltage and the temperature and the production variance. CONSTITUTION:The charging and discharging operations are repeated by the power current means Ic and Id and the signal of the prescribed frequency is outputted. So that the voltage of a capacitor C1 is kept between the upper and lower limit levels which are decided by the voltage detector means 42 and 43. Under such conditions, the voltage detector means 62 and 63 having the game characteristics as the means 42 and 43 are provided and the current values of both means Ic and Id are corrected in response to the variance of both means 62 and 63.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to oscillators, and in particular
The present invention relates to an oscillator which can obtain a stable oscillation frequency against fluctuations in power supply voltage, fluctuations in temperature, and manufacturing variations.

[0002]

2. Description of the Related Art A voltage controlled oscillator that controls the charging and discharging current amount to a capacitor by an input voltage, determines charging or discharging according to a result of detection of an output voltage of the capacitor by a comparator, and outputs a triangular wave is conventionally known. It was realized by the configuration as shown in.

The basic structure will be described with reference to FIG.

Charging current source I71 and discharging current source I7
The current value of 2 is controlled by the input voltage Vc. The capacitor C71 integrates the charging and discharging currents to generate the output voltage 71.

V71, V72, and V73 are inverter gates. The threshold voltage of the inverter gate V72 is high, and the threshold voltage of the inverter gate V71 is low.

NAND gate N71 and NAND gate N7
2 constitutes an SR latch. And switch S
The switch 71 and the switch S72 are configured to be turned on and off according to the output signal 74 of the NAND gate N71.

Next, the operation will be described with reference to FIG.

Now, it is assumed that the output signal 74 of the NAND gate N71 is at a high level, the switch S71 is ON, and the switch S72 is OFF.

In this state, the capacitor C71 is charged by the output current of the charging current source I71 and its output voltage 71 rises. Output voltage 71 is inverter gate V
When the threshold voltage of 72 is reached, the output signal 72 of the inverter gate V72 becomes low level. Then,
The output of the NAND gate N72 becomes high level, and the output signal 74 of the NAND gate N71 becomes low level. As a result, the switch S71 is turned off and the switch S72 is turned off.
Turns on. Then, conversely, the electric charge stored in the capacitor C71 is discharged through the discharge current source I72, and the output voltage 71 thereof starts to decrease.

The output voltage 71 is the inverter gate V71.
When the output voltage 73 of the inverter gate V73 becomes low level, the output signal 73 of the inverter gate V73 becomes low level. Then,
The output signal 74 of the NAND gate N71 becomes high level, and the output of the NAND gate N72 becomes low level. As a result, the switch S71 is turned on again and the switch S72 is turned off again. Then, again, the capacitor C
71 is charged by the charging current source I71, and the output voltage 7
1 goes up.

By repeating the above operation,
The output voltage 71 of the capacitor C71 is the threshold voltage of the inverter target V72 and the inverter target voltage V7.
It varies between one threshold voltage and. That is, the circuit oscillates and the output voltage waveform of the capacitor C71 becomes a triangular wave.

The triangular wave also becomes a rectangular wave by passing through a comparator such as an inverter. In this type of voltage controlled oscillator, the output signal frequency fo is expressed as follows.

[0013]

[Equation 1]

In the equation (1), Ic is the current source I
71 and the current value of I72, ΔV is the inverter gate V7
1 and the threshold voltage difference of the inverter gate V72.

[0015]

In the above prior art, the correlation between the threshold voltage difference ΔV between the inverter gates V71 and V72 and the charging / discharging current value Ic to the capacitor C71 was not taken into consideration. Therefore, when the threshold voltage difference ΔV and the charging / discharging current value Ic vary due to manufacturing variations, power supply voltage variations, and temperature variations, there is a problem that a stable output signal frequency fo cannot be obtained.

An object of the present invention is to overcome the above-mentioned problems of the prior art and provide a voltage controlled oscillator that can obtain a stable output frequency without depending on semiconductor manufacturing variations, power supply voltage variations, temperature variations, and the like. Especially.

[0017]

The present invention has been made to achieve the above object, and in one aspect thereof, a capacitance for integrating a current, a first reference voltage (VH), and the first reference voltage (VH).
A reference voltage means having a second reference voltage (VL) lower than the reference voltage, and an integrated output voltage (V) of the capacitance,
Based on the result of the comparison by the comparator that compares the magnitude relationship with the first and second reference voltages and the comparator,
From the state of V <VH, V ≧ VH
When it is detected that the state has changed to the state of, the above capacity is discharged with a current of a predetermined value,
An oscillator configured to include a current power supply means for charging the capacitance with a current having a predetermined value when detecting a change in a state of VL ≧ V, wherein the current power supply means is capable of adjusting the current value. And a correction means for changing the current value of the charge and the current value of the discharge by the current power supply means according to the difference voltage between the first reference voltage and the second reference voltage. An oscillator is provided.

The correction means includes difference voltage generation means for generating the difference voltage, and control means for changing the current value of the current power supply means in accordance with the difference voltage generated by the difference voltage generation means. May be composed of

The correction means includes second reference voltage generation means having the same reference voltage as the reference voltage generation means.
The difference voltage generating means may output the difference between the first reference voltage and the second reference voltage of the second reference voltage generating means as the difference voltage.

In this case, it is preferable that the reference voltage generating means and the second reference voltage generating means have the same circuit structure inside. Further, the reference voltage generating means and the second reference voltage generating means are
It is preferable that they are formed on the same substrate.

The second reference voltage generating means is C
It is preferable that the structure includes a MOS inverter circuit. In this case, the second reference voltage generating means has the CMOS inverter circuit for each reference voltage, and the output terminal and the input terminal of each CMOS inverter circuit are short-circuited. It is preferable.

[0022]

The comparator compares the magnitude relationship between the integrated output voltage (V) of the capacitance and the first and second reference voltages.
The current power supply means performs the following charging / discharging operation based on the result.

When the state of V <VH changes to the state of V ≧ VH, the discharge of the above capacity is started with a current of a predetermined value.

When the state of VL <V is changed to the state of VL ≧ V, the above capacity is charged with a current of a predetermined value.

As a result, the integrated voltage of the capacitance is
And the second reference voltage with a periodicity. That is, it oscillates a signal of a predetermined frequency.

In the state where such an oscillating operation is performed, the following correction control is performed in parallel with this.

In this case, since the second reference voltage generating means and the first reference voltage generating means are collectively made on the same substrate, these first and second reference voltages are 1 is almost the same as that generated by the reference voltage generating means. Further, since it is configured to include the CMOS inverter circuit, the reference voltage can be accurately generated by short-circuiting the input / output terminals.

The difference voltage generating means outputs the difference between the first reference voltage and the second reference voltage of the second reference voltage generating means as the difference voltage. Then, the control means changes the control value of the current power supply means according to the difference voltage. As a result, even during the oscillation operation of the oscillator, it is possible to perform correction control in response to temperature fluctuations, manufacturing variations, and power supply voltage fluctuations without interfering with the oscillation operation.

[0029]

An embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, the voltage controlled oscillator of this embodiment has a voltage / current conversion circuit 8, current sources Ic and Id, a current switch S1, a capacitor C1, a comparator 2, and V.
H detection circuits 42 and 62, VL detection circuits 43 and 63, S-
It is composed of an R latch 4 and a differential voltage generation circuit 6.

The capacitor C1 integrates the output currents of the current sources Ic and Id to generate an integrated voltage 11.

The VH detection circuit 42 detects whether the integrated voltage 11 of the capacitor C1 exceeds the high level threshold voltage VH. When it exceeds, the high level detection signal 13 is output. On the other hand, the VL detection circuit 43 detects whether or not the integrated voltage 11 exceeds the low level threshold voltage VL, and when it exceeds, outputs the low level detection signal 14.

The comparator 2 also detects whether the integrated voltage 11 exceeds the reference voltage VT of the comparator 2 itself, and outputs the detection result as a rectangular wave. The "comparator" in the claims is realized not inside the comparator 2 but inside the VH detection circuit 42 and the VL detection circuit 43.

The SR latch 4 turns on / off the switch S1 according to the high level detection signal 13 output from the VH detection circuit 42 and the low level detection signal 14 output from the VL detection circuit 43. The "current power supply means" referred to in the claims is a concept including not only the current sources Ic and Id but also the SR latch 4 and the switch S1.

The oscillator of this embodiment has threshold voltages of the VH detection circuit 42 and the VL detection circuit 43 (note: as will be described later, the VH detection circuit 62 corresponding to these threshold voltages is actually used.
And the threshold voltage of the VL detection circuit 63), the output control current Io for controlling the current source Ic and the current source Id is corrected. Hereinafter, the configuration in this respect will be described.

VH detection circuit 62 and VL detection circuit 63
Are the threshold voltages VH and VL of the VH detection circuit 42.
This is for generating a threshold voltage corresponding to the threshold voltage VL of the detection circuit 43. In principle, it is preferable to take out the threshold voltage directly from the VH detection circuit 42 and the VL detection circuit 43. However, since it is difficult to extract the threshold voltage during the operation of the oscillator, in the present embodiment, the VH detection circuit 62 and the VL detection circuit 6 having the same configurations as these are used.
3 is provided, and the threshold voltage is used instead of both.

In this embodiment, the threshold voltage is accurately generated by short-circuiting the input and output of the VH detection circuit 62. VH detection circuit 62 and VH detection circuit 4
Since 2 is a circuit configured separately, the threshold voltages of both do not completely match. However, in this embodiment, the VH detection circuit 62 and the VH detection circuit 42 are collectively formed on the same substrate, so that the threshold voltages of both are substantially equal. That is, the VH detection circuit 62 and the VH detection circuit 42
Are formed at the same time, so that the deviation of the manufacturing conditions or the like acts on both of them in substantially the same manner. Therefore, at least between the VH detection circuit 62 and the VH detection circuit 42 included in the same oscillator, the threshold voltages can be substantially the same. Similarly, the threshold voltages of the VL detection circuit 43 and the VL detection circuit 63 are matched. The VH detection circuit 62 and VL
A specific circuit configuration of the detection circuit 63 will be described later with reference to FIG.

The differential voltage generation circuit 6 detects a difference voltage VD between the high level threshold voltage VH generated by the VH detection circuit 62 and the low level threshold voltage VL generated by the VL detection circuit 63, and a voltage VDG proportional to the difference voltage VD. It has a function of generating and outputting (hereinafter, referred to as “proportional double voltage VDG”). The specific circuit configuration of the difference voltage generation circuit 6 will be described later with reference to FIGS. 6 and 7.

The voltage-current conversion circuit 8 is the "control means" referred to in the claims. The voltage-current conversion circuit 8
Converts the input control voltage VIN into the output control current Io with reference to the proportional double voltage VDG, and outputs the current sources Ic and Ic.
output to d. The input control voltage VIN is input by a circuit not shown in the figure and corresponds to the frequency of the signal to be output by the oscillator. In this embodiment, the oscillation frequency is changed according to the voltage, that is, the input control voltage. However, if the current / current conversion circuit is used instead of the voltage / current conversion circuit 8, the input control current is changed. It is of course possible to change the oscillation frequency accordingly. A specific circuit configuration of the voltage-current conversion circuit 8 will be described later with reference to FIGS. 8 and 9.

The current sources Ic and Id are output control current Io.
The current value is changed according to. In the present embodiment, the case where the ratio between the current values Ic and Id is 1: 2 will be described, but other ratios may of course be used.

VH detection circuits 42 and 62, VL detection circuit 4
3, 63 and the internal configuration of the comparator 2 will be described with reference to FIG.

FIG. 2A shows the circuit configuration of the VL detection circuits 43 and 63. VL detection circuit 4 of this embodiment
3, 63 are constructed by connecting CMOS inverters in two stages. One is the PMOS transistors M1 and NMO
CMOS inverter composed of S transistors M5 and M9
It is Others are PMOS transistor M2 and NMOS
It is a CMOS inverter composed of a transistor M6. As described above, according to the present embodiment, the CMOS inverter is adopted, so that there is no possibility that the element is destroyed even if the input and output are short-circuited.

FIG. 2B shows a circuit configuration of the comparator 2. The comparator 2 is a CM including a PMOS transistor M3 and an NMOS transistor M7.
It is composed of an OS inverter.

FIG. 2C shows the circuit configuration of the VH detection circuits 42 and 62. VL detection circuit 42, 62
Is a CMOS inverter composed of PMOS transistors M4 and M10 and an NMOS transistor M8. As described above, according to the present embodiment, the CMOS inverter is adopted, so that there is no possibility that the element is destroyed even if the input and output are short-circuited.

Here, the size ratio of the transistors M1 and M5, the size ratio of the transistors M3 and M7, and the size ratio of the transistors M4 and M8 are made equal. Further, a transistor M9 and a transistor M10 are provided, and the VL detection circuits 43 and 63 and the comparator circuit 2 are provided.
Of the threshold voltages VL, VT, and VH between the VH detection circuit 42 and the VH detection circuit 42 and VL <VT <
It is set to VH (see FIG. 3). Note that FIG. 3 shows the VL detection circuits 43 and 63, the comparator circuit 2, and the VH detection circuit 4.
It is a graph which shows the input / output characteristic of 2,62. The horizontal axis represents the integrated voltage 11 which is the input voltage, and the vertical axis represents the output voltage of each.

Next, the internal structure of the SR latch 4 will be described with reference to FIG. The S-R latch 4 is a known one composed of two NAND gates. The inputs are the high level detection signal 13 and the low level detection signal 14, and the output is the switch control signal 15.

Next, the oscillation operation of the oscillator of this embodiment will be described with reference to FIG. However, here, it is assumed that the output control current Io is constant, without considering the correction control by the difference voltage generation circuit 6, the voltage-current conversion circuit 8 and the like, which is the feature of this embodiment. The correction control of the output control current Io will be described in detail later.

If the switch S1 is open now, the current Ic flows from the current source Ic into the capacitor C1 and the capacitor integrated voltage 11 increases. When the high-level threshold voltage VH is reached, the high-level detection signal 13 which is an output signal for VH detection becomes "L", and the switch control signal 15 which is the output of the SR latch 4 becomes "H". As a result, the switch S1 is closed and the capacitor C
A differential current (Id-Ic) between the current sources Id and Ic is drawn from 1. Here, if the current value of the current source Id is set to twice the current value of the current source Ic, the current of the current value Ic is drawn from the capacitor C1.

The integrated voltage 11 of the capacitor C1 decreases,
When the low level threshold voltage VL is reached, the low level detection signal 14 which is the output signal for VL detection becomes "L" and the switch control signal 15 becomes "L". As a result, the switch S1 is opened, and the current Ic flows from the current source Ic into the capacitor C1 again.

The oscillation operation is performed by repeating the above operation. Although the waveform of the integrated voltage 11 is a triangular wave, it is also possible to obtain a rectangular wave oscillation output signal 12 by using the comparator 2. The oscillation frequency fo at this time is expressed by the following equation.

[0051]

[Equation 2]

Here, the voltage VD is a difference voltage between the high level threshold voltage VH and the low level threshold voltage VL.

Next, the correction control operation of the output control current Io, which is a feature of this embodiment, will be described.

The VH detection circuit 62 generates a high level threshold voltage VH because its input and output are short-circuited.
Similarly, the VL detection circuit 63 also generates the low level threshold voltage VL. Then, these two voltages are input to the differential voltage generation circuit 6.

Then, the difference voltage generation circuit 6 generates a proportional double voltage VDG according to the difference between the two voltages (difference voltage VD) and outputs it to the voltage / current conversion circuit 8. The voltage-current conversion circuit 8 corrects the output control current Io according to the proportional voltage VDG and then outputs it to the current sources Ic and Id to control them. For example, when the difference voltage VD is large due to temperature fluctuation or manufacturing variation, the charging / discharging current to the capacitor C1 is corrected to be large. As a result, it is possible to cancel the variation of the difference voltage and maintain a constant frequency. Also, when the difference voltage changes due to the fluctuation of the power supply voltage VCC, the output control current Io also changes and the oscillation frequency is kept constant.

Finally, a detailed circuit configuration of each part will be described.

An example of the difference voltage generation circuit 6 is shown in FIG. The differential voltage generation circuit 6 includes PNP transistors Q13 and Q1.
4, NPN transistors Q11 and Q12, resistor R11
And R12 and current sources I11 and I12.
The current flowing through the resistor R11 is (VH-VL) / R11. Therefore, if the current values of the current sources I11 and I12 are made equal, the current flowing through the resistor R12 is 2 (VH-VL) /
It becomes R11. Therefore, the output voltage VDG is 2 (VH-V
L) R12 / R11, which is proportional to the difference voltage (VH-VL).

Another example of the differential voltage generating circuit 6 is shown in FIG.
In this example, PNP transistors Q23 and Q24, NPN
It is composed of transistors Q21 and Q22, operational amplifiers OP21 and OP22, and resistors R21, R22, and R23. The high level threshold voltage VH is the operational amplifier OP
21 and is applied to the resistor R21. The low level threshold voltage VL is input to the operational amplifier OP22 and applied to the resistor R22. Here resistors R21 and R2
If the values of 2 are made equal, the current flowing through the resistor R23 is (VH-VL) / R21 and the output voltage VDG is (VH-V).
L) R23 / R21, which is proportional to the difference voltage (VH-VL). Therefore, in both cases of FIG. 6 and FIG. 7, the output voltage V
DG is expressed as Equation 3 using the proportionality constant k1.

[0059]

[Equation 3]

Next, an example of the voltage-current conversion circuit 8 will be described with reference to FIG. PNP transistors Q32, Q33, Q
40, Q41, NPN transistors Q31, Q34, Q
35, Q36, Q37, Q38, Q39, operational amplifier O
P31, resistors R31, R32, R33, R34, R3
5, R36 and bias voltage VB. The difference voltage VDG input from the difference voltage generation circuit 6 is the operational amplifier O.
It is input to P31 and applied to the resistor R31. The current generated here is returned by the current mirror circuit composed of PNP transistors Q32 and Q33, and again by the current mirror circuit composed of NPN transistors Q34, Q35, Q36 and Q37. For simplification, the PNP transistors Q32 and Q33 have the same size, and the NPN transistors Q34, Q35, Q36, and Q3.
7 have the same size and resistors R32, R33, R34, R3
Assuming that 5 and 5 have the same resistance value, transistors Q35 and Q
The collector current flowing through 36 and Q37 is VDG / R31.
It is represented by. And Q38 and Q3 which constitute the differential amplifier
9. Input control voltage VIN and bias voltage VB to R36
Enter. The current flowing through the resistor R36 is (VIN-V
B) / R36, and the output control current Io is Io = VD
It is represented by G / R31 + 2 (VIN-VB) / R36.
If the current value Ic of the current source Ic is set to k2 times the output control current Io, Ic = k2 × Io. Center frequency is V
When IN = VB, at this time Ic = k2 × VDG / R
It becomes 31. Therefore, the center frequency foc is expressed by the following equation.

[0061]

[Equation 4]

As can be seen from the equation 4, the center frequency f
oc does not depend on the high-level threshold voltage VH and the low-level threshold voltage VL.

FIG. 9 shows another example of the voltage-current conversion circuit 8. In this example, the voltage-current conversion circuit 8 includes PNP transistors Q52, Q53, Q59, Q60, NPN transistors Q51, Q54, Q55, Q56, Q57, Q5.
8, operational amplifier OP51, resistors R51, R52, R5
3, R54, and bias voltage VB. Similar to FIG. 8, the voltage VDG input from the differential voltage generation circuit 6 is input to the operational amplifier OP51 and applied to the resistor R51. The current generated here is the PNP transistor Q5
It is folded back by the current mirror circuit composed of 2 and Q53, and is folded back again by the current mirror circuit composed of NPN transistors Q54, Q55 and Q56. For the sake of simplicity, the PNP transistors Q52 and Q53 have the same size, and the NPN transistors Q54, Q55 and Q56,
Is the same size and the resistors R52, R53, R54 have the same resistance value, the collector current flowing through the transistors Q55, Q56 is represented by VDG / R51. The input control voltage V is applied to Q57 and Q58 which constitute the differential amplifier.
IN and bias voltage VB are input. At this time, the output control current Io is Io = VDG / R51 (1 + q (VIN−
It is represented by VB) / k × T). Here, q is the electron charge amount, k is the Boltzmann constant, and T is the absolute temperature. If the current value Ic of the current source Ic is set to k2 times the output control current Io, Ic = k2 × Io. Therefore, the output oscillation frequency fo of the voltage controlled oscillator is expressed by the following equation,

[0064]

[Equation 5]

As can be seen from the equation 5, the oscillation frequency fo
Has a characteristic shown in FIG. 10 without depending on the high level threshold voltage VH and the low level threshold voltage VL. The center frequency when the input difference voltage VIN-VB is zero is k1 × k2 / (2 × R31 × C1) or k1 × k2 / (2 × R51 × C1).

As described above, the VH detection circuit 4
2 and the error in the oscillation frequency due to the manufacturing variation of the VL detection circuit 43 can be reduced. Further, even if the high level threshold voltage and the low level threshold voltage fluctuate due to temperature fluctuations and power supply voltage fluctuations, the oscillation frequency does not fluctuate.

The configurations of the respective parts described in the description of the above embodiments are merely examples of the present invention, and other circuit configurations may be adopted as long as the same control can be performed.

[0068]

According to the present invention, even if the high level threshold voltage and the low level threshold voltage fluctuate due to variations in semiconductor manufacturing, power supply voltage fluctuations, and temperature fluctuations, the oscillation frequency of the voltage controlled oscillator fluctuates. There is no stable frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an oscillator.

FIG. 2 shows VL detection circuits 42 and 62, a comparator 2, and V.
It is a circuit diagram which shows the internal structure of H detection circuit 43,63.

FIG. 3 is a diagram showing VL detection circuits 42 and 62, a comparator 2, and V.
6 is a graph showing characteristics of H detection circuits 4 and 63.

FIG. 4 is a circuit diagram showing an internal configuration of an SR latch 4.

FIG. 5 is an explanatory diagram showing the operation of the voltage controlled oscillator.

FIG. 6 is a circuit diagram showing an example of a difference voltage generation circuit 6.

FIG. 7 is a circuit diagram showing another example of the differential voltage generation circuit 6.

FIG. 8 is a circuit diagram showing an example of a voltage-current conversion circuit 8.

FIG. 9 is a circuit diagram showing another example of the voltage-current conversion circuit 8.

FIG. 10 is a graph showing the input / output characteristics of the voltage controlled oscillator.

FIG. 11 is a circuit diagram showing a configuration of a conventional voltage controlled oscillator.

FIG. 12 is an explanatory diagram showing an operation of a conventional voltage controlled oscillator.

[Explanation of symbols]

VH: High-level threshold voltage VL: Low-level threshold voltage VD: Difference voltage between high-level threshold voltage and low-level threshold voltage Vin: Input control voltage Io: Output control current fo: Output signal frequency Ic: Charge current Id: Discharge Current Td: Delay time 2: Comparator 4: SR latch 6: Differential voltage generation circuit 8: Voltage-current conversion circuit 11: Integrated voltage 12: Output signal 13: High level detection signal 14: Low level detection signal 15: Switch control signal 42: VH detection circuit 43: VL detection circuit 62: VH detection circuit 63: VL detection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Hase Inventor Kenichi Hase 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Akihiko Hirano Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshida-cho, Hitachi, Ltd. Microelectronics equipment development laboratory (72) Inventor Hiroshi Kimura 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Microelectronics equipment development laboratory (72) Inventor Ken Urakami 4-6, Surugadai Kanda, Chiyoda-ku, Tokyo Inside Hitachi, Ltd.

Claims (7)

[Claims] 1. A reference voltage means having a capacitance for integrating a current, a first reference voltage (VH), and a second reference voltage (VL) lower than the first reference voltage, and a capacitance of the capacitance. Based on the result of the comparison by the comparator that compares the integrated output voltage (V) and these first and second reference voltages with each other, the magnitude relationship is changed from the state of V <VH. , When the change of V ≧ VH is detected, the capacitance is discharged with a current of a predetermined value, and when the change of the state of VL <V to the condition of VL ≧ V is detected, the capacitance is changed to a predetermined value. Current source means for charging with the current of, and the current source means capable of adjusting the current value thereof, wherein the first reference voltage and the second reference voltage are According to the differential voltage of the Oscillator according to claim, further comprising a correction means for changing the current value of the current value and the discharge of the charge. 2. The correction means includes a difference voltage generation means for generating the difference voltage, and a control means for changing the current value of the current power supply means according to the difference voltage generated by the difference voltage generation means. The oscillator according to claim 1, wherein the oscillator is configured to include. 3. The correction means includes a second reference voltage generation means having the same reference voltage as the reference voltage generation means, and the difference voltage generation means is a first reference voltage generation means included in the second reference voltage generation means. 3. The oscillator according to claim 2, wherein the difference between the reference voltage and the second reference voltage is output as the difference voltage. 4. The oscillator according to claim 3, wherein the reference voltage generating means and the second reference voltage generating means have the same circuit configuration inside. 5. The oscillator according to claim 4, wherein the reference voltage generating means and the second reference voltage generating means are formed on the same substrate. 6. The second reference voltage generating means is a CMOS
4. The oscillator according to claim 3, wherein the oscillator includes an inverter circuit. 7. The second reference voltage generating means is the CM.
7. The oscillator according to claim 6, wherein an OS inverter circuit is provided for each reference voltage, and the output terminal and the input terminal of each CMOS inverter circuit are short-circuited.