JPS62239498A - Eprom writing device - Google Patents

Abstract

PURPOSE:To use any of a synchronizing type or a synchronizing masters ROM by providing a changeover circuit to select either of a fixing level force signal and the output signal of a clock generating circuit and supply it to the chip enable terminal of an IC socket. CONSTITUTION:To a conventional circuit, the inverse of CE clock generating circuit 10, the inverse of CE signal changeover circuit 6 and a changeover switch 9 are added. For the action of the circuit, first, in case of an a synchronizing type ROM, a changeover switch is made into a low level, a low level fixing signal is given to the inverse of CE terminal 2, the signal from the inverse of CE clock generating circuit 10 is cut and reading is executed. Next, in case of a synchronizing type ROM, the changeover switch is made into the high level, a low level fixing signal is cut, the signal from the inverse of CE clock generating circuit 10 is given to the inverse of CE terminal 2, and therefore, the address signal is latched and the reading can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an EPROM writer, and particularly to a writing IC.
This relates to a signal circuit for supplying a signal to socket 1-.

[Conventional technology]

If it becomes necessary to use ROM in computer equipment or office automation equipment, it would be best to use master ROM in terms of cost. However, in the early stages of design, it is difficult to avoid design mistakes and system changes, and it is not a good idea to rush to create a master ROM. Therefore, we will promote the period leading up to the final master ROM.
A product is manufactured using OM or EPROM, and after sufficient debugging, conversion to master ROM will be considered.

EFROM can be said to meet these conditions very well. That is, the first step is to create a product based on the design and conduct various evaluation tests to identify any problems with the product. This specially used ROM is normally discarded without being used in the next design, but as a characteristic of EPROM,
By irradiating it with ultraviolet rays, it can be rewritten and used again, making it easy to respond to design changes.

An EPROM writer is a tool that allows the user to easily write to an EPROM as described above, and has the following characteristics. First, it has a buffer memory for storing write information read from the master ROM or external interface, and second, it has a buffer memory for storing write information read from the master ROM or external interface.
Thirdly, it has a function to read the written contents of the EPROM and compare the written information in the buffer memory.

FIG. 3 is a block diagram of a conventional EPROM writer. To explain the operation method shown in Fig. 3, set the master ROM in IC socket 1, and set Vco to 5V (
(normal case) and σ lower (chip enable) terminal 2
A low level signal (fixed) is applied to the master ROM to enable reading of the master ROM.

Next, the timing generation circuit 11 is activated and an address signal is applied from the address generation circuit 12 to the IC socket 1.

At this time, the address information is provided by the address counter 13, and the address counter 13 further provides the address information to the write information storage buffer 14. Read information is output from the master ROM set in the IC socket 1, stored in the data I10 buffer 15, and written to a designated address in the write information storage buffer 15. However, this conventional E'PROM
The writer uses a ROM with a reading method as shown in Figure 4.
In other words, it is a type of ROM (asynchronous ROM) in which the output is output simply by changing the address while the surface (chip enable signal) remains in the enable state (low level here).
Applicable only to However, due to reasons such as limiting the power of the master ROM, which has now increased in capacity, the ROM uses the reading method shown in Figure 5, that is, it outputs only by switching the address, but it does not output by applying a pulse clock to the σ100 terminal 3. A type of ROM (synchronous ROM) that latches an address and outputs an output corresponding to that address has become mainstream.

[Problem that the invention seeks to solve]

However, this conventional EPROM writer has some problems when reading the contents of the master ROM into the buffer memory. For example, if the master ROM is the master ROM, the EPR.

The 0M writer must have a master ROM reading function. On the other hand, master ROMs usually have two types of data readout types: one is a type in which an output appears just by determining the address (asynchronous type...see Figure 4), and the other type is a type in which an output is generated just by determining the address (see Figure 4), and the other type is a type in which the output appears when the address is determined (see Figure 4). There is a type (synchronous type...see FIG. 5) that requires a clock signal to latch the address.

Among these, the asynchronous type generally has the same read timing as the EPROM and there is no problem, but there are almost no equivalent EPROMs to the synchronous type, and therefore this type of master ROM cannot be read with a conventional EPROM writer. Ta.

An object of the present invention is to provide an EPROM that can be used as either a synchronous or asynchronous master ROM by providing a selection circuit for providing a synchronous signal or a fixed signal.
The purpose is to provide a writing device.

[Means for solving problems]

The configuration of the EPROM writer of the present invention is as follows:
Alternatively, an IC socket for setting the master ROM, a timing generation circuit for distributing I/rega timing, a clock generation circuit for generating a chip enable clock in response to the timing, a fixed level power signal and the clock generation circuit. The device is characterized in that it includes a switching circuit that selects one of the output signals and supplies it to the chip enable terminal of the IC socket.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram showing a first embodiment of the present invention. In this figure, the IC socket serves not only as a socket 1- for the EPROM to be written to, but also as a socket for reading information from the master ROM. This block diagram especially shows only the reading circuit portion of the master ROM.

The circuit shown in FIG. 1 has a configuration in which a σ1 clock generation circuit 10, a σT signal switching circuit 6, and a changeover switch 9 are added to the conventional circuit shown in FIG. In the case of an asynchronous ROM, the operation of this circuit is as follows: first, the changeover switch is set to low level, a low level fixed signal is applied to terminal 2, the signal from clock generation circuit 10 is cut off, and reading is performed. Next, in the case of a synchronous ROM, the selector switch is set to high level, the low level fixed signal is cut off, and the signal from the CE clock generation circuit 10 is given to the CE terminal 2, so the address signal can be latched and read. .

FIG. 2 is a block diagram of a second embodiment of the invention. In this figure, two ROM enable signal terminals, CE terminal 2 and OE terminal 3, are considered.

And OE terminal 3 is fixed level (Vcc and ground level)
A switching circuit 4 is connected to the one side terminal 2, and a signal polarity switching circuit 5 and a level or clock pulse switching circuit 6 are connected to the one side terminal 2. The clock pulses used here are the asynchronous type (the type that is latched by the address CE clock pulse) and the synchronous type (the CE is fixed at a low level (or high level) and the output is output only by switching the address). This is because there is a type).

Next, the operation of this circuit will be described for examples of two types of master ROMs. As a first example, σ100 is enabled at a fixed low level,
In the case of a ROM where ■ is enabled at a fixed high level,
The pitch level of the σT signal polarity changeover switch and the surface signal polarity changeover switch 5 may be set to high level, and the σT relevel clock changeover switch 9 may be set to low level. As a second example, if you need a pulse clock with a fixed high level and a negative polarity, set the σT signal polarity changeover switch sound to low level, set the σTT signal polarity changeover switch 5 to low level,
■The level/clock changeover switch 9 may be set to a high level.

〔Effect of the invention〕

As explained above, the present invention provides an EPROM writer with a built-in double clock generation circuit, a C signal switching circuit, and a changeover switch.
When reading to PR, 0M write information buffer, master R
This has the effect of making it possible to read whether the OM is an asynchronous ROM or a synchronous ROM7

[Brief explanation of drawings]

FIG. 1 is a block diagram of an EPROM writer representing a first embodiment of the present invention, FIG. 2 is a block diagram of an EPROM writer representing a second embodiment of the invention, and FIG. 3 is a block diagram of a conventional EPROM writer. FIG. 4 is a timing chart showing a read cycle of an asynchronous ROM, and FIG. 5 is a timing chart showing a read cycle of a synchronous ROM. gender switching circuit, 6... ■level/clock switching circuit, 7
... Plane signal polarity changeover switch, 8 ... Plane signal polarity changeover switch, 9 ... σ■ level/clock changeover switch, 10 ... σT clock generation circuit, 11 ... Timing generation circuit, 12.・Address generation circuit, 13・
...Address counter, 14...Write information storage module 2
Figure 4 Figure Ne S concave

Claims (1)

[Claims] An IC socket for setting a PROM to be written or a master ROM, a timing generation circuit for distributing trigger timing, a clock generation circuit for generating a chip enable clock in response to the timing, and a fixed level power signal and the output of the clock generation circuit. An EPROM writer comprising: a switching circuit that selects one of the signals and supplies the selected signal to a chip enable terminal of the IC socket.