JPS62235811A - Clock logic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to the field of clock control of CMO8 logic circuits.

[Prior art]

Most complex VL8 I circuits are implemented using synchronous logic, ie, logic that is sequentially controlled by a central clock signal. For example, almost all microprocessors use such logic.

Asynchronous logic is used only for special purposes, typically simple functions. Sequencing and writing data to memory is an example of such a function.

The present invention relates to synchronous logic, especially complementary metal-oxide-semiconductor (
It deals with CMOS) circuits.

MO8 circuits have an inherent capacity that allows for temporary storage of logic states, thereby allowing the use of low power dynamic circuits. Typically, an external clock signal is applied to the integrated circuit and several internal clock phases are generated to move the signal throughout the chip. A typical structure will be described below with reference to FIG.

〔problem〕

One problem associated with multiple clock phases is that the three phases must be distributed across the chip. Moreover, their phases must not coincide. Otherwise, a state may be moved to a device before the information stored on the device is read. Typically, "dead time" is provided between phases to avoid overlapping operations. VLS
In I circuits, the propagation time of each phase to all corners of the chip must be considered. This is because the phase propagation times are different from each other. The need to take these considerations complicates the design of VLSI circuits. In some cases, in order to ensure a certain dead time across the chip, the dead time must be increased when taking into account the propagation times of the various phases, thereby slowing down the operation of the circuit.

The present invention provides a logic device that uses a single phase clock signal. Single-phase clock signals have been used in 11 circuits, ECL circuits, and to some extent MO8 circuits.

A description of a single-phase clock device for NMOS circuits is given below.
IEEE Journal of Solid State Circulation
f5olid-5tate C1rcuits),
Vol. 5C-18, No. 2, April 1983.
Microcomputer Systems Quiz Dual Port Memory and Error Check 7
NMO8DRAM Control@r for Mi
crocomput@r Systems with
Dual-PortMemory and Erro
r Checking and Corr@ction
) (see beginning of page 168).

The present invention extends those techniques to obtain a simple approach for 0M08 circuits.

[Summary of the invention]

In this specification, complementary metal-oxide-semiconductor (C
A single phase clock logic device for integrated circuits (MOS) is described. The device includes a first logic circuit and a second logic circuit, each having an input transistor. The tlIJl logic circuit is coupled to receive an input signal, and the output signal of the first logic circuit is coupled as an input to the second logic circuit. The first logic circuit and the second logic circuit are coupled to receive clock signals of the same phase. causing a first logic circuit to receive an input signal during a first period of the clock signal; i! of the clock signal; ! so that the second logic circuit receives the output signal of the first logic circuit during the period J2,
The input transistors of the first logic circuit and the input transistors of the second logic circuit have different sizes. The first period and the second period do not overlap. In a preferred embodiment, the first and second logic circuits are D-type, level-triggered, 7-lip, 70-tube transistors, and the input transistors are n-type transistor flip-flops. For example, one logic circuit is activated when the clock signal is less than one-third of its highest potential, and the other logic circuit is activated when the clock signal is more than two-thirds of its highest potential. Ru. This leaves a safe area or safe time when neither circuit transitions.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

including methods using p-wells, n-wells and double wells;
A number of CMO8 integrated circuit fabrication methods can be used to fabricate the device of the present invention.

A conventional 0MO8 logic device is shown in FIG. This device consists of a series-coupled D-type bistable circuit (flip 70
This is a dynamic realization of Tsugu. The input signal on line 10 is clocked through transistors 6 and 7 and stored in the parasitic capacitance at the input node of inverter 12. The output of this inverter is the transistor 18.19
It is stored in the parasitic capacitance of the inverter 140 input circuit point as controlled by the t-clock. The output signal from the logic device is provided on line 15.

In FIG. 1, timing signals φ0. φ2 and the complementary signals of these timing signals are mutually opposite in phase and are usually generated from an external clock signal applied to the chip. For example, during a first period determined by timing signal φl, a signal on line 10 is applied to the input of inverter 12 via transistors 16 and 17. During that first period, Ruru data can also be detected at 1!15. Then, during a second period determined by timing signal φ2, the data at the output terminal of inverter 12 is coupled through transistor 1i19 to the input point of inverter 14. New data can be applied to line 10 during that second period. From the circuit of FIG. 1, if transistors 16 and 17, 18 and 19 conduct simultaneously, I! before the data stored at the input of inverter 12.14 is read. The data on 10 is combined through inverter 12.14. For this reason, the timing signal φ1. The clock phases defined by φ2 typically do not overlap, and dead time often exists between φ and φ to avoid overlapping operations.

Timing signal φ0. φ, and their complementary signals are distributed throughout the integrated circuit, requiring an extensive path network. In some cases, the complements of signals φ, and φ2 are generated locally by an inverter, or other configurations are used in the 0M08 circuit if only two clock phases (no complementary phases) are required. used.

In the present invention, static storage is used in place of the dynamic storage shown in FIG. 1 (FIG. 2). For this purpose, a master bistable circuit and a slave bistable circuit are used. In FIG. 2, the first (master) bistable circuit includes a cross-coupled gate pair. One pair of gates includes an AND gate 21 and a NOR gate 22, and the other pair of gates includes an AND gate 23 and a NOR gate 24. An input signal 20 on line 20 is applied to the circuit 21 and via an inverter 25 to the gate 23. A one phase clock signal on line 26 is applied to AND gates 21 and 23.

The second (slave) bistable circuit of FIG. 2 also includes a cross-coupled gate pair. One gate pair includes an OR gate 2T and a NAND gate 28, and the other gate pair includes an OR gate 29 and a NAND gate 30. Noah Gate 22, 24
The outputs of are given to the input terminals of OR gates 27 and 29, respectively. The clock signal on line 26 is or game) 27.2
9 to the other input terminal. nand gate 28.3
The zero outputs Q and Ql are provided on lines 32 and 33, respectively.

According to the present invention, as will be explained in detail with reference to FIG. 3, by appropriately selecting the sizes of the input transistors of the single-star bistable circuit and the slave bistable circuit, The operations of the slave selection circuits are prevented from overlapping.

A preferred embodiment of the logic device of FIG. 2 is shown in FIG. Input line 20 and output ll32.33 are also shown. A single phase clock signal is also coupled to line 26. AND gate 21 and NOR gate 22 include transistors 36-41. A p-type transistor 36 is coupled to vcc (positive potential) and the sources of p-channel transistors 37,38. Transistor 3T is coupled in series to n-channel transistor 39.40. A clock signal is coupled to the gate of transistor 38.40. Cross-coupling from gate pair 23.24 takes place through the gate of transistor 36.41.

The output signal from gate pair 21 and 22 is transmitted to transistor 3T.
and 39 and from the common connection point of transistors 38 and 41.

Gate pair 23 and 24 includes transistors 44-49;
Connected similarly to gate pair 21 and 22.

The input signal is passed through the inverter 25 to the transistor 45.
Given to 47 gates. A clock signal is coupled to the gate of transistor 46.48.

The cross-coupling of the gate pair 21 and 22 is the transistor 44°4.
This is done through 9 gates.

The gate pair 27 and 28 in FIG. 2 is the transistor 5 in FIG.
This is realized by 2.57. p channel transistor j
2. ．． 53 is V. C potential and n-channel transistor 55
connected in series between the drains of the p-channel transistor 54 is transistor 52). 53 in parallel. Transistor 55 is an n-channel transistor 56.5
Coupled to the drain of 7. Transistors 56, 57
+7)/- are grounded. The output signal of gate pair 21.22 is coupled to the gate of transistor 53.56.

A clock signal is applied to the gate of transistor 52.57. Cross-coupling of gate pair 29 and 30 takes place through the gates of transistors 54,55.

The gate pair 29 and 30 in FIG. 3 are transistors 60 to 65.
, and is constructed in the same manner as gate pair 27 and 28.

The output of gate pair 23.24 is coupled to the gate of transistor 61.84. The clock signal is the transistor 60
．． 65 and cross-coupling of gate pair 27.28 is provided through the gate of transistor 62.63.

The input transistors 37 and 38 of the gate pair 21 and 22 are surrounded by a solid circle 6T. The input transistors 39, 40 of the gate pair are surrounded by a dashed circle 68. Similarly 1 gate pair 23 and 24 input transistors 45.46
is surrounded by a solid circle 69, and the input transistor 47.48
is surrounded by a dashed circle 70.

In gate pair 27.28, enter Kadran Sister 5
2 and 53 are surrounded by a broken line circle 71, and the input transistor 5
2.53 is surrounded by a solid line circle T2. Similarly, the input quadrant distal 0.61 of the gate pair 29.30 is surrounded by a circle 73 with a broken line, and the input quadrant distal 4.65 is recessed with a solid circle 74.

In the table below! The relative drawn dimensions of the three-factor transistor are shown (in this table only the value of 2 is given, which is the width of the channel, the length of the channel and the distance between source and drain) are all the same and are 2 microns).

36.44 18 52.60 1637
．． 45 18 53.61 163B, 4
6 18 54,62 839.47
6 55, 63 144G, 48
6 56,64 1441.49 6
57.65 The dimensions of the fourteen transistors are selected to provide operation as will be described in more detail below with reference to FIG. Specifically, the transistor dimension Z/L (width/length) is a transistor parameter that can be varied to obtain the desired result. According to the present invention, the transistors surrounded by the solid line circles 67, 69, 72, and 74 are the dotted line circles? 1.73. It is made larger than the transistor surrounded by H,70.

Any one of a number of calculation methods can be used to determine the dimensions of the transistor. One currently preferred technique is to calculate the dimensions and then simulate the circuit with a combinator model. This allows for relatively small adjustments in transistor dimensions to obtain the combination of dimensions that yields the best results. However, the initial dimensions of the input transistors are made according to the invention.

In the illustrated embodiment, the master and slave flip-flops or bistable circuits are level triggered devices and are combined together to form an edge triggered device. More specifically, a positive level triggered master 7 lip and a negative level triggered slave flip-flop form a negative edge triggered lip 70. A positive edge triggered flip-flop can be constructed by having the master flip-flop be a negative level triggered flip-flop and the slave flip-flop being a seven lip flop that is positive level triggered.

Next, refer to FIG. The single phase clock signal applied to 82B is shown by waveform 26&. A typical input as applied to line 20 is shown as waveform 201. The desired output (Q output) given to line 32 is waveform 32
It is indicated by m.

The input transistors for the gate pair of FIG. 3 are selected such that the master flip-flop receives input from input line 20 when the clock signal is in a first period. In the embodiment described herein, the first period occurs when the potential of the clock signal exceeds two-thirds of vcc. The input transistors of the slave flip-flops are selected such that the slave flip-flops receive the output from the master flip-flop when the clock signal is during the second period. In the embodiment described herein, the second period occurs when the potential of the clock signal is less than one-third of vcc. Those periods are waveform 2
"Master sample" and "slave sample" in 6a
are shown respectively. The period between the master flip-flop and slave flip 70 is shown as a safe region.

At time 100, the master circuit samples waveform 20a in a low level state. At time 101, the slave circuit samples its low level waveform and produces a low level output on line 32. Assuming that the potential on line 20 goes high, at time 102 that potential is sampled by the master circuit, and as shown at time 103, the slave circuit samples the higher potential. When the potential of the input signal drops, as shown at time 104, the master circuit samples the low potential input signal, and the slave circuit also samples the low potential input signal.

With the operations described above, the safety area prevents duplication of operations.

Comparing the circuit of FIG. 1 with the circuit of FIG. 3, it can be seen that the circuit of FIG. 3 is considerably more complex.

The advantages derived from a single phase clock signal can be realized by adding only 1-2% to the actual circuit area of the device. This area increase does not take into account the area saved by eliminating the buses required to distribute multiphase signals.

An improved logic device for 0MO8VLSI using a single-phase clock signal has been described above.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional CMO8 logic circuit, and FIG. 2 is a circuit diagram of two level-triggered D-type flip-flops forming an edge-triggered D-type flip-flop used to explain the present invention. , FIG. 3 is a circuit diagram of the logic device of the present invention, and FIG. 4 is a waveform diagram used to explain the operation of the logic device of the present invention. 21.23...antogame), 22.24...
Noah Gate, 25...Inverter, 27.29...
...Or Gate, 28.30...Nand Gate.

Claims (10)

[Claims] (1) a first logic circuit having a first input transistor and coupled to receive an input signal; and a second logic circuit having a second input transistor and coupled to receive an output signal of the first logic circuit. a logic circuit, wherein the first logic circuit and the second logic circuit are coupled to receive the same phase of a clock signal, and during a first period of the clock signal, the first logic circuit receives the input signal and the second logic circuit receives the output signal from the first logic circuit during a second period of the clock signal. The dimensions of the two input transistors are different,
Complementary metal-oxide, characterized in that said first time period and said second time period do not overlap, so that one clock signal is used for said first logic circuit and said second logic circuit. Clock logic devices in material-semiconductor (CMOS) integrated circuits. (2) A logical device according to claim 1, which
Logic device wherein each of the first and second logic circuits is a level-triggered flip-flop that together form an edge-triggered flip-flop. (3) A logical device according to claim 2, which
A logic device wherein each of the first and second periods of the clock signal is separated by a third period of the clock signal. (4) A logical device according to claim 3, which
A logic device, wherein the first logic circuit and the second logic circuit are static circuits. (5) A logical device according to claim 4, which
A logic device, wherein the first logic circuit and the second logic circuit are bistable circuits. (6) a master bistable circuit comprising cross-coupled first and second gates and coupled to receive an input signal; and a slave comprising cross-coupled third and fourth gates. a bistable circuit, wherein the first gate, the second gate, the third gate, and the fourth gate each include an input transistor, and the input transistor of the first gate and At least some of the second gate input transistors are coupled to receive the input signal, and some of the third gate input transistors and the fourth input transistor are coupled to receive the input signal from the master circuit. the other input transistors of the first to fourth gates are coupled to receive the same phase of the clock signal, and during a first period of the clock signal the master circuit the first clock signal receives an input signal, and the slave circuit receives an output signal from the master circuit during a second period of the clock signal that does not overlap with the first period of the clock signal;
The sizes of the input transistors of the gate and the second gate are different from the sizes of the input transistors of the third gate and the fourth gate, such that one for the master circuit and the slave circuit. A clock logic device in a complementary metal-oxide-semiconductor (CMOS) integrated circuit, characterized in that a clock signal is used. (7) A logical device according to claim 6,
A logic device wherein the first period and the second period of the clock signal are separated by a third period of the clock signal. (8) A logical device according to claim 7,
Logic device characterized in that the input signal is coupled to the second gate via an inverter. (9) A logical device according to claim 8,
A logic device characterized in that the first gate and the second gate include an AND gate and a NOR gate, and the third gate and the fourth gate include an OR gate and a NAND gate. (10) The logic device according to claim 7, wherein the input transistors of the first to fourth gates include a transistor of a first conductivity type and a transistor of a second conductivity type. Characteristic logical device.