JPH03263919A - Dynamic logic circuit - Google Patents

Abstract

PURPOSE:To prevent the waveform of a clock signal from rounding, signal propagation from delay, and the malfunction of a circuit from occurring in the inside of an LSI, etc., by combining plural clock signals with certain delay quantity, and applying the signals to this dynamic logic circuit. CONSTITUTION:When a clock phi1 goes to an 'L' level, both transistors Q1, Q2 are turned on, and transistors Q3, Q4 are turned off, and output OUT is pre-charged to an 'H' level via turned-on transistors Q1, Q2. When a clock phi2 goes to the 'H' level after the delay of prescribed time td, the transistor Q2 is cut off, while, the transistor Q4 is turned on, therefore, the output OUT goes to the 'H' or 'L' level corresponding to the logic of input IN. In such a manner, since a pre-charge period tpc can be regulated by the delay time td of the clock phi2 for the clock phi1, the wiring of a signal line for the clock for P/D with narrow width in the inside of the LSI is eliminated.

Description

[Detailed Description of the Invention] [Summary] Dynamic logic circuit, especially L using the logic circuit.
Regarding the SI design method, in order to prevent clock signal waveform dullness, signal propagation delay, circuit malfunction, etc. inside the LSI, and to facilitate logic design and layout design, a predetermined pulse width has been introduced. a clock supply circuit that supplies a clock signal and a clock signal that has the opposite logic to the clock signal and is delayed by a predetermined time; a logic circuit that is set to any one of the above and realizes a predetermined logic in response to at least one input signal, and the logic circuit is connected in series between the first power supply line and the output terminal, and the logic circuit is connected in series between the first power supply line and the output terminal, and a precharge circuit comprising a plurality of MO3 transistors whose gates respond to the two types of clock signals; and a discharge circuit connected between the output terminal and a second power supply line and responsive to the two types of clock signals. It is configured to have the following.

[Industrial Field of Application] The present invention relates to a dynamic logic circuit, and particularly to an LSI design method using the logic circuit.

LSI design methods include methods that use static or dynamic logic circuits, but for the same logic, the dynamic type uses fewer transistors to make up the logic section than the static type. It has the advantage of being done. Therefore, especially in LSIs such as microcomputers, the number of transistors is reduced to reduce the chip area [5] This is a commonly used method.

[Conventional technology]

FIG. 10 shows an example of the configuration of a conventional dynamic logic circuit, and FIG. 11 shows its operation timing waveforms.

The illustrated dynamic logic circuit is composed of a PMOS transistor Qp and nMOS transistors Q n + and Qn, which are connected in series between a high potential power line Vcc and a low potential power line VssO.
p and Qn constitute a precharge circuit and a discharge circuit, respectively, and respond to an active low precharge/discharge clock (P/D clock PCX).

Further, the transistor Qnz constitutes a logic section and responds to a signal at the input terminal IN.

In this configuration, when the P/D clock PCX reaches the pin level, the transistor Qp turns on and the transistor Qn
+ is turned off, and the output line 0LIT is charged to the level of Vcc (“H level”) via the transistor Qp in the on state (precharge period trc).

Next, when the P/D clock PCX becomes "H" level (at the end of the precharge period trc), the transistor Qp
is off, transistor Qn is on, and the output (OU
The level of T) becomes "H" level or "L" level depending on the input logic (IN) (discharge period, that is, logic operation period tDC). In the illustrated example, when the input (IN) is at the "L" level, the transistor Q n z is in the cut-off state, and the output (OIJT) maintains the original "H" level. Conversely, when the input is at the "H" level, the transistor Qnz turns on, and the transistor Qn in the on state
, and Qnz, the charge on the output line OUT is extracted to the power supply line Vss side, thereby changing the output to the "L" level. This logic operation period t0° ends when the P/D clock PCX changes to the "L" level.

In this way, the precharge period tic is defined by the period from the falling edge to the rising edge of the P/D clock PCX, while the discharge period (logic operation period) tnc is defined by the rising edge of the P/D clock PCX. It is defined by the period from the beginning to the falling point. That is, the precharge period trc and the logic operation period tゎ. The total corresponds to one period of the P/D clock PCx.

[Problem to be solved by the invention]

As mentioned above, in a dynamic logic circuit, the longer the precharge period tic, the longer the logic operation period tD.
Since C is short, the circuit must operate at high speed accordingly.In order to achieve this, a signal line that propagates a clock with a narrow pulse width, that is, a high-speed clock, must be routed inside the LSI. It becomes necessary.

However, when a signal line that propagates a clock with a narrow pulse width is routed inside an LSI, the waveform of the clock signal becomes dull due to the wiring resistance and wiring capacitance, which in turn causes signal propagation delay, and in some cases, the circuit may malfunction. There is a problem that occurs. Therefore, sufficient care must be taken when performing LSI wiring, which makes wiring design complicated. This complicates the logic design and layout design, and there is room for improvement.

On the other hand, with the recent increase in the integration and speed of LSIs, the operating clock frequency of LSIs has increased from 50 to 100MHz.
This has led to the need for the internal operation clock signals of LSIs and the internal logic circuits of LSIs to operate at high speeds.

In a dynamic logic circuit, the precharge period trc
Since the circuit (see FIG. 11) does not perform any logical operation, it is preferable that trc be as short as possible for high-speed operation of the LSI. However, if a clock with a narrow pulse width (in the example shown in FIG. 11, it is negative logic and has a width of trc) is routed inside the LSI, the above-mentioned problems arise, which is not preferable. Therefore, when applying a P/D clock to a dynamic logic circuit, a method of applying the clock must be devised.

The present invention was created in view of the problems in the prior art, and includes the blunting of the waveform of the clock signal inside the LSI,
It is an object of the present invention to provide a dynamic logic circuit that can prevent signal propagation delays, circuit malfunctions, etc., and facilitate logic design and layout design.

[Means to solve the problem]

In order to solve the above problems, the present invention eliminates the need to route wiring for signals with narrow pulse widths (that is, high-speed signals) inside the LSI, and allows clock signals input from the outside to be dynamically input as much as possible in their original state. I am trying to supply it to a type logic circuit.

Therefore, according to the present invention, there is provided a clock supply circuit that supplies a clock signal with a predetermined pulse width, a clock signal that has the opposite logic to the clock signal and is delayed by a predetermined time, and two types of clock signals from the clock supply circuit. a logic circuit that is set to either a precharge state or a discharge state in response to a first input signal and realizes a predetermined logic in response to at least one input signal;
a precharge circuit consisting of a plurality of MO3I-transistors connected in series between the power supply line and the output terminal and whose respective gates respond to the two types of clock signals; and between the output terminal and the second power supply line. There is provided a dynamic logic circuit characterized in that it has a discharge circuit connected to the discharge circuit and responsive to the two types of clock signals.

[Effect]

According to the above-described configuration, two types of clock signals having a specific phase difference and logical relationship are supplied to the dynamic logic circuit, so that the two types of clock signals are both supplied to the precharge circuit in the precharge circuit. A predetermined precharge operation is performed only during the period when the logic is the same. That is, the precharge period is defined by the delay time between two types of clock signals.

Therefore, it is no longer necessary to route a clock with a narrow pulse width inside the LSI, which was the case in the past.
Inconveniences such as blunted clock signal waveforms, signal propagation delays, and malfunctions of circuits within the SI can be eliminated, and convenience can also be achieved in logic design and layout design.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the configuration of a dynamic logic circuit as an embodiment of the present invention.

In the figure, C3 indicates a clock supply circuit, which includes an inverter IV that responds to an externally input clock signal CLK, and a capacitor C connected between the output terminal of the inverter and a low-potential power supply line VssO. There is. The inverter Iν and the capacitor C constitute a kind of delay circuit. This clock supply circuit CS receives an external clock signal CLK, outputs a clock signal φ1 having the same phase as the clock signal, inverts the polarity of the external clock signal CLK through a delay circuit, and further delays it by a predetermined time (td). and outputs a clock signal φ2. These two types of clock signals φ1. φ2 is the precharge/discharge clock (
It is used as a clock for P/D.

This logic circuit consists of a precharge circuit PC connected in series between a high potential power line VCC and a power line VssO.
1. Consists of a logic section LCI and a discharge circuit DCI.

The logic unit LCI consists of an nMOS transistor g5 that responds to the input (IN), and cooperates with the discharge circuit DCI during the discharge period (logic operation period) to respond to the input (IN).
The output (OMIT) level is determined according to the logic of N). In this embodiment, to simplify the explanation, the logic section LCI
has a circuit configuration that performs simple inverter operation.

The precharge circuit PCI includes two pMs connected in series and responsive to P/D clocks φ1 and φ2, respectively.
Consists of O3 transistors Q1 and Q2, clock φ
1. When both φ2 are “L level”, the output (OUT) is “H”
On the other hand, the discharge circuit DCI is composed of two nMO3 transistors Q3 and Q4 connected in parallel and responsive to the P/D clocks φ1 and φ2, respectively, and is precharged to the When one side is at the "H" level, the output (OUT) is maintained at the "H" level (when IN = "L" level) or discharged to the "L" level (IN = ``H'' level).

FIG. 2 shows an operation timing chart of the circuit of FIG. 1.

When the clock φ1 goes to "L" level (at this point, the clock φ2 is "beyond"), the transistor QLΩ
2 is a transistor Q3. Q4 is turned off, and the output (
OIJT) is precharged to "H'" level (precharge period trc).

When the clock φ2 reaches the "H" level after a delay of a predetermined time (td), the transistor Q2 is cut off and the transistor Q4 is turned on, so the output (OUT) changes according to the logic of the input (IN). “H” level or “L”
level. In other words, at this point, the precharge period t
rc ends, and a discharge period (logic operation period) tDe begins instead. This logic operation period tDC is based on the clock φ1. This is continued while at least one of φ2 is at "H" level.

In the illustrated example, the logic operation period tDC ends when the clock φ1 falls to the next level.

In this way, the precharge period tic is the clock φ1
Since it is defined by the delay time (td) of the clock φ2 relative to the clock φ2, it is no longer necessary to route a signal line for the P/D clock with a narrow pulse width inside the LSI as in the conventional case. Therefore, logical design and layout design can be easily performed.

Furthermore, since the edge of one of the two types of clocks φ1 and φ2 is used, the dynamic logic circuit can function normally without being affected by the duty ratio of the clock input signal.

FIG. 3 shows a circuit configuration of another embodiment of the present invention.

In this configuration, the dynamic logic circuit includes a discharge circuit DC2, a logic section LC2, and a precharge circuit DC2 connected in series between the power supply line Vcc and the power supply line VssO.

The logic section LC2 consists of a pMO3 transistor 010 that responds to the input (IN), and cooperates with the discharge circuit DC2 during the logic operation period to determine the level of the output (OIIT) according to the logic of the input (IN). Similar to the embodiment in FIG. 1, the logic section LC2 has a circuit configuration that performs a simple inverter operation.

The precharge circuits PC2 are connected in series and each have a P/D clock φ1. and two n in response to φ2
MO3l-consisting of transistors Q6 and 07, clock φ1. When both φ2 are at the “H” level, the output (OUT) is discharged to the “L” level (precharged in negative logic). On the other hand, the discharge circuit DC2 is connected in parallel and is connected to the P/D clocks φ1 and φ2, respectively. It consists of two PMOS transistors 8 and Q9 that respond to
” level, output (OU) according to the input (IN) logic.
T) is maintained at the "L" level (when IN-"1" level) or is charged up to "H" level (discharged at negative logic) (when IN-"B level").

Note that the clock supply circuit C3 is the same as in the embodiment shown in FIG. 1, so its explanation will be omitted.

FIG. 4 shows an operation timing chart of the circuit of FIG. 3.

Compared to the operation timing of the circuit in Figure 1 (see Figure 2), the logic of each signal is simply reversed, and the operation can be easily inferred from the operation in Figure 2, so the explanation will be given below. Omitted.

Note that in each of the embodiments described above, the logic units LCI and LC2
In the series circuit of the discharge circuits DCI and DC2, the logic section is connected closer to the output terminal OUT side, but this is due to the connection order as shown in FIGS. 5 and 6. Even if it is reversed, similar actions and effects can be obtained.

Further, in the embodiment described above, the discharge circuits DC1,
DC2 has a parallel connection configuration of only nMO3 transistors or pMOs transistors, but as shown in FIG. 7, for example, clocks φ1 and φ2
The discharge circuit DCI may be configured of an OR gate OR that responds to the output of the OR gate, and an nMO3 transistor 011 that responds to the output of the OR gate. Furthermore, as shown in FIG. 8 as another example, the clocks φ1 and φ2
It may be a discharge circuit DC2'' consisting of an AND gate AND that responds to the output of the AND gate, and a pMOS transistor [112 that responds to the output of the AND gate. Alternatively, a parallel connection configuration in which PMOS transistors and nMOS transistors are mixed may be used. .

Similarly, various modifications can be considered for the precharge circuits PCI and PC2.

Furthermore, in each of the above embodiments, the same clock signal φ1. Although φ2 is used, they do not necessarily have to be the same.

For example, it may be a non-overlap signal,
Alternatively, it may be inverted using an inverter or the like, and in short, it is sufficient if there are a plurality of signals (two types in the embodiment) having the same amount of delay.

Furthermore, in each of the embodiments described above, in order to simplify the explanation, the logic units LCI and LC2 have a circuit configuration that performs an inverter operation in response to a single signal. Of course, it may be a circuit configuration that performs the operation.

In this case, as shown in FIG. 9 as an example, a circuit configuration may be adopted in which the discharge circuit DC3 is incorporated in the logic section LC3.

[Effects of the Invention] As explained above, according to the present invention, the precharge period can be shortened by combining a plurality of clock signals having a delay amount of This eliminates the need to route a P/D clock line with a narrow pulse width (high speed) inside the LSI, which was conventionally necessary. As a result, it is possible to prevent clock signal waveform distortion, signal propagation delay, circuit malfunction, etc. inside the LSI, and it is also possible to facilitate logic design and layout design.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a dynamic logic circuit as an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the circuit in FIG. A circuit diagram showing the configuration of the embodiment; FIG. 4 is a timing diagram for explaining the operation of the circuit in FIG. 3; FIG. 5 is a circuit diagram showing the configuration of the main part of the first modification of the embodiment in FIG. 1. 6 is a circuit diagram showing the configuration of the main part of the first modification of the embodiment shown in FIG. 3, and FIG. 7 is a circuit diagram showing the construction of the main part of the second modification of the embodiment shown in FIG. 1. 8 is a circuit diagram showing the configuration of the main part of the second modification of the embodiment shown in FIG. 3, and FIG. 9 is a circuit diagram showing the construction of the main part of the third modification of the embodiment shown in FIG. 1. 10 is a circuit diagram showing an example of the configuration of a conventional dynamic logic circuit, and FIG. 11 is a timing diagram for explaining the operation of the circuit shown in FIG. (Explanation of symbols) CS...Clock supply circuit, PCI, PC2...Precharge circuit, DCI
, DCIo, DC2, DC2', DC3...
Discharge circuit, LC1, LC2, LC3...logic section, Ql, Q2. ΩB, Q9. QIO, Q12・
・・PMOS transistor, 03~lower I port 11...
nMO3 transistor, Vcc...high potential power line, Vss...low potential power line, IN, IN, ~lNn-input terminal, OUT...output terminal, φ1. φ2...P/D clock d...Delay time (between clocks φ1 and φ2). Figure 1: Timing diagram for explaining the operation of the circuit $2 Figure 3: Timing diagram for explaining the operation of the circuit Figure 4: Figure VSS No.C3 Figure 10: A circuit diagram showing an example of the configuration of CC ss. Figure 11:

Claims (1)

[Scope of Claims] A clock supply circuit (CS) that supplies a clock signal (φ1) with a predetermined pulse width and a clock signal (φ2) that has the opposite logic to the clock signal and is delayed by a predetermined time (td); a logic circuit that is set to either a precharge state or a discharge state in response to two types of clock signals from the clock supply circuit and realizes a predetermined logic in response to at least one input signal; The logic circuit includes a plurality of MOS transistors (Q1, Q2) connected in series between a first power supply line (Vcc, Vss) and an output terminal (OUT), each gate of which responds to the two types of clock signals. ; Q6, Q7); and a discharge circuit (DC1) connected between the output terminal and the second power supply line (Vss, Vcc) and responsive to the two types of clock signals. , DC1', DC2, DC2', DC3
) A dynamic logic circuit characterized by having the following.