JPS62235779A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which can be produced in higher yield even if an interval between electrodes is short by forming a polycrystalline silicon layer only in a hole formed in an insulating film formed on a semiconductor substrate to eliminate the contact of the silicon layer with the electrodes. CONSTITUTION:An insulating film 2 formed on a semiconductor substrate 1, holes 4, 5 formed at the film 2, and a polycrystalline silicon layer 9 formed only in the holes 5, 6 are contained. For example, a base diffused region 3 is formed at part of the substrate 1, a base hole 4 and an emitter hole 5 are formed at the film 2, and a polycrystalline silicon layer 9 is buried therein. The layer 8 buried in the hole 4 is implanted, for example, with the same impurity as the region 3 by an ion implanting method, and an impurity having an opposite conductivity type to the base is implanted to the layer 9 buried in the hole 5. An emitter region 7 and a base high density region 10 are formed by thermally diffusing from the layer 8 containing the impurity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device using a polycrystalline silicon layer.

[Conventional technology]

Conventional high-speed operation? Some semiconductor devices that require this are manufactured using a solid-phase diffusion method from a polycrystalline silicon layer containing impurities. For example, in ultra-high-speed operation transistors, a polycrystalline silicon layer containing arsenic is used as an emitter diffusion source to obtain a semiconductor device with ultra-high-speed operation, and the solid-phase diffusion method from a polycrystalline silicon layer containing impurities is important. It has become a technology.

[Problem that the invention seeks to solve]

However, in order to use the solid phase diffusion from a polycrystalline silicon layer containing impurities as described above, it is necessary to form a polycrystalline silicon layer.

FIG. 2 shows a vertical cross-sectional view of a conventional transistor using a polycrystalline silicon layer.As shown in FIG. 2, a silicon oxide film 2 is formed on a silicon substrate 1, and a base diffusion region 3. Base opening 4. Emitter opening 5
is formed. Further, in the emitter, a polycrystalline silicon layer 6 containing arsenic is formed extending over the silicon oxide film 2 as shown in the figure. Emitter region 7 is formed by thermal diffusion from this arsenic-containing polycrystalline silicon layer,
Electrodes 8 are formed on the polycrystalline silicon layer above the base opening and the emitter opening, and constitute transistors 1 to 1.

However, in a transistor that requires ultra-high-speed operation, it is necessary to make the emitter region small and to make the distance between the emitter and the base opening very close. In such a case, the distance between the base electrode and the polycrystalline silicon layer becomes very close, resulting in the following problem. One is
This is a phenomenon in which the base electrode and the polycrystalline silicon layer become close to each other, creating a short circuit between the emitter and the base.

Another problem is that since the step of the polycrystalline silicon layer comes very close to the base electrode, the shape of the photoresist becomes abnormal due to the influence of this step when forming the electrode.

Because of these two problems, it has been impossible to reduce the electrode space to 1 μm or less.

It is an object of the present invention to eliminate contact between the polycrystalline silicon layer and the electrode, thereby eliminating short circuits between emitter bases, and to avoid contact with the photoresist in the electrode formation process, which occurs due to steps in the polycrystalline silicon layer. It is an object of the present invention to provide a semiconductor device that does not adversely affect the shape and can be produced with a high yield even when the electrode spacing is small.

[Means for solving problems]

A semiconductor device of the present invention includes an insulating film formed on a semiconductor substrate, an opening provided in the insulating film, and a polycrystalline silicon layer provided only in the opening. Note that a semiconductor device in which the polycrystalline silicon contains impurities and is formed by solid phase diffusion through heat treatment becomes an effective device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of a transistor that is an embodiment of the present invention.

In FIG. 1, 1 is a silicon substrate and 2 is a silicon oxide film. A base diffusion region 3 is formed in a part of the silicon substrate, and a base opening 4 and an emitter opening 5 are formed in the silicon oxide film, each of which is filled with a polycrystalline silicon layer 9. This polycrystalline silicon is buried only in the opening and does not exist on the silicon oxide film. The polycrystalline silicon layer buried in the base opening is implanted with the same impurity (for example, boron) as the base diffusion region, for example by ion implantation, while the polycrystalline silicon layer buried in the emitter opening An impurity (eg, arsenic) having a conductivity type opposite to that of the base is implanted into the base. Emitter region 7 and base high concentration region 10 are formed by thermal diffusion from the polycrystalline silicon layer containing impurities, and electrode 8 is in contact with these polycrystalline silicon layers to form a transistor.

〔Effect of the invention〕

As described above, in the transistor according to the present invention, since the polycrystalline silicon layer is buried in the emitter or base opening, there is no contact between the electrode and the polycrystalline silicon layer, and no short circuit occurs between the emitter and the base.

In addition, since there is no polycrystalline silicon layer on the silicon oxide layer,
There are no steps, and there is no effect on the shape of the photoresist during the electrode process.

For this reason, it has been possible to significantly improve the yield of transistors and integrated circuits with particularly small electrode spacing.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of an example of a conventional high-speed operation transistor. 1... Silicon substrate, 2... Silicon oxide film, 3.
...Base diffusion region, 4...Base opening, 5...
Emitter opening, 6... Polycrystalline silicon layer containing impurities, 7... Emitter diffusion region, 8... Electrode, 9...
- Polycrystalline silicon layer containing impurities, 10...base high concentration diffusion region.

Claims (3)

[Claims] (1) A semiconductor device comprising an insulating film formed on a semiconductor substrate, an opening provided in the insulating film, and a polycrystalline silicon layer provided only in the opening. (2) The semiconductor device according to claim (1), wherein the polycrystalline silicon layer is a polycrystalline silicon layer containing impurities. (3) The semiconductor device according to claim (1), wherein the polycrystalline silicon layer contains impurities and is heat-treated.