JPS6223462B2 - - Google Patents

Info

Publication number
JPS6223462B2
JPS6223462B2 JP60296893A JP29689385A JPS6223462B2 JP S6223462 B2 JPS6223462 B2 JP S6223462B2 JP 60296893 A JP60296893 A JP 60296893A JP 29689385 A JP29689385 A JP 29689385A JP S6223462 B2 JPS6223462 B2 JP S6223462B2
Authority
JP
Japan
Prior art keywords
bump
layer
wiring
semiconductor device
stress relaxation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60296893A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6211253A (ja
Inventor
Susumu Sato
Hideo Tsunemitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60296893A priority Critical patent/JPS6211253A/ja
Publication of JPS6211253A publication Critical patent/JPS6211253A/ja
Publication of JPS6223462B2 publication Critical patent/JPS6223462B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)
JP60296893A 1985-12-27 1985-12-27 半導体装置 Granted JPS6211253A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60296893A JPS6211253A (ja) 1985-12-27 1985-12-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60296893A JPS6211253A (ja) 1985-12-27 1985-12-27 半導体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP12631877A Division JPS5459080A (en) 1977-10-19 1977-10-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6211253A JPS6211253A (ja) 1987-01-20
JPS6223462B2 true JPS6223462B2 (ko) 1987-05-22

Family

ID=17839525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60296893A Granted JPS6211253A (ja) 1985-12-27 1985-12-27 半導体装置

Country Status (1)

Country Link
JP (1) JPS6211253A (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011033393A1 (en) 2009-09-17 2011-03-24 Koninklijke Philips Electronics N.V. Geometry of contact sites at brittle inorganic layers in electronic devices

Also Published As

Publication number Publication date
JPS6211253A (ja) 1987-01-20

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