JPS62234368A - Photodetector - Google Patents
PhotodetectorInfo
- Publication number
- JPS62234368A JPS62234368A JP61078569A JP7856986A JPS62234368A JP S62234368 A JPS62234368 A JP S62234368A JP 61078569 A JP61078569 A JP 61078569A JP 7856986 A JP7856986 A JP 7856986A JP S62234368 A JPS62234368 A JP S62234368A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- potential
- trench
- volt
- type well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は受光孝子に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a light receiving device.
従来の技術
近年、受光素子においても高集積度が要求され、特に固
体撮像素子の分野においては、高解像に対する要求が強
くなってきている。2. Description of the Related Art In recent years, a high degree of integration has been required for light receiving devices, and particularly in the field of solid-state image sensors, there has been a strong demand for high resolution.
この要求を満たすべく、従来は第２図のような構造がし
ばしばとられていた。２１はＮ型シリコン基板、２２は
Ｐ型ウェル、２３はチャンネルストッパー、２４はトラ
ンスファーゲート（Ｔ、（：Ｌ）、２６は受光部（ＰＤ
）、２６は電荷転送部、２７はＬＯＣＯ８，２ａはポリ
シリコン、２９は渡光謹、２１０は酸化膜である。In order to meet this requirement, conventionally a structure as shown in FIG. 2 has often been adopted. 21 is an N-type silicon substrate, 22 is a P-type well, 23 is a channel stopper, 24 is a transfer gate (T, (:L)), and 26 is a photodetector (PD).
), 26 is a charge transfer section, 27 is a LOCO 8, 2a is polysilicon, 29 is a wafer, and 210 is an oxide film.
上記のような従来の構造について説明する。Ｐ型ウェル
２は、受光部６の下は濃度が低く、電荷転送部６の下は
濃度が高くなるように形成されている。従って上記Ｐ型
ウェル２とＮ型シリコン基板１の間に逆バイアス電圧Ｖ
をかけ、受光部６の下のＰ層を完全に空乏化すれば、受
光部６であふれでた電荷は、電荷転送部にあふれこまず
に、Ｎ型基板へバンチスルー電流となって吸収される。The conventional structure as described above will be explained. The P-type well 2 is formed so that the concentration is low below the light receiving section 6 and the concentration is high below the charge transfer section 6. Therefore, a reverse bias voltage V is applied between the P-type well 2 and the N-type silicon substrate 1.
If the P layer under the light receiving section 6 is completely depleted by applying the current charge, the charges overflowing from the light receiving section 6 will be absorbed into the N-type substrate as a bunch-through current without overflowing into the charge transfer section. Ru.
このような受光部であふれでた電荷を掃きすてるための
ドレイン（オーバーフロードレイン）ヲ、受光部の横で
はなく深部に設ける構造（Ｖ、 Ｏ，Ｄ構造）は、平面
的に制約をうけないので、高解像に対しては主流構造と
なりつつあった。The structure (V, O, D structure) in which the drain (overflow drain) for sweeping away the charge overflowing from the light receiving part is provided deep inside the light receiving part rather than beside it is not subject to any restrictions in terms of plane. Therefore, it was becoming the mainstream structure for high resolution.
発明が解決しようとする問題点
しかしながら、上記のような構造では、次のような問題
点があった。まず第１に、素子分離にＬＯＣＯ３を使う
限シ、素子の集積度はＬＯＣＯ８の２次元的な拡がりに
よって制限されるという問題があった。第２に、電荷転
送部の下及びチャンネルストッパーのＰ型領域は、ポテ
ンシャルとしてはｏｖのフラットな領域であり、ここに
光があたって発生した電荷は、ランダムな運動をし、電
荷転送部にもれこんだ場合は偽信号（スミア）の原因と
なる。第３に、Ｐ型ウェルは網目状に形成されているた
め、シート抵抗が高く、光励起された過剰ホールにより
Ｐウェル電位がｏＶに保たれないという問題があった。Problems to be Solved by the Invention However, the above structure has the following problems. First of all, as long as LOCO3 is used for element isolation, there is a problem that the degree of integration of the elements is limited by the two-dimensional expansion of LOCO8. Second, the P-type region under the charge transfer section and the channel stopper is a flat region with a potential of ov, and the charges generated when light hits this region move randomly and reach the charge transfer section. If it leaks, it may cause false signals (smear). Thirdly, since the P-type well is formed in a mesh shape, the sheet resistance is high, and there is a problem that the P-well potential cannot be maintained at oV due to excessive holes that are photoexcited.
本発明はかかる点に鑑みてなされたもので、素子分離領
域が狭く、しかもスミアが少なく、さらにＰウェル電位
を安定にｏＶに保つ構造をもった受光素子を提供するこ
とを目的としている。The present invention has been made in view of these points, and an object of the present invention is to provide a light-receiving element having a narrow element isolation region, less smear, and a structure that stably maintains the P-well potential at oV.
問題点を解決するための手段
本発明は前記問題点を解決するため、素子分離領域を溝
で形成し、前記溝内に基板と少なくともその一部が接触
するように金属を埋めこんだ構造にするものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has a structure in which the element isolation region is formed by a groove, and a metal is buried in the groove so that at least a part of the groove is in contact with the substrate. It is something to do.
作 用
本発明は前記した構造により、素子分離領域は基板に溝
をほって形成するのであるから、平面的にはエツチング
幅にのみ制約され、ＬＯＧＯ８のような、酸化時の２次
元的な拡がシは無視できる。Effects In the present invention, with the above-described structure, the element isolation region is formed by cutting a groove in the substrate, so that it is limited only by the etching width in a plan view, and two-dimensional expansion during oxidation, such as in LOGO8, is limited. Gas can be ignored.
また、溝内に金属を埋めこむことにより、斜めに入って
きた光は、金属で遮光されるため、スミアも低減するこ
とができる。さらに前記金属はＰ型ウェルと接触させて
いるので、前記金属の電位をＯｖに保っておけば、金属
は低抵抗であるから各受光部下のＰウェルをＯｖに保っ
たことになり、Ｐ型ウェルの電位が変動することはない
。Furthermore, by filling the groove with metal, light that enters obliquely is blocked by the metal, so smear can also be reduced. Furthermore, since the metal is in contact with the P-type well, if the potential of the metal is kept at Ov, since the metal has low resistance, the P-well under each light receiving area is kept at Ov, and the P-type The potential of the well does not change.
実施例
第１図は、本発明の受光素子の一実施例を示したもので
ある。１１はＮ型シリコン基板、１２はＰ型ウェル、１
３はチャンネルストツバ−１１４はＴ、Ｇ、１６は受光
部、１６は電荷転送部、１７は溝、１８はＭｏ金属、１
９はポリシリコン、１１０は遮光膜゛、１１１は酸化膜
である。Embodiment FIG. 1 shows an embodiment of the light receiving element of the present invention. 11 is an N-type silicon substrate, 12 is a P-type well, 1
3 is the channel stopper 114 is T, G, 16 is the light receiving part, 16 is the charge transfer part, 17 is the groove, 18 is Mo metal, 1
9 is polysilicon, 110 is a light shielding film, and 111 is an oxide film.
素子分離は、シリコン基板に堀った溝１７によってなさ
れているので、分離領域を狭くすることができる。即ち
画素の高集積化が可能である。また、前記溝１７内に埋
めこんだＭｏ金属１８により、斜めに入射してきた光Ａ
は遮光され、電荷転送部の下のＰ型領域にもれこんで偽
信号をつくることはない。即ちスミアを低減することが
できる０さらに、前記Ｍｏ金属１８を撮像面外で電位を
ＯＶに保つことにより、Ｍｏ金属１８は低抵抗であるか
ら、撮像面内のＰ型ウェルは、全領域にわたってＯｖと
することができる。即ち、Ｐ型ウェルの電位をＯｖに保
つことができる。Since element isolation is achieved by grooves 17 dug in the silicon substrate, the isolation region can be narrowed. That is, high integration of pixels is possible. In addition, the Mo metal 18 buried in the groove 17 prevents the light A that is obliquely incident.
is shielded from light and does not leak into the P-type region under the charge transfer section and create false signals. In other words, smear can be reduced. Furthermore, by keeping the potential of the Mo metal 18 at OV outside the imaging surface, the P-type well within the imaging surface can be It can be Ov. That is, the potential of the P-type well can be maintained at Ov.
発明の効果
以上のべてきたように、本発明によれば、きわめて簡単
な方法で、画素の高集積化が可能であシ、しかもスミア
が少なくＰウェルの電位をｏＶに保つことができ、実用
的にきわめて有効である。Effects of the Invention As described above, according to the present invention, it is possible to highly integrate pixels by an extremely simple method, and the potential of the P well can be maintained at oV with less smear. It is extremely effective in practical terms.
第１図は本発明の一実施例の受光素子の断面図、第２図
は従来の受光素子の断面図である。
１７・・・・・・溝、１８・・・・・・Ｍｏ金属。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名＋ｒ
−−−ｔｔτシリコン基４艮
１２−−−／Ｉｌクエル
＋３°°゛ナヤ７冬ル又Ｌ７ノ〔−
唱−ｒｅ。
＋１１−−−Ｍ、会長
ｔ９−一一子！ワシリコン
（ｆｔｒ−−−＠１巴月東
ｆｕ＝−四秀４ｃ月夷FIG. 1 is a sectional view of a light receiving element according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional light receiving element. 17...Groove, 18...Mo metal. Name of agent: Patent attorney Toshio Nakao and 1 other person + r
---ttτ silicon group 4 艮 12 ---/Il quel + 3°°゛Naya 7 Winter Ru again L7ノ [- chant-re. +11---M, Chairman t9-Ichiko! Wasilicon (ftr---@1 Tomoe East fu=-Sishu 4c Moon Yi
Claims (1)
の中に前記基板に接触するように金属が埋め込まれてい
ることを特徴とする受光素子。A light-receiving element characterized in that a groove serving as an element isolation region is formed on a surface of a substrate, and a metal is embedded in the groove so as to be in contact with the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61078569A JPS62234368A (en) | 1986-04-04 | 1986-04-04 | Photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61078569A JPS62234368A (en) | 1986-04-04 | 1986-04-04 | Photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62234368A true JPS62234368A (en) | 1987-10-14 |
Family
ID=13665525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61078569A Pending JPS62234368A (en) | 1986-04-04 | 1986-04-04 | Photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62234368A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161757A (en) * | 1987-12-18 | 1989-06-26 | Nec Corp | Solid-state image pickup element |
| JP2004128350A (en) * | 2002-10-04 | 2004-04-22 | Graphic Techno Japan Co Ltd | Image sensor equipped with pixel isolation region |
-
1986
- 1986-04-04 JP JP61078569A patent/JPS62234368A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161757A (en) * | 1987-12-18 | 1989-06-26 | Nec Corp | Solid-state image pickup element |
| JP2004128350A (en) * | 2002-10-04 | 2004-04-22 | Graphic Techno Japan Co Ltd | Image sensor equipped with pixel isolation region |
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