JPS62221758A - Storage device - Google Patents

Abstract

PURPOSE:To improve greatly the reliability of the titled memory device by switching automatically a bank register to a spare one if the bank register gets out of order. CONSTITUTION:In case one of bank registers 20-23 has trouble and either one of those outputs has an error, the output of one of detecting circuits 410-413 that corresponds to said erroneous bank is set at logic 1. When either one of individual error registers 420-423 is equal to logic 1, either one of selecting circuits 30-33 of the corresponding bank is switched to output the information received from a bank spare register 24. While either one of the corresponding AND gages 400-403 outputs bank setting signals S0-S3. Furthermore, the output of an OR gate 430 is set at logic 1 together with the output of a common error register 431 set at logic 1 respectively. Hereafter the logic 1 is kept and a NAND gate 405 outputs one of signals S0-S3 in response to the bank having a trouble.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] This invention is used in an information processing system, which has a plurality of banks for storing binary information, and stores banks in bank registers in response to different bank set signals. Set common information,
The present invention relates to a storage device that speeds up the overall operation by outputting the information to the corresponding bank.

"Prior Art" Conventionally, this type of storage device has a plurality of banks because the speed of banks for storing binary information is relatively slow.
A method of commonly controlling a plurality of banks in synchronization with a system clock is often used.

In a conventional storage device, a plurality of bank registers are provided corresponding to a plurality of banks to hold period information of the bank's operating time (a time that is an integral multiple of the system clock period), and the system clock is input from an external device. Operation requests sent synchronously were held in the bank register specified by the operation.

[Problems to be solved by the invention] In recent years, there has been a demand for higher reliability of storage devices.
The above-mentioned conventional storage device has a problem in that if one bank register fails, the entire storage device fails, and as the number of banks increases, the reliability of the storage device deteriorates.

Therefore, an object of the present invention is to provide a plurality of bank registers (7
) By providing another spare bank register and automatically switching to the spare bank register when one of the plurality of bank registers fails, the storage device can be maintained normally even if one of the bank registers fails. The object of the present invention is to provide a storage device that can operate efficiently and has dramatically improved reliability.

"Means for Solving the Problems" A storage device of the present invention includes a plurality of banks that store binary information, and a storage device that is provided corresponding to the plurality of banks and stores bank common information including error detection bits. a plurality of bank registers that hold information in response to a plurality of bank set signals as input; a bank reserve register that holds information with the bank common information as input; a plurality of selection circuits that receive information from each of the plurality of bank registers and the bank reserve register and output one of them to the plurality of banks; and whether or not there is an error in the output of the plurality of bank registers. If there is no error, the bank reserve register is updated every time at least one of the bank registers is updated, and the plurality of selection circuits are updated with information from each of the plurality of bank registers. When an error is detected, the bank spare register is updated with the bank set signal corresponding to the bank with the error, and the selection circuit corresponding to the bank with the error is set to the bank spare register. and an error detection control circuit that controls output of information from the register.

"Example" Next, the present invention will be explained with reference to the drawings.

In FIG. 1 showing one embodiment of the present invention, the storage device of the present invention has four banks 10 to 1 for storing binary information.
3, bank registers 20 to 23 which commonly input the bank common information CD and hold information in accordance with each of the four bank set signals 5o-83, and the bank common information CD.
The bank spare register 24, which is used when any of the bank registers 20 to 23 fails, and the output of each of the bank registers 20 to 23, and the common output of the bank spare registers 24, are input. Selection circuits 30 to 3 that output either one to banks 10 to 13
3, and an error detection control circuit 40 that detects whether or not there is an error in the output of any of the bank registers 20 to 23 and controls the selection circuits 30 to 33 and the bank reserve register 24 depending on the presence or absence of an error. It consists of:

The error detection control circuit/10 includes bank registers 20 to 23.
and error detection circuits 410 to 414 that detect whether or not there is an error in each of the bank spare registers 24, and individual error registers that maintain the state when an error is detected in the output from the error detection circuits 410 to 413. 420
423, an OR gate 430 that performs the logical sum of the outputs of the error detection circuits 410 to 413, and this OR gate 430.
The output of 0 is input, and the output is the OR gate 4300 Å.
Common error register 431 connected to the input side, bank set signal 5o-83 and individual error registers 420-4
AND gate 40 for ANDing each of the 23 outputs.
0 to 403 and the outputs of these ANDNO gates 40403 and outputs the negated value.NOR gate 404 performs the AND of the output of this NOR gate 404 and the output of OR gate 430, and the negation is performed. NANI) gate 405 which outputs a value, and A which performs AND between the output of the error detection circuit 414 and the output of the common error register 43].
ND gate 432.

In FIG. 1, when the bank registers 20 to 23 are operating normally, the error detection circuits 410 to 413
The output of OR gate 43o, individual error registers 420-423 and common error register 431 are all logic ``0''. Since the outputs of the individual error registers 420 to 423 are logic "O", the selection circuits 30 to 33 output the outputs of the bank registers 20 to 23 to banks 10 to 13, respectively. Also, the output of the OR gate 430 is logic Since the output of the NAND gate 405 is logic "1", the bank reserve register 24 stores bank common information for each system clock (not shown, but all registers operate in synchronization with this system clock). Store the CD.

In the case of 2, one of the bank set signals SO to S3 becomes logic "1" in accordance with an operation request from an external device (not shown), and corresponds to the case.
The bank common information CD is stored in one of 3. Note that the bank set signals SO to S3 become logic "1" only during the period of the system clock cycle (hereinafter abbreviated as T), and then become logic "1" at least during the operation period of banks 10 to 13, that is, nT (however, n is a positive integer value greater than 1).

If one of the next banks 20 to 23 fails and one of its outputs has an error, the output of one of the error detection circuits 410 to 413 corresponding to the bank with the error becomes a logic 'X1'. Individual error. The registers 420 to 423 are used as registers that, once set to logic "1", hold the logic "1" until a reset signal (not shown) arrives.

Any of the individual error registers 420 to 423 is at logic “1”.
“When this happens, one of the selection circuits 30-33 of the corresponding bank is switched to output information from the bank reserve register 24, and the corresponding AND gate 40-33 is switched to output information from the bank reserve register 24,
403 outputs bank set signals SO to S3. Further, since any of the outputs of the error detection circuits 410 to 413 becomes a logic "1", the output of the OR gate 430 becomes a logic "1", and the output of the common error register 43 becomes a logic "l". Hold "1".

When the output of OR gate 430 becomes logic "l", NAN
Since D gate 405 outputs the negative value of NOR gate 404, it outputs one of bank set signals SO-S3 corresponding to the failed bank via AND gates 400-403 and NOR gate 404.

Until the error detection circuits 410 to 413 detect an error,
Since the bank spare register 24 stores the bank common information CD for each system clock, the error detection circuit 41
When an error is detected in 0 to 413, normal operation can be continued by using bank spare register 24 in place of any of the failed bank registers 20 to 23.

Note that if there is an error in the bank registers 20 to 23 and there is an error in the bank reserve register 21, the output of the common error register 431 is already a logic "1", and the output of the error detection circuit 414 is already a logic "1". 1”, so AND
The output of the gate 1-432 becomes a logic "1". In such a case, it is treated as a failure of the entire storage device by a circuit not shown.

This embodiment is effective when the amount of circuits in the bank resins 220 to 230 is larger than the amount of circuits including the selection circuits 30 to 33 and the error detection control circuit 40 and the failure rate is high. 3 than 2 manual selection circuit
The amount of circuitry is ~5 times as much, and since the error detection control circuit 40 has a smaller number of bits than the bank registers 20-23, the amount of circuitry is small. For example, in the case of a storage device having 30 pits as an address signal, each bank register has 30 bits, but the error detection control circuit 4
It is sufficient for each individual error register to have one pit.

"Effects of the Invention" As explained above, the present invention significantly increases the reliability of storage devices by automatically switching to a spare bank register when a failure occurs in a bank register. It has the effect of improving.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. 10-13: Bank, 20-23: Bank register, 2
4: Bank spare register, 30-33: Selection circuit, 40
:Error detection control circuit, 400-403, 432
: Gate, 404:NOR Gate
, 405: NAND gate, 410-414: error detection circuit, 420-423: individual error register, 430
: OR gate, 431: Common error register, CD: Bank common information, SO to S3: Bank set signal.

Claims (1)

[Claims] (1) A plurality of banks that store binary information, and a bank that is provided corresponding to the plurality of banks, and receives bank common information including error detection bits as input and stores that information in response to a plurality of bank set signals. a plurality of bank registers that hold the bank common information; a bank spare register that receives the bank common information and holds the information; a plurality of selection circuits that input the information and output one of them correspondingly to the plurality of banks, and a plurality of selection circuits that detect whether or not there is an error in the output of the plurality of bank registers, and detect whether or not there is an error. If not, update the bank reserve register every time at least one of the bank registers is updated, and control the plurality of selection circuits to output information from each of the plurality of bank registers, When an error is detected, the bank spare register is updated with the bank set signal corresponding to the bank with the error, and the selection circuit corresponding to the bank with the error is configured to output information from the bank spare register. and an error detection control circuit that controls the error detection control circuit.