JPS62221145A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which is strong against a soft error, highly integrated, low power consumption and appropriate for high speed operation by providing a circuit group which has a conductive layer which is the potential barrier against small number of carriers and a circuit group which contains CMOS and bi-polar transistors in the semiconductor device. CONSTITUTION:The first circuit group A which has a conductive layer effective as the potential barrier against small number of carriers consists of, e.g., a memory cell which stores an information. The second circuit group B which transmits and receives a signal with the first circuit group A consists of CMOS and bi-polar transistors and, e.g., is a peripheral circuit for reading the stored information from the memory cell or writing. The information stored in the memory cell A cannot be destroyed by the radiation of alpha-rays, etc., due to the conductive layer which is effective as the barrier against small number of carriers. Since the peripheral circuit B contains the CMOS and the bi-polar transistors, the high driving capability of the bipolar transistor is also used by making the most of the characteristics of the highly integrated and low power consumption CMOS.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular, to prevent malfunctions caused by radiation such as alpha rays, so-called soft errors, and to operate at high speed and with low power consumption. The present invention relates to a semiconductor device suitable for and a method for manufacturing the same.

[Conventional technology]

The so-called one-transistor memory cell, which consists of a capacitor for storing information charge and one MOS transistor for switching, occupies a small area and is suitable for high integration, so it is used as a dynamic RAM (random access memory). It is widely used as a memory cell for DRAM (hereinafter referred to as DRAM). However, in recent years, the so-called soft error phenomenon has become a problem, in which the information charge in the memory cell disappears due to minority carriers generated in the silicon substrate when radiation such as alpha rays is incident, causing the memory to malfunction. There is. More recently, static RAM (
The above-mentioned soft error phenomenon has also become a major problem in SRAM (hereinafter referred to as SRAM) (or general semiconductor devices). Regarding mechanism 11 of soft error phenomenon,
IIE Transactions on Electron Devices
ons on Electron Devices;
Vo Q.

ED-26, 41, J a n, 1979. p p,
2 to 9], so the details will be omitted here, but as LSIs become more highly integrated, the amount of signals handled inevitably becomes smaller, so countermeasures against soft error phenomena have become an urgent necessity.

Various measures have been considered as countermeasures against the soft error phenomenon, but currently the most effective one is considered to be a voltage (potential) barrier (hereinafter referred to as "barrier") against carriers caused by alpha rays, etc. This is a method of preventing the inflow of minority carriers by providing a layer that serves as a barrier (abbreviated as a barrier). FIG. 2 shows an example in which the barrier is provided in a DRAM memory cell, which is a so-called H i -C type memory cell.

Hi-C type memory cells will be discussed at the Technical Digest International Electron Device Meeting (Technical DjHest).
The mechanism will be explained using the second @. In FIG. 2, 1 is a silicon substrate of p-type conductivity type, and 2 is an insulating film for isolation between elements, which is usually made of SiO2. Reference numeral 3 denotes an electrode at one end of the capacitor, which is usually made of polysilicon. 4 is an insulating film that becomes the dielectric of the capacitor;
It is formed of SiOz, 5iaN4, etc. 5,8
is an interlayer insulating film between each electrode and wiring, and usually 5
Formed from iOz. 6a and 6b are gate electrodes of MOS transistors, and also serve as word lines of the memory.

Note that the reference numeral 6b serves as the gate electrode of a plurality of other memory cells (not shown), and its position varies depending on the method of arranging the memory cells. 6a.

6b is formed of polysilicon, a high melting point metal such as Mo, W, or Ti, or a silicide such as Mo5iz, WSix, Ti5iz, or the like. Reference numeral 7 denotes a gate insulating film of the MOS transistor, which is usually formed of 5 iOz.

Reference numeral 9 denotes a wiring serving as a data line of the memory, which is usually formed of AΩ, and is connected to the n-type 10b via a communication hole 11. 10
Reference numerals a and 10b are n-type conductive layers, which respectively serve as the drain or source electrodes of the Mo8) transistor. 12 is an n-type conductive layer.

This is the electrode at one end of the capacitor. Reference numeral 13 denotes a P-type conductive layer, which acts as a barrier to minority carriers as described later. Note that in FIG. 2, for example, when the same materials are formed in contact with each other, a boundary line does not normally exist, but a clear boundary line is shown here for convenience of explanation.

The same applies below.

In FIG. 2, information charges are distributed between the electrode 3, the insulating film 4, and the conductive layer 12. Information can be read and written through the data line 9 by controlling the potential of the gate electrode, which is the word line. Second
In the figure, since the conductive layer 13 is of the P type conductivity type, a Pn junction is formed between the conductive layer 13 and the N type conductivity type. This has the effect of increasing the capacitance of the capacitor by the junction capacitance of the Pn junction. Furthermore, an important function of the conductive layer 13 is that it acts as a barrier for minority carriers (electrons in this case) that cause soft errors through the following mechanism. FIG. 2(b) shows an impurity profile in the depth direction from the silicon substrate 1, where the horizontal axis X represents the distance from the substrate surface, and the vertical axis N represents the impurity concentration. X
1! , X 13 is the n-type conductive layer 12. P-type conductive layer 13
diffusion depth, N 1 , N 1 x # N ta
is a silicon substrate 1. The respective impurity concentrations of conductive layers 12 and 13 are shown. FIG. 2(c) shows the potential distribution (the upper part is negative) when the concentration profile is as shown in FIG. 2(b). (c) As shown in the figure, a potential peak or barrier is formed in the P-type conductive layer 13.

As a result, even if electrons generated by the incidence of radiation such as alpha rays try to flow into the n-type conductive WJ12,
Most of the electrons are repelled by this peak of potential, and almost no electrons are collected in the n-type conductive layer 12.

This almost eliminates the occurrence of soft error phenomena. In this way, according to the Hi-C structure, it is possible to form a potential barrier against minority carriers.

Here, we showed an example applied to DRAM, but SRAM
Of course, it is also effective to provide a potential barrier in order to prevent soft error phenomena in other general semiconductor devices as well. The above-mentioned technology is an essential technology for promoting higher integration of semiconductor devices in the future.

On the other hand, MOS transistors and bipolar transistors are commonly used as devices for semiconductor devices, but MOS transistors are advantageous in terms of degree of integration, and in order to realize semiconductor devices with high integration and low power consumption, N CMOS (complementary MO) that combines a channel MOS transistor and a P-channel MOS transistor
S) The device is suitable.

For the above reasons, in order to realize a semiconductor device that is highly integrated and resistant to soft errors using conventional technology, it is necessary to use 0MO5.
It is essential to provide a barrier against minority carriers, such as a Hi-C structure, in a region that can cause soft errors.

[Problem that the invention seeks to solve]

Using the above-mentioned conventional technology, it is possible to realize a semiconductor device with low power consumption that is resistant to soft errors at the current degree of integration, but problems will arise as the degree of integration increases further in the future. In order to increase the degree of integration, it is necessary to make the devices constituting the semiconductor device smaller, but the smaller the devices, the smaller the amount of signals handled.

In order to handle a small amount of signal at high speed, devices used in semiconductor devices are required to have a large drive capability, but as long as 0MO3 is used as a device, the size of the MOS transistor can be increased from the point of view of integration. The speed decreases with the degree of integration, so even if measures are taken to prevent soft errors, it has been difficult to realize a semiconductor device with high integration, high speed, and low power consumption as long as CMOS is used.

An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device that is resistant to soft errors, has high integration, low power consumption, and is suitable for high-speed operation, and a method for manufacturing the same.

[Means for solving problems]

In order to achieve the above object, the present invention provides a conductive layer that acts as a barrier against minority carriers in a portion where a soft error may occur due to the inflow of minority carriers, such as a memory cell, for example. Furthermore, at least some of the circuits were constructed using a mixture of OMO5 and bipolar transistors.

[Effect]

The conductive layer described above acts as a potential barrier against minority carriers generated by incidence of radiation such as alpha rays. As a result, it is possible to prevent soft errors in memory cells caused by the inflow of minority carriers, and there is no malfunction.
Because there is a bipolar transistor in addition to 0 MO
It is possible to take advantage of the high integration and low power consumption, which are the features of 5, and the high drive capability, which is the feature of bipolar transistors.

Therefore, it is possible to realize a highly integrated, low power consumption, and high speed semiconductor device that does not malfunction due to soft errors. Furthermore, by forming the conductive fft layer as a barrier to minority carriers and the conductive layer serving as the base of the bipolar transistor in the same process, the structure and manufacturing process can be simplified.

〔Example〕

Examples of the present invention will be described below. FIG. 1 is an embodiment showing the concept of the present invention. A is a first circuit group having a conductive layer acting as a potential barrier against minority carriers, and is composed of, for example, a memory cell for storing information. B is a second circuit group that exchanges signals with the first circuit group, and is composed of a CMO3 and a bipolar transistor, and is used, for example, to read and write stored information from the memory cell. This is the peripheral circuit. C indicates a semiconductor chip which is a semiconductor device. Hereinafter, an embodiment will be described in which A represents the above-mentioned memory cell array and B represents the above-mentioned peripheral circuit, but the present invention is not limited thereto.

According to the configuration of FIG. 1, the information stored in memory cell A is stored in
Because of the i-layer, it will not be destroyed even if radiation such as alpha rays enters it.6 Also, since the peripheral circuit B is configured to include CMO5 and bipolar transistors, the features of CMO8 such as high integration and low power consumption can be achieved. By taking full advantage of the high drive capability of bipolar transistors, high-speed operation can be achieved.

FIG. 3 is a sectional view showing a second embodiment of the invention.

This example is an application of the present invention to a DRAM,
FIG. 3 shows one cell in memory cell array A that stores information.
This figure shows a cross section of one memory cell, and a cross section of a bipolar transistor, a P-channel MOS transistor, and an N-channel MO3 transistor in a peripheral circuit B that exchanges signals with the memory cell. Note that in FIG. 3 and the following drawings, things that are necessary for an actual semiconductor device, such as an insulating film on a substrate or wiring, but are not directly related to the gist of the present invention, are not shown in FIG. The memory cell shown in A has the same Hi-C structure as shown in FIG. can be prevented. Here, the conductive layer 13 is provided below the electrode 12 of the capacitor, and the n-type trench conductive layer 1.0 a is the source and drain of the MOS transistor.

If it is necessary to provide a barrier also under 10b, a conductive layer 13 may be provided as necessary. In B of FIG. 3, an n-type trench conductive layer 17a is used as a collector.

A bipolar transistor having the P-type trench layer 16 as a base and the n-type trench layer 14c as an emitter, and the P-type trench layer 18
A P-channel transistor formed in the n-well 17b with a and 18b as the source and drain and 6c as the gate, and an n-channel MOS transistor with the n-type trench conductor layers 10c and 10d as the source and drain and 6d as the gate. Indicated. Here, the n-type trench conductor layers L4a, 14b and the p-type trench conductor layer 15 include a collector 17a and a base 16, respectively.
This is a high-concentration impurity diffusion layer for establishing electrical connection with wiring (not shown in the figure). The reason why the two high concentration layers are provided in the collector 17a is to reduce the resistance of the collector 17a and prevent the potential of the collector from decreasing and saturating the bipolar transistor when a current flows through the collector. It goes without saying that either one of 14a and 14b may be used as needed, or the resistance may be further reduced by using a structure that surrounds the base 16. Also,
17a, 1 between the n-wells 17a, 17b and the substrate 1.
It is also possible to lower the resistance by providing an n-type trench conductor layer having a higher impurity concentration than 7b. Note that the P-type trench conductor layer 1 serving as a barrier
The concentration of #3 and the depth from the substrate surface are variously selected depending on the purpose, but in general, each #10" to #10"
on the other hand, the concentration and depth from the substrate surface of the P-type trench conductive layer 16, which is the base of the bipolar transistor, are generally 1.
0 lB ~ 10 "cs""" 0.1pm ~ 5μm
Selected for the Guraino range.

As described above, according to this embodiment, the memory cell has
A one-transistor type memory cell with a P-type trench conductor layer that acts as a barrier for minority carriers is used, and one peripheral circuit is composed of a P-channel MOS transistor, an N-channel MOS transistor, and a bipolar transistor. It is possible to realize a semiconductor device that is free from the risk of soft errors caused by radiation and that can operate at high speed with low power consumption. Furthermore, in this embodiment, the P-type trench layer 13 serving as a barrier and the P-type trench layer 13 serving as the base of the bipolar transistor can be formed in the same process. In that case, the above embodiment can be realized at low manufacturing cost by reducing the manufacturing process.

In the above-mentioned embodiment, the memory cell has a planar capacitor, but various other memory cells, such as those described in the literature IEEE Journal on Solid State Circuits,
f5olid-8tate C1rcuits.

Vo Q-S C-19e & 5e Oct
The present invention can also be applied to a memory cell of the type in which a trench is dug in a silicon substrate and the side surface of the trench is used as a capacitor, as described in 1984e p. 634-640].

FIG. 4 shows an example in which the present invention is applied to a memory cell having a capacitor on a substrate. In FIG. 4, the capacitor is composed of electrodes 3 and 20a and an oxide film 4', and M
A P-type trench conductive layer 13 having an impurity concentration higher than that of the silicon substrate (P-type) is provided as a barrier directly under 10a which becomes the source or do/in region of the OS transistor.

The peripheral circuit section B has the same structure as that in FIG. In this embodiment, if the inflow of electrons into the conductive layer 10b becomes a problem, a P-type conductive layer serving as a barrier may be provided under the n-type trench conductive layer 10a.

According to this embodiment, as with the embodiment shown in FIG. 3, it is possible to realize a high-speed semiconductor device with a high degree of integration, without causing soft errors, and with low power consumption. 13 and the base 15 of the bipolar transistor can be formed in the same process, the manufacturing cost can be reduced as well, as in the embodiment shown in FIG. moreover,
In this embodiment, since the capacitor of the memory cell is disposed on the MOS transistor, the area occupied by the memory cell is small, making it suitable for higher integration than the embodiment shown in FIG.

Note that the impurity concentration profile of the P-type conductive layer serving as a barrier in one or more of FIGS. 3 and 4 may be set variously as necessary. For example, in order to further ensure the barrier effect, the P-type trench conductive layer 13 may be formed in various types to provide a plurality of peaks of potential, or the junction breakdown voltage with the N-type trench conductive layer in contact with the conductive layer 13 may be In order to prevent a decrease in the bonding potential, the P-type trench conductive layer 13 may be formed at a deeper location at a distance from the N-type trench conductor layer 13, or the concentration inside the P-type trench conductor layer 13 may be increased in deep regions. It is also possible to further increase the effectiveness of the barrier without deteriorating the withstand voltage. In addition, MOS transistors used in memory cells and peripheral circuits are
It goes without saying that changes can be made without changing the spirit of the present invention, such as increasing the resistance to hot carriers by using an extremely doped drain structure or changing the structure of the bipolar transistor. Here L D
For details on the effects of D4'l construction, see IEF!E Transactions on Electron Devices (IEF!
ectron Devices VoQ, ED-2
, 7, Au g.

19.80. p p , 1359-1367). Furthermore, in each of the embodiments described above, n
I explained using a channel MOS transistor as an example, but
By reversing the conductivity type of the impurities, the present invention is also applicable to those using P-channel MOS transistors.

Although no particularly difficult technology is required to manufacture the semiconductor device according to the present invention, by devising the manufacturing process, it is possible to manufacture the semiconductor device using steps close to the number of manufacturing steps for CMO3. Taking the structure of FIG. 3 as an example, an example of the manufacturing method will be explained using FIG. 5. In Figure 5(a),
A cross section of the structure in the middle of the manufacturing process is shown. Below, (a
), we will outline the manufacturing method in sequence.

(a) A silicon substrate 1 containing a P-type impurity, for example, boron, is prepared. The concentration of impurities is generally 1
6 set within the range of 018~10171''8
Next, the well-known LOGO3 (first step) is performed to form n-type conductive layers (n-well) 17a and 17b on the main surface of the silicon substrate 1 by ion implantation technology or normal diffusion technology.
Local Oxidat, ton of Silico
In step (n), an insulating film 2 made of 5iOz is formed using a technique.

(b) A P-type trench conductive layer 13 serving as a barrier and a P-type thick conductive layer serving as a base of a bipolar transistor are simultaneously formed by ordinary diffusion technology or ion implantation technology. Next, an n-type trench conductor layer that will become one f8 pole of the capacitor is formed.

(c) Insulating film of capacitor 4. is formed by oxidizing the surface of silicon substrate 1, and electrode 3 is formed on top of it. As the material of the electrode 3, polysilicon, for example, is used at a temperature of 1°C.

Next, the gate insulating films 7a, 7b, 7 of the MOS transistors
A is formed by oxidizing the surface of the silicon substrate 1, and a gate electrode 6a is formed on the top thereof.

6c and 6d are formed. The materials for the electrodes 6a, 6c, and 6d include polysilicon or high melting point metals such as W and Mo;
A silicide such as WSiz or Mo5iz or a layered film of these is used. Here, the insulating films 7a, 7b, 7
c and electrodes 6a, 6a.

6d may be deposited over the entire surface of the silicon substrate 1 and then simultaneously formed using a known photoetching technique.

(d) Next, the n8 conductive layer that becomes the source and drain of the n-channel MOS transistor: L Oa r 10 b
rloc, 10d and the emitter L4c of the bipolar transistor and the n-type trench conductive layer 14a of the collector portion.

14b is simultaneously formed by ion implantation technique.

After this, P-type thick electric layer 18a becomes the source and drain of the P-channel MOS transistor.

1 and 8b and the highly doped P-type trench conductor layer 15 in the base of the bipolar transistor are simultaneously formed by ion implantation technology, the structure shown in FIG. 3 is obtained. Although the insulating film on the gate electrode of the MOS transistor and wiring such as data lines are omitted here, these can be easily formed by known processes.

According to the above manufacturing method, the P-type trench conductor layer 13 serving as a barrier
Not only can a P-type thick conductive layer, which is the base of a bipolar transistor, be formed in the same process, but also a P-channel MO
8) - The n-well 17b for the transistor and the n-well 17a for the bipolar transistor can be formed in the same process,
Furthermore, n-type thick electric layers 10a, 10b, 10c, 10d which become the source and drain of the n-channel MOS transistor
The emitter 14c and the n-type trench conductive layers 14a and 14b of the collector part of the bipolar transistor can be formed in the same process, and the P-type thick conductive layers 18a and 18b which become the source and drain of the P-channel MOS transistor and the bipolar transistor can be formed in the same process. High concentration P-type trench layer 1 in the base
5 can also be formed in the same process. In other words, according to this embodiment, a bipolar transistor can be formed without changing the manufacturing process of a conventional DRAM in which the memory cell part has a Hi-C structure and one peripheral circuit is composed of MOS, and it is possible to form a bipolar transistor with high integration and to avoid soft errors. Therefore, a high-speed semiconductor device with low power consumption can be realized at low cost.

The present invention has been explained above using examples.

The scope of application of the present invention is not limited thereto, and various structural or manufacturing modifications are possible.

For example, although DRAM has been explained here as an example, SR
It can be applied to AM or general semiconductor devices without changing the main idea.

In addition, although I explained to Seisaku that the half-electricity that serves as a barrier should be provided within the memory cell, this is not limited to this.
For example, this patent can be applied as is when the barrier conductive layer is provided on a data line of a memory cell, or when it is provided on another circuit section such as a sense amplifier section for detecting a minute signal from a memory cell. Of course, these can be applied alone or in any combination.

[Results of invention]

As explained above, according to the present invention, by providing a circuit group including a conductive layer that serves as a potential barrier against minority carriers and a circuit group including a CMO3 and a bipolar transistor in a semiconductor device, It is possible to fundamentally solve the problem of soft errors, take advantage of the advantages of CMO5 such as high integration and low power consumption, and realize a high-speed semiconductor device using bipolar transistors.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the concept of the present invention. FIGS. 2(a) and 2(b) are diagrams showing the prior art, and FIG. 3 is a diagram showing a cross section of a specific embodiment of the present invention. 4 is a cross-sectional view of another embodiment of the present invention, and FIG. 5 is a cross-sectional view showing the manufacturing process of the embodiment shown in FIG. 3. A...Circuit group, B...Circuit group, C...Semiconductor chip, 13...P-type trench conductor layer (layer serving as a potential barrier), 16...P-type trench conductor layer, ( Pipolar transistor A...Circuit group 6...Circuit group C...Semiconductor chip/second (b)

Claims (1)

[Claims] 1. A semiconductor device having at least one MOS transistor, characterized in that a conductive layer that acts as a potential barrier against minority carriers and at least one bipolar transistor are provided. semiconductor devices. 2. In the semiconductor device according to claim 1, signals are exchanged between the memory cell array formed near the main surface of the semiconductor substrate and consisting of memory cells for storing information, and the memory cell array. A semiconductor device having a peripheral circuit, wherein the memory cell includes at least a first region of a first conductivity type near a main surface of a semiconductor substrate, and a first region of a first conductivity type formed near the first region. A semiconductor device comprising a second region of a different second conductivity type, and wherein the peripheral circuit includes at least one MOS transistor and at least one bipolar transistor. 3. Claim 2, characterized in that the memory cell is configured to include at least one MOS transistor.
The semiconductor device described in . 4. The semiconductor device according to claim 2, wherein the memory cell includes at least one MOS transistor and at least one capacitor. 5. A method for manufacturing a semiconductor device having at least one MOS transistor and a bipolar transistor, in which the MOS transistor is provided with a conductive layer acting as a potential barrier to minority carriers, the conductive layer acting as a potential barrier and the base of the bipolar transistor. 1. A method of manufacturing a semiconductor device, characterized in that a conductive layer constituting the semiconductor device is formed in the same process.