JPS62219967A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62219967A
JPS62219967A JP6318186A JP6318186A JPS62219967A JP S62219967 A JPS62219967 A JP S62219967A JP 6318186 A JP6318186 A JP 6318186A JP 6318186 A JP6318186 A JP 6318186A JP S62219967 A JPS62219967 A JP S62219967A
Authority
JP
Japan
Prior art keywords
carrier
layer
semiconductor layer
traveling
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6318186A
Other languages
Japanese (ja)
Inventor
Akira Ishibashi
晃 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6318186A priority Critical patent/JPS62219967A/en
Publication of JPS62219967A publication Critical patent/JPS62219967A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7785Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To avoid degradation of the mobility and speed of carriers of a two-dimensional carrier gas layer in a carrier traveling semiconductor layer caused by LO (longitudinal optical) phonon scattering and improve sheet density by a method wherein one of two hetero-junction planes of which the two-dimensional carrier gas layer is composed is formed by laminating compound semiconductor layers which have no overlapping of oscillation frequency in the LO phonon branch. CONSTITUTION:1st and 2nd carrier supply layers 1 and 2, which supply carriers to a carrier traveling semiconductor layer 3 in which carriers exist locally and which are made of semiconductors with wider gaps compared to the gap of the carrier traveling semiconductor layer 3 as shown in an energy band model of a conduction band side, are provided on both sides of the layer 3 holding the layer 3 between them and 1st and 2nd hetero-junction planes J1 and J2 are formed. The two junction planes J1 and J2 are, or the one junction plane J1 is, composed of 1st and 2nd wide gap semiconductor thin film layers 11 and 12 which have wide band gaps. The thickness (a) of the carrier traveling semiconductor layer 3 in which carriers exist locally conforms to the relation a<=pi/q, wherein (q) is the momentum of the carrier, for instance electron, in the layer 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置、特にダブルヘテロ接合面による半
導体装置、例えばダブルヘテロ接合面による2□次元電
子ガス層型の電界効果型トランジスタ(FIT ) 、
或いは速度変調トランジスタVMT ’等の半導体装置
に関わる。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a semiconductor device using a double heterojunction surface, such as a two-dimensional electron gas layer type field effect transistor (FIT) using a double heterojunction surface. ,
Or it relates to semiconductor devices such as speed modulation transistors VMT'.

〔発明の概要〕[Summary of the invention]

本発明はダブルヘテロ接合面を有する半導体装置におい
□て、そのキャリ)′走行半導体層の夫々2次元キャリ
アガス層を“形成する2つのヘテロ接合面のうち、の少
くとも・・一方のヘテロ接合面をLO(縦型光学的)フ
ォノンブランチに振動数の重なりのない化合物半導体層
の重ね合せによって構成し、LOフォノン散乱による2
次元キャリアガス層におけるキャリアの移動度の低下、
速度の低下を回避し、更にキャリアのシート密度の向上
をはかる。
The present invention provides a semiconductor device having a double heterojunction surface, in which at least one of the two heterojunction surfaces forming a two-dimensional carrier gas layer of each of the carrier (carrier)' traveling semiconductor layers is provided. The surface is constructed by superimposing a compound semiconductor layer on an LO (vertical optical) phonon branch with no frequency overlap, and 2
dimensional carrier mobility reduction in the carrier gas layer;
Avoiding a decrease in speed and further improving the sheet density of the carrier.

〔従来の技術〕[Conventional technology]

2次元キャリアガス層をキャリア走行チャンネルとして
用いたFETは、その2次元キャリアガス屓の利用によ
って不純物散乱によるキャリアの移動度が無視できて高
い移動度が期待できるという利点があるが、反面、キャ
リアのシート密度が低いという問題点がある。これに対
処して、共通のキャリア走行層に対しこれを挟んでその
両面に電子供給層となるワイドギャップ半導体層による
2・つのヘテロ接合面を形成して2つの2次元キャリア
ガス屓を形成し、これによってキャリア密度を倍加させ
るようにしたダブルヘテロ接合面による2次元キャリア
ガス層によるFETが提案された。
FETs that use a two-dimensional carrier gas layer as a carrier transport channel have the advantage that by utilizing the two-dimensional carrier gas layer, carrier mobility due to impurity scattering can be ignored and high mobility can be expected. The problem is that the sheet density is low. To deal with this, we formed two heterojunction surfaces with wide-gap semiconductor layers that serve as electron supply layers on both sides of a common carrier transport layer, thereby forming two two-dimensional carrier gas layers. , an FET using a two-dimensional carrier gas layer with a double heterojunction surface was proposed, thereby doubling the carrier density.

しかしながら、このようなダブルヘテロ接合型の2次元
キャリアガス層によるFEETにおいても、特に100
K以上の温度では、その2次元キャリアガス屓において
LOフォノン散乱によるキャリアの移動度の低下、速度
の低下が問題となってくる。
However, even in a FEET using such a double heterojunction type two-dimensional carrier gas layer, especially 100
At temperatures above K, problems arise in that carrier mobility and velocity decrease due to LO phonon scattering in the two-dimensional carrier gas.

このことは、2つのヘテロ接合面を設け、夫々異るキャ
リア移動度の2次元キャリアガス層のチャンネルを構成
し、これらチャンネルを切り換え利用することによって
速度変調を行うようにしたダブルヘテロ接合型VMTに
関しても、例えば、本来充分高い移動度と速度をもって
形成されるべき側のチャンネルにおいても、上述したL
Oフォノン散乱の問題によって、充分高い移動度と速度
を得ることができないという問題点がある。
This means that a double heterojunction type VMT has two heterojunction surfaces, each forming a channel of a two-dimensional carrier gas layer with a different carrier mobility, and speed modulation is performed by switching and utilizing these channels. For example, even in the channel that should originally be formed with sufficiently high mobility and speed, the above-mentioned L
There is a problem in that sufficiently high mobility and velocity cannot be obtained due to the problem of O phonon scattering.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は上述したダブルヘテロ接合型の2次元キャリア
ガス層型半導体装置における少くとも一方の2次元キャ
リアガス層のLOフォノン散乱による影響の問題を回避
してキャリア密度が大で、高い移動度を有するキャリア
走行チャンネルを形成する。
The present invention avoids the problem of the influence of LO phonon scattering in at least one two-dimensional carrier gas layer in the double heterojunction type two-dimensional carrier gas layer type semiconductor device described above, and achieves high carrier density and high mobility. Forming a carrier traveling channel with.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、例えば第1図、或いは第3図に示すよ・うに
、キャリアを局在させるキャリア走行半導体層(3)を
挟んでその両面に、第2図及び第4図に夫々そのコンダ
クションバンド側のエネルギーバンドモデルを示すよう
に、キャリア走行半導体層(3)に比しワイドギャップ
の半導体より成り、キャリア走行半導体層(3)に対し
キャリアの供給を行う第1及び第2のキャリア供給層(
11及び(2)を設け、第1及び第2のヘテロ接合面J
工及びJ2を有する構造とする。この構造において、特
に本発明においては、例えば第1図に示すように再接合
面J1及びJ2を、或いは第3図に示すように一方の接
合J□を、キャリア走行半導体層(3)に比し、バンド
ギャップが広い第1及び第2のワイドギャップ半導体薄
膜層(11)  (12)によって構成する。
In the present invention, for example, as shown in FIG. 1 or FIG. 3, the carrier transport semiconductor layer (3) that localizes carriers is sandwiched between the two surfaces thereof, and the conduction layer as shown in FIGS. 2 and 4, respectively. As shown in the energy band model on the band side, the first and second carrier supplies are made of a semiconductor with a wider gap than the carrier traveling semiconductor layer (3) and supply carriers to the carrier traveling semiconductor layer (3). layer(
11 and (2), and the first and second heterojunction surfaces J
The structure shall have a construction and a J2. In this structure, especially in the present invention, for example, the rejoining surfaces J1 and J2 as shown in FIG. 1, or one junction J□ as shown in FIG. However, it is constituted by first and second wide-gap semiconductor thin film layers (11) and (12) having a wide band gap.

これらワイドギャップ半導体層(11)及び(12)と
キャリア走行半導体層(3)とはその運動量−振動数分
散図のし0フオノンブランチが例えば第5図中曲線(5
1A)及び(51B ”)に示すように互いに振動数に
重なりのない化合物半導体によって構成する。すなわち
、例えば各半導体(3)及び薄膜層(11)(12)が
、夫々AとB、CとDの各元素による化合物半導体(A
B)及び(CD)から成る場合、各化合物半導体の各構
成元素のうち、夫々その原子量の小さい方の元素同志の
原子量に大きな差がある材料を選定するものであり、例
えば(AB)としてGaAsを、(CD)としてAll
Asを用いることができる。このような系においては、
GaAs的及びA1^S的LOフォノンが互いに他の層
中にしみこむことができず、各々の層にとじ込められて
しまう。
These wide gap semiconductor layers (11) and (12) and the carrier traveling semiconductor layer (3) have a momentum-frequency dispersion diagram whose 0 phonon branch is, for example, the curve (5) in FIG.
As shown in 1A) and (51B''), they are made of compound semiconductors that do not overlap in frequency with each other. That is, for example, each semiconductor (3) and thin film layers (11) and (12) are composed of A, B, and C, respectively. Compound semiconductors (A
In the case of B) and (CD), a material is selected that has a large difference in atomic weight between the elements with smaller atomic weights among the constituent elements of each compound semiconductor. For example, as (AB), GaAs , as (CD) All
As can be used. In such a system,
GaAs-like and A1^S-like LO phonons cannot penetrate into other layers and are confined in each layer.

そして、ワイドギャップ半導体薄膜Ji!(11)及び
(12)はその厚さを1〜3原子層とし、LOフォノン
については充分局在させ電子については、トンネルを許
すようにする。キャリアを局在させるキャリア走行半導
体層(3)は、その厚さaを、a≦□        
  ・・・・(1)とする、qはこのキャリア、例えば
電子を局在させる半導体層(3)におけるキャリアの運
動量であって、このqは q”mvS       ・・・・(2)であり、mI
′はキャリアの有効質量、VSはこの半導体層(3)の
構成材料のバルク中、でのキャリアの飽和速度である。
And wide gap semiconductor thin film Ji! In (11) and (12), the thickness is set to 1 to 3 atomic layers so that LO phonons are sufficiently localized and electrons are allowed to tunnel. The carrier traveling semiconductor layer (3) that localizes carriers has a thickness a such that a≦□
...(1), q is the momentum of this carrier, for example, a carrier in the semiconductor layer (3) that localizes electrons, and this q is q''mvS ...(2), mI
' is the effective mass of carriers, and VS is the saturation velocity of carriers in the bulk of the constituent material of this semiconductor layer (3).

すると、とじこめられた運動量π/aは、qに対し−2
9なる関係をみたす。
Then, the confined momentum π/a is -2 for q
Fulfills 9 relationships.

一方、ペテロ接合面J1及びJ2にその面方向に電界を
与える手段、すなわち、ソース及びドレイン各電極(4
s)及び(4d)を設ける。
On the other hand, means for applying an electric field to the Peter junction surfaces J1 and J2 in the plane direction, that is, each source and drain electrode (4
s) and (4d) are provided.

そして、ソース及びドレイン電極(4s)及び(4d)
間にゲート電極(5G)、或いは第1及び第2のゲート
電極(5Gs)及び(5G2)が設けられる。
And source and drain electrodes (4s) and (4d)
A gate electrode (5G) or first and second gate electrodes (5Gs) and (5G2) are provided in between.

このような構成において、各ゲート電極(5G) 。In such a configuration, each gate electrode (5G).

(5Gよ)及び(5G2 )に所要の電圧を印加すれば
、キャリア走行半導体層(3)の各ヘテロ接合面J工及
びj2側に2次元キャリアガス層によるキャリア走行チ
ャンネルC1及びC2を生成、消滅するなど制御するこ
とができる。
By applying a required voltage to (5G) and (5G2), carrier transport channels C1 and C2 are generated by a two-dimensional carrier gas layer on the respective heterojunction surfaces J and J2 of the carrier transport semiconductor layer (3), It can be controlled such as disappearing.

〔作用〕[Effect]

上述の本発明構成によれば、少くとも一方のヘテロ接合
面においてキャリアを局在させたことによってキャリア
のシート密度nsが高められると共に、この接合面にお
いてLOフォノンを局在させたことによりこの接合面に
関わる2次元キャリアガス層のキャリア移動度を高める
ことができる。
According to the configuration of the present invention described above, the carrier sheet density ns is increased by localizing the carriers on at least one heterojunction surface, and the LO phonons are localized at this junction surface, thereby increasing the carrier sheet density ns. The carrier mobility of the two-dimensional carrier gas layer related to the surface can be increased.

因みに、キャリア移動度μは、 μ侃□          ・・・・(3)(Wはキャ
リアとLOフォノンとの散乱確率)であり、Wは、 Woc 5M” 4’ r d” P      ・・
・・(41(Mはマトリックスエレメント)である、今
、本発明装置におけるキャリア走行半導体層(3)とワ
イドギャップ半導体薄膜層(11)または(12) と
の積層によるいわば、超格子構造によるマトリックスエ
レメントyI LFT SLと、超格子構造によらない
化合物半導体バルクのそれM2Oとの比についてみると
、例えば、ワークブック・オン・インターナショナル・
コンファランス・オン・エレクトロニック・プロバティ
ーズ・オン・2−ディメンシラナル・システム(N、S
awaki、 Workbook of Intern
ationalconference  on  el
ectronic  properties  of 
 2−dimensionsystem、 Kyoto
+ 1985+ P639)にあるように、qJ2+(
qzi    )’ ・・・・(5) である。こ−に、Qzは、超格子構造の接合面と直交す
る方向のキャリアの運動量であり、q上はそれに直交す
る方向の運動量である。上述した本発明構成では、キャ
リアの走行方向を半導体rfi (3)及びワイドギヤ
ツブ半導体iFJ層(11)または(12)のヘテロ接
合面J1またはJ2の面方向に選定したことにより、q
z〜0である。これによれば、(5)式から q↓2 M uT!EL / M 30  = □qJ2+()
2 ・・・・(5)′ となる。
Incidentally, the carrier mobility μ is μ侃□ ... (3) (W is the scattering probability between the carrier and the LO phonon), and W is Woc 5M"4' r d" P ...
...(41 (M is a matrix element)) Now, in the device of the present invention, a matrix with a superlattice structure is formed by laminating the carrier traveling semiconductor layer (3) and the wide gap semiconductor thin film layer (11) or (12). Regarding the ratio of element yI LFT SL to that of M2O of a compound semiconductor bulk that does not depend on superlattice structure, for example, Workbook on International
Conference on Electronic Properties on 2-Dimensional System (N, S
awaki, Workbook of Intern
ational conference on el
electronic properties of
2-dimension system, Kyoto
+ 1985+ P639), qJ2+(
qzi )' (5). Here, Qz is the momentum of the carrier in the direction perpendicular to the junction surface of the superlattice structure, and q is the momentum in the direction perpendicular to it. In the above-described configuration of the present invention, the traveling direction of the carrier is selected to be in the plane direction of the heterojunction surface J1 or J2 of the semiconductor rfi (3) and the wide gear semiconductor iFJ layer (11) or (12).
z~0. According to this, from equation (5), q↓2 M uT! EL/M30 = □qJ2+()
2...(5)'.

そして、本発明においては、aを、(1)式のπ (3)式及び(4)式から移動度μが充分太き(なるこ
とが分る。
In the present invention, a is defined as π in equation (1). From equations (3) and (4), it can be seen that the mobility μ is sufficiently large.

〔実施例〕〔Example〕

第1図を参照して、ダブルヘテロ接合型の2次元電子ガ
ス層チャンネル型のFETを構成する場合の一例につい
て説明する。この場合、例えばCrドープの半絶縁性の
GaAs化合物半導体基板(21)上に順次第2のキャ
リア供給半導体層(2)、第2のワイドギャップ半導体
薄膜層(12) と、キャリアすなわち電子走行半導体
層(3)と第1のワイドギャップ半導体薄膜層(11)
と第1のキャリア供給半導体層(2)とをMOCVD法
(有機金属気相成長法)、或いはMBR(分子線エピタ
キシー法)にょっ°ζ連続的にエピタキシーし、キャリ
ア走行層(3)を挟んでその両面に第1及び第2のヘテ
ロ接合面J1及びJ2を形成する。
An example of a double heterojunction type two-dimensional electron gas layer channel type FET will be described with reference to FIG. In this case, for example, on a Cr-doped semi-insulating GaAs compound semiconductor substrate (21), a second carrier supply semiconductor layer (2), a second wide gap semiconductor thin film layer (12), and a carrier, that is, an electron transport semiconductor are sequentially formed. Layer (3) and first wide gap semiconductor thin film layer (11)
and the first carrier supplying semiconductor layer (2) are continuously epitaxied by MOCVD (metal organic chemical vapor deposition) or MBR (molecular beam epitaxy), with the carrier traveling layer (3) in between. Then, first and second heterojunction surfaces J1 and J2 are formed on both surfaces thereof.

そして、ソース及びドレイン各電極(4S)及び(4d
)を、第1のキャリア供給半導体層(1)上から第1及
び第2のヘテロ接合面J1及びJ2に到る深さにアロイ
して形成し、両電極(4S)及び(4d)間に例えばシ
ョットキーゲート電極(5G)を形成する。
Then, source and drain electrodes (4S) and (4d
) is formed by alloying the layer from above the first carrier supplying semiconductor layer (1) to a depth reaching the first and second heterojunction surfaces J1 and J2, and between both electrodes (4S) and (4d). For example, a Schottky gate electrode (5G) is formed.

第1及び第2のキャリア供給半導体層+1)及び(2)
は、n型の例えば八Ilo、3Gao、y Asより成
る化合物半導体層によって構成し、キャリア走行半導体
Jii (3)はGaAsによって構成し、第1及び第
2のワイドギャップ半導体薄膜層(11)及び(12)
は例えば2原子層のへIAs化合物半導体層によって構
成する。
First and second carrier supply semiconductor layers +1) and (2)
is composed of an n-type compound semiconductor layer made of, for example, 8Ilo, 3Gao, yAs, the carrier transport semiconductor Jii (3) is composed of GaAs, and the first and second wide gap semiconductor thin film layers (11) and (12)
is constituted by, for example, a diatomic layer of an IAs compound semiconductor layer.

このような構成によれば、キャリア走行半導体層(3)
の両面に第1及び第2の2次元電子ガス層のチャンネル
C1及びC2が形成されたダブルヘテロ接合型の2次元
電子ガス層型のFETが構成され、このコンダクシッン
バンド側のエネルギーバンドモデルは第2図に示すよう
になる。
According to such a configuration, the carrier traveling semiconductor layer (3)
A double heterojunction two-dimensional electron gas layer type FET is constructed in which channels C1 and C2 of first and second two-dimensional electron gas layers are formed on both sides of the conduction band side. is as shown in Figure 2.

第3図は本発明による速度変調トランジスタの一例を示
すもので、この場合においては、基板(21)に第2の
ゲート電極(5G2)となるn型の埋込み層を設け、第
1のチャンネルC1を形成する第1のヘテロ接合面J1
にのみ第1のワイドギャップの例えば2元化合物半導体
薄膜層(11)を設けて、第1のチャンネルC1に関し
て高い電子移動度が得られるようにした場合である。第
4図はこの場合のエネルギーバンドモデルを示す。尚、
第3図において第1図と対応する部分には同一符号を付
して重複説明を省略する。この場合、第1及び第2のゲ
ート電極(5G1)及び(5G2 )への印加電圧によ
って第1及び第2のチャンネルC1及びC2を切換動作
せしめるものである。
FIG. 3 shows an example of a speed modulation transistor according to the present invention. In this case, an n-type buried layer serving as the second gate electrode (5G2) is provided on the substrate (21), and the first channel C1 The first heterojunction surface J1 forming
This is a case where, for example, a binary compound semiconductor thin film layer (11) having a first wide gap is provided only in the first channel C1 to obtain high electron mobility for the first channel C1. FIG. 4 shows an energy band model in this case. still,
In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and redundant explanation will be omitted. In this case, the first and second channels C1 and C2 are switched by voltages applied to the first and second gate electrodes (5G1) and (5G2).

〔発明の効果〕〔Effect of the invention〕

本発明装置によれば、例えば第1図の例では両チャンネ
ルC1及びC2に関し、また第3図の例では一方のチャ
ンネルに関して、その2次元キャリアガス層によるチャ
ンネルのキャリアのシート密度nsを高めることができ
ることによってgraの向上がはかられる。また、LO
フォノンの閉じ込めを行うようにしたことによって10
0に以上の高い温度においても高いキャリア移動度が得
られ高速度化が実現できる。さらに、飽和速度vgの上
昇をも、もたらすことが期待される。今、例えば高純物
n−GaAs結晶の電子移動度の温度依存性をみると、
第6図に示すようにその総合的電子移動度は曲線(61
)に示すように100K程度以上で急激に低下する。同
図において曲線(62)はイオン化不純物によるもの、
(64)はLOフォノンによるもの、(63)は中性不
純物によるもの、(65)はディフォメーションポテン
シャルによるものであり(66)はピエゾエレクトリッ
ク散乱によるものである。
According to the apparatus of the present invention, for example, for both channels C1 and C2 in the example of FIG. 1, and for one channel in the example of FIG. 3, the sheet density ns of the carrier in the channel can be increased by the two-dimensional carrier gas layer. By being able to do this, the gra can be improved. Also, L.O.
10 by confining phonons.
High carrier mobility can be obtained even at temperatures as high as 0 or higher, and high speeds can be achieved. Furthermore, it is expected that an increase in the saturation speed vg will also be brought about. For example, if we look at the temperature dependence of electron mobility in a high-purity n-GaAs crystal,
As shown in Figure 6, the overall electron mobility is the curve (61
), it rapidly decreases above about 100K. In the figure, the curve (62) is due to ionized impurities;
(64) is due to LO phonons, (63) is due to neutral impurities, (65) is due to deformation potential, and (66) is due to piezoelectric scattering.

100に程度以上の電子移動度の低下は、LOフォノン
による依存性が大である。ところが本発明によれば、L
Oフォノンの閉じ込めを行うようにしたことから移動度
の特に100に以上の高温での低下を効果的に改善でき
るものであり、この2次元キャリアガス屓チャンネルに
おいて、高速性を維持したまま室温附近での使用を可能
にするなどの多くの利益をもたらす。
The decrease in electron mobility of about 100 or more is largely dependent on LO phonons. However, according to the present invention, L
By confining O phonons, it is possible to effectively improve the drop in mobility, especially at high temperatures of 100 or higher, and in this two-dimensional carrier gas channel, it is possible to reduce the mobility near room temperature while maintaining high speed. It offers many benefits such as allowing its use in

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第3図は夫々本発明による半導体装置の路線
的拡大断面図、第2図及び第4図は夫々そのバンドモデ
ル図、第5図は運動量−振動数分子&図、第6図は電子
移動度の温度依存性を示す図である。 (21)は基板、(1)及び(2)は第1及び第2のキ
ャリア供給層、(3)はキャリア走行層、(11)及び
(12)は第1及び第2のワイドギャップ半導体層であ
る。
1 and 3 are respectively enlarged linear cross-sectional views of the semiconductor device according to the present invention, FIGS. 2 and 4 are band model diagrams thereof, FIG. 5 is a momentum-frequency molecule diagram, and FIG. is a diagram showing the temperature dependence of electron mobility. (21) is the substrate, (1) and (2) are the first and second carrier supply layers, (3) is the carrier transit layer, and (11) and (12) are the first and second wide gap semiconductor layers. It is.

Claims (1)

【特許請求の範囲】 キャリアを局在させるキャリア走行半導体層と、該キャ
リア走行半導体層を挟んでその両面に夫々ヘテロ接合面
を形成するワイドギャップのキャリア供給層が設けられ
、上記キャリア走行半導体層の両面に夫々2次元キャリ
アガス層による第1及び第2のキャリア走行チャンネル
を形成するようにしたダブルヘテロ接合型の半導体装置
において、上記第1及び第2のヘテロ接合面の少なくと
も一方を、分散関係においてLOフォノンブランチが上
記キャリア走行半導体層のLOフォノンブランチと振動
数の重なりがないワイドギャップ半導体薄膜層とのヘテ
ロ接合面によって構成され、 上記キャリア走行半導体層は、その厚さaを、a≦π/
q (但し、qは上記キャリア走行半導体層におけるキャリ
アの運動量q=m^※vsであり、m^※はキャリアの
有効質量、vsは該半導体層の構成材料のバルク中での
キャリアの飽和速度)とし、キャリアの走行方向を上記
ヘテロ接合面に沿う方向に選定する電界印加手段を具備
する ことを特徴とする半導体装置。
[Scope of Claims] A carrier traveling semiconductor layer that localizes carriers, and a wide gap carrier supply layer sandwiching the carrier traveling semiconductor layer and forming a heterojunction surface on both sides thereof are provided, and the carrier traveling semiconductor layer In a double heterojunction type semiconductor device in which first and second carrier traveling channels are formed by two-dimensional carrier gas layers on both sides of the semiconductor device, at least one of the first and second heterojunction surfaces is dispersed. In the relationship, the LO phonon branch is constituted by a heterojunction between the LO phonon branch of the carrier traveling semiconductor layer and a wide gap semiconductor thin film layer in which the frequencies do not overlap, and the carrier traveling semiconductor layer has a thickness a of a ≦π/
q (However, q is the carrier momentum q=m^*vs in the carrier traveling semiconductor layer, m^* is the effective mass of the carrier, and vs is the saturation velocity of the carrier in the bulk of the constituent material of the semiconductor layer. ), and further comprising an electric field applying means for selecting a traveling direction of the carrier in a direction along the heterojunction surface.
JP6318186A 1986-03-20 1986-03-20 Semiconductor device Pending JPS62219967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6318186A JPS62219967A (en) 1986-03-20 1986-03-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6318186A JPS62219967A (en) 1986-03-20 1986-03-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62219967A true JPS62219967A (en) 1987-09-28

Family

ID=13221817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6318186A Pending JPS62219967A (en) 1986-03-20 1986-03-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62219967A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055891A (en) * 1990-05-31 1991-10-08 Hewlett-Packard Company Heterostructure transistor using real-space electron transfer
WO1991016730A1 (en) * 1990-04-26 1991-10-31 Lucas Industries Public Limited Company Insulated gate bipolar transistor
US5223724A (en) * 1990-07-31 1993-06-29 At & T Bell Laboratories Multiple channel high electron mobility transistor
US5266506A (en) * 1990-07-31 1993-11-30 At&T Bell Laboratories Method of making substantially linear field-effect transistor
JPH0832051A (en) * 1994-07-14 1996-02-02 Nec Corp Semiconductor device
JP2008057852A (en) * 2006-08-31 2008-03-13 Daikin Ind Ltd Refrigerating device
JP2008057870A (en) * 2006-08-31 2008-03-13 Daikin Ind Ltd Refrigerating device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016730A1 (en) * 1990-04-26 1991-10-31 Lucas Industries Public Limited Company Insulated gate bipolar transistor
US5055891A (en) * 1990-05-31 1991-10-08 Hewlett-Packard Company Heterostructure transistor using real-space electron transfer
US5223724A (en) * 1990-07-31 1993-06-29 At & T Bell Laboratories Multiple channel high electron mobility transistor
US5266506A (en) * 1990-07-31 1993-11-30 At&T Bell Laboratories Method of making substantially linear field-effect transistor
JPH0832051A (en) * 1994-07-14 1996-02-02 Nec Corp Semiconductor device
JP2008057852A (en) * 2006-08-31 2008-03-13 Daikin Ind Ltd Refrigerating device
JP2008057870A (en) * 2006-08-31 2008-03-13 Daikin Ind Ltd Refrigerating device

Similar Documents

Publication Publication Date Title
JP2773487B2 (en) Tunnel transistor
JPS6127681A (en) Field effect transistor having channel part of superlattice construction
JPS61210679A (en) Semiconductor device
JPH0237115B2 (en)
JPS6327065A (en) Hetero-junction double-channel semiconductor device, field effect transistor to which the device is applied and apparatus with negative conductance to which the semiconductor is applied
JPS61174776A (en) Heterojunction field effect transistor
CA1290865C (en) Hot electron transistor
US4797716A (en) Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields
KR860000705A (en) Semiconductor device comprising N-channel and P-channel transistors and method of manufacturing same
JPS62219967A (en) Semiconductor device
JPS62256478A (en) Compound semiconductor device
JP2722885B2 (en) Field effect transistor
JPH0312769B2 (en)
US3273030A (en) Majority carrier channel device using heterojunctions
JPH03286540A (en) Velocity-modulation type field-effect transistor
EP0136108B1 (en) Heterojunction semiconductor device
JPS61156773A (en) Heterojunction semiconductor device
JPS58107679A (en) Field effect transistor
JPS61268069A (en) Semiconductor device
JPS61230379A (en) Semiconductor device
JPH0311767A (en) Velocity modulation type field-effect transistor
JPS61230381A (en) Semiconductor device
JP2792295B2 (en) Tunnel transistor
JPS63115385A (en) Semiconductor device
JPS6292368A (en) Semiconductor device