JPS62217672A - Field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the connection resistance between a quadratic electron gas layer and electrodes by a method wherein an n-GaAs layer to be a cap layer of a hetero junction FET with a quadratic electron gas layer is specified to be thick exceeding 1,100Angstrom . CONSTITUTION:An i-GaAs layer 22, an n-AlGaAs layer 23 and an n-GaAs layer 24 are grown on a semiconductor insulating GaAs substrate 21 by a series of epitaxially growing processes. The layers 22, 23 and 24 are respectively a layer forming a quadratic electron gas layer (2DEG)27, a carrier feeding layer and a cap layer. The cap layer 24 is specified to be thick exceeding 1,100Angstrom . Next, Au/AuGe is evaporated as an ohmic metal to be heat-treated in N2 atmosphere forming a source electrode 25 and a drain electrode 26. Through these procedures, the connection resistance between the quadratic electron gas layer 27 and the electrodes 25, 26 can be reduced to improve the characteristics of a hetero junction FET.

Description

[Detailed Description of the Invention] [Summary] In a heterojunction PET having a two-dimensional electron gas layer,
n -GaAs layer n -AN GaAs layer i -G
It has a structure made of aAs and has a thickness of n-GaAs of 1100 Å or more, and has a two-dimensional electron gas layer, a source,
Reduce the connection resistance between the drain and each electrode.

[Industrial application field]

The present invention relates to the structure of a heterojunction FET, and particularly to an evixaxial layer structure and an electrode structure that make it possible to improve its performance.

[Conventional technology]

FIG. 5 shows a cross-sectional view of a HEMT of a conventional heterojunction FET. In Figure 5, 1 is semi-insulating (S-1) G
an aAs substrate; 2 is an undoped GaAs (i-GaAs) layer on which a two-dimensional electron gas layer 2DEG is formed; 3 is a semiconductor layer doped with n-type impurities as a carrier supply layer; here, n-A# XGa1- It is formed of a yAs layer. Further, a cap layer 4 which is a protective layer is formed on the carrier supply layer 3, and is made of an n-GaAs layer here. A concave portion is formed in the gate electrode forming portion beyond the cap layer 4 to form a gate electrode 8. On the other hand, a source electrode 5 and a drain electrode 6 are provided on the cap layer 4 by ordinary vapor deposition or the like, and are subjected to an alloying process to make ohmic contact with the two-dimensional electron gas R2DEG.

Conventionally, the cap layer 4 is considered to be just a protective film.
Care was taken to keep the thickness thin so that it would not become an obstacle when making ohmic contacts between the source and drain. In particular, n -GaAs of the cap layer and n -AI of the carrier co-supply layer 3! Because of the energy gap (usually about 0.3 eV) that occurs at the heterointerface between xGa+-x and S, if the cap layer 4 is thick, the cap layer 4 is usually formed to have a thickness of about 300 layers.

When considering the connection between the source, drain and 2DEC, two paths are considered, indicated by arrows 1 and Ll in FIG. Conventionally, when forming the source electrode 5 and the drain electrode 6, an alloying process is performed so that the alloy region extends to 2 DEGs through the cap layer 4 and the carrier supply layer 3.
I was trying.

That is, consideration was given only to reducing the resistance of the path L.

As a current path, there is Ll shown as a second path in FIG. Energy gap created at the interface (usually 0.3 eV
It was thought that this Ll path would not contribute to reducing the contact resistance.

Based on the above points of view, and also from the results obtained by the inventor through experiments and calculations, as shown in FIG. was observed to increase.

[Problem that the invention seeks to solve]

The present invention was made based on the recognition that in order to improve the performance of a heterojunction FET, it is necessary to further reduce the source resistance.

[Means for solving problems]

In the present invention, mutually lattice matched undoped Ga
A7IGaAsffl doped with As layer and n-type impurity
and n-type GaAs are arranged adjacent to each other in that order, and a two-dimensional electron gas layer is formed near the interface of the undoped GaAs on the Aj2 GaAs side,
The thickness of the n-type GaAs layer is set to 1100 Å or more, and source and drain alloy electrodes are formed in ohmic contact with the n-type 0865 layer to form ohmic connections with the two-dimensional electron gas layer, respectively. A field effect semiconductor device is provided.

[Effect]

As described above, the present inventor conducted experiments by varying the thickness of the cap layer over a wide range, including a region where the thickness of the cap layer is thick, which is considered common knowledge in the prior art and has not been considered until now.

The experimental results are illustrated in FIG. In FIG. 1, the thickness of the cap layer is plotted on the horizontal axis, and the contact resistance is plotted on the vertical axis.

RC indicates TLM (Transmissi).
Contact resistance measured using on-line model. In addition, RCI is the contact resistance between the source and drain electrodes of Ll shown in FIG. 4 and the two-dimensional electron gas layer 2DEG calculated by RC, while RC2 and What is indicated is the contact resistance between the cap layer and the source and drain electrodes determined from RC and calculation.

From the experimental results shown in FIG. 1, it is predicted that the source resistance of the device can be reduced by making the cap layer thicker than in the conventional case to improve ohmic contact with the source and drain electrodes.

Therefore, the present inventors have determined that the cap layer has an n -
The relationship between the thickness d of the GaAs layer and the source resistance Rs was measured. As a result, it is clear that even in the actual device structure, as shown by the circle mark in Figure 3, the source resistance can be reduced by making the cap layer thicker and making good ohmic contact between the cap layer and the source and drain electrodes. became. Note that the solid line indicates the calculated value of the source resistance.

〔Example〕

FIG. 2 shows the HEM of the heterojunction FET according to the embodiment of the present invention.
FIG. 2 is a cross-sectional view of an element of T, and the figure corresponds to a state before formation of a gate electrode.

In the figure, reference numeral 21 denotes a substrate made of semiconductor insulating GaAs.

22 is a semiconductor layer on which a two-dimensional electron gas layer (2DEC) 27 is formed, and is made of i-GaAs.

23 is a carrier supply layer n-8l x Gal-x As
It consists of Note that here, the carrier supply layer is 2.
It is divided into two layers, with 200 nA7 members on the 2DEG side!
a layer of X Ga1-xAs (X = 0.3), and 3
Aβ composition change in 00 people (gn-8l x Gap-
xAsn x changes from 0.3 on the inside to O on the surface side).

Here, its X value is set adjacent to 22 i -GaAs (
According to the rule, X = 0.3, and the n-Ga
On the side in contact with As, x=Q. This carrier supply layer 23 is doped with n-type impurities to a carrier concentration of 2×10 18 CI 11-3.

The cap layer of 24 is formed of n-GaAs and has a 2×1
The cap layer is doped with an n-type impurity at a high concentration of about 2×101” near the surface. In this embodiment, the thickness of this canvas is 300 people, 700 people, 1100 people, and 15 people.
An experiment was conducted with 00 people in four different ways.

Each of the above semiconductor layers is formed by a series of epitaxial growth steps.

Next, a method for forming the source and drain electrodes will be explained.

25 and 26 are a source electrode and a drain electrode, respectively. These are respectively 8u/ as Omi Tsukumetal.
AuGe (Au thickness 4000 mm, AuGe thickness 200 mm) was formed by vapor deposition, and nitrogen (N2
) is formed by heat treatment at 460° C. for 1 minute in an atmosphere.

For the above Peter structure, the thickness of the cab layer is 300, 700, 1100, and 1500 as described above.
The results of measuring the source resistance in four different ways are shown in the third figure.
As shown in the figure. As is clear from the figure, n − of the cap layer
When the thickness of GaAs is increased to 1100 mm, which is sufficiently thicker than the conventional one, the source resistance Rs exhibits good characteristics close to 1 Ω, which is considered to be sufficient for practical use. And the thickness of the cap layer is 1500
In humans, an even better value of 1Ω was obtained. Note that even if the thickness of the cap layer is 1500 Å or more, the source resistance R
The effect of reducing s becomes saturated. There is a natural limit to the thickness of the cap layer. For example, if the cap layer is thick, it is necessary to form the alloy deeply to make ohmic contact between the cap layer and the source and drain electrodes, which increases the processing temperature and adversely affects the device characteristics. This becomes a limiting condition. For this reason, the practical upper limit of the thickness d of the cap layer is considered to be about 3000 layers. The first reason why the structure of this embodiment reduces the source resistance compared to the conventional one is that the thickness of the cap layer 24 is increased, which improves the contact resistance between the cap layer 24 and the source and drain electrodes 25 and 26. , and the second reason is that 11 composition change layers (gn-8I!X Ga1-X
This is considered to be because the contact resistance between the cap layer 24 and the carrier supply layer 23 was reduced by introducing S) into the carrier supply layer 23.

〔Effect of the invention〕

As is clear from the above, according to the present invention, by making the thickness of n-GaAs of the cap layer 1000 Å or more, the contact resistance and source resistance of the Peter junction F'ET can be reduced. Therefore, it is possible to further improve the device characteristics of the Peter junction FET.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the dependence of contact resistance on the thickness of the n-GaAs layer of the cap layer, FIG. 2 is a diagram showing a heterostructure of an embodiment of the present invention, and FIG. 3 is a diagram of the structure of the embodiment. Figure 4 is a diagram showing the contact resistance when making direct contact with the two-dimensional electron gas layer. Figure 5 is a diagram showing the measurement results of the source resistance of a conventional heterojunction FET.
FIG. 21 is a semiconductor insulating GaAs substrate, 22 is an i-GaAs semiconductor layer on which a two-dimensional electron gas layer (2DEC) 27 is formed, and 23 is an n-8 (l x Gap-x As) carrier supply layer.
24 is n-GaAs in the cavity layer. 25. 26 is the source electrode and drain electrode, respectively. Patent agent: Fujitsu Limited Representative, Patent attorney, Gobe Tamamushi (one other person). Relationship between thickness and contact resistance. Fig. 1 shows the heterostructure of the embodiment Fig. 2 shows the measurement results of the source resistance of the embodiment Fig. 2 Fig. 2 shows the contact resistance for DEG
Figure 5 Cross-sectional view of conventional device

Claims (2)

[Claims] (1) An undoped GaAs layer, an n-type impurity-doped AlGaAs layer, and n-type GaAs that are lattice matched to each other are arranged adjacent to each other in that order, and the undoped GaAs is
In a field effect semiconductor device in which a two-dimensional electron gas layer is formed near the interface on the aAs side, the thickness of the n-type GaAs layer is 1100 Å or more, and the source and drain are in ohmic contact with the n-type GaAs layer. A field-effect semiconductor device comprising: alloy electrodes formed thereon, each forming an ohmic connection with the two-dimensional electron gas layer. (2) The electric field according to claim 1, characterized in that the AlGaAs layer doped with the n-type impurity is formed such that the proportion of Al on the side in contact with the n-type GaAs layer is reduced. Effective semiconductor device.