JPS62216444A - Code conversion method - Google Patents

Abstract

PURPOSE:To suppress increase of number of circuit elements and save power consumption by converting data signals of n-bit code constitution to data signals of (n+1)-bit code constitution and using specific (n+1)-bit code which is not used as code for data for a frame synchronizing signal. CONSTITUTION:An nB(n+1)B-code converting circuit 2 is provided, and input signals 1 of n-bit data are converted to (n+1)-bit code in a data converting section 3 and a frame signal 6 is added to data signals as a unique word of (n+1)-bit constitution in a unique word preparing section 4. Data signals and frame signal converted in the converting circuit 2 are converted to serial signals by a parallel serial converting circuit 5 and sent out output signals. The data converting section 3 converts data signals to (n+1)-bit code having little continuation of the same code, and the unique word preparing section 4 sends out the unique word instead of data signals when the frame signal 6 is given.

Description

[Detailed description of the invention] [Signature required] When adding a frame synchronization signal to a data signal, a data signal with an n-bit code configuration is converted to a data signal with an (n+1) bit code configuration, and the frame synchronization signal is A specific (n+1) bit code that is not used as a data code is used.

This code conversion reduces the number of consecutive identical codes (n+1
) A signal with a bit code configuration is used as a data signal, and a signal with a configuration not used as a data signal can be assigned as a frame signal, so there is no need to assign a special signal as a frame signal.

[Industrial application field]

The present invention relates to improvements in code conversion methods.

A data signal, such as an image signal, is converted from analog to digital and parallel to serial before being transmitted.

On the receiving side, when reproducing the original signal, a synchronization signal is required to convert the received serial signal into a parallel signal at the correct time.

For this purpose, the transmitting side sends out a frame synchronization signal together with the data signal. In this case, it is desirable not to complicate the device configuration and increase circuit scale and power consumption due to frame synchronization.

[Conventional technology]

Conventionally, when transmitting a data signal, particularly an image signal, the image signal is first subjected to analog-to-digital conversion, then parallel-to-serial conversion, and sent to a transmission line as a serial signal.

On the receiving side, a frame synchronization signal is required to convert the received serial signal into a parallel signal.

Therefore, during code conversion during transmission, for example, an 8-bit image signal is converted into a 9-bit signal by adding a 1-bit frame signal for frame synchronization.

However, if this 9-bit code is sent to the transmission line as it is, continuous "0" or continuous "1" will occur in the data signal, making it difficult to extract the synchronization signal on the receiving side. , conventionally, 9B10B code conversion etc.
A method is used to prevent "1" continuation and "1" continuation.

In this method, a 9-bit signal is further added with a 1-bit sign to become a 10-bit signal.

For 8-bit image data, 2 bits of extra data are required for the transmission path.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional frame synchronization method, the number of transmission bits increases, resulting in a high bit rate (which means that the transmission speed must be increased.As a result, the number of circuit elements used also increases, leading to an increase in power consumption. There are drawbacks.

[Means for solving problems]

The above problem can be solved by providing an n B (n+1)B code conversion circuit 2 and converting an input signal 1 of n-bit data into (n+
1) Convert the frame signal 6 into a focus code, and add the frame signal 6 to the data signal as a unique word of (n+1) bit configuration in the unique word creation section 4. The data signal and frame signal thus converted in the conversion circuit 2 are converted into serial signals by the parallel-to-serial conversion circuit 5, and the output signal 7 is output.
Send as. The data converter 3 converts the data signal into an (n+1) bit code with fewer consecutive identical codes, and the unique word generator 4 converts the data signal into a unique word instead of the data signal when the frame signal 6 is given. send out.

[Effect]

According to the present invention, as shown in FIG. 1, an n-bit data signal string is converted into an (n+1)-bit code by the data conversion unit 3 of the nB (n+1)B code conversion circuit 2. This (n+1)-bit configuration code is larger in number than the n-bit configuration code, and makes it possible to select only a code configuration with as few consecutive "0"s and consecutive "1s" as possible.

In addition, the frame signal is configured to select a code that is not assigned to a data signal from among the (n+1) bit configuration codes, and a code that is continuous "0" or "1" and is used as a unique word. I can do it.

On the receiving side, the frame synchronization signal can be easily detected by using this unique word pattern detection circuit.

In this way, the transmission signal is an (n+1) bit code, and it is possible to transmit the synchronization frame signal and the data signal.

〔Example〕

The present invention will be explained according to illustrated embodiments.

FIG. 2 is a block diagram of a transmitting side device according to an embodiment of the present invention when transmitting an image signal as a data signal, FIG. 3 is a block diagram of an 889B code according to an embodiment of the present invention, and FIG. 4 is a transmission signal arrangement FIG. 5 shows a block circuit diagram of a receiving side device according to an embodiment of the present invention.

In FIG. 2, the image signal is supplied as an 8-bit input signal 21 to an 889B converter 25 via a flip-flop circuit 23. Further, the frame signal 22 is supplied to an 889B conversion device 25 via a flip-flop circuit 24.

The 889B converter 25 converts an 8-bit input signal into a 9-bit signal as already explained in FIG. Insert.

This selection is performed by the selection circuit 8.

Here, the relationship between the n-bit signal and the n-bit code is shown in Table 1, and the relationship between the (n+1)-bit signal and the (n+1)-bit code is shown in Table 2.

Note that here n=8.

In Figure 3, the 9-bit code structure is oooo at the bottom.
There can be 512 values between the oooooo configuration and the 111111111 configuration at the top. On the other hand, an input signal having an 8-bit configuration has only 256 types of values. Therefore, in the case of a 9-bit code structure, for example, select only the code structure with few consecutive "O" or "1"s in the part shown in FIG. 3 and FIG.
It can be made to correspond to In the 889B conversion, conversion to a signal having the code structure selected in this manner is performed.

That is, the correspondence between the n pinto code and the (n+1) pinto code can be established, for example, as shown in Table 3.

Furthermore, a unique word indicated by .largecircle. in FIG. 3 is used as a synchronization signal, and when a frame signal is given, the unique word .largecircle. is inserted in place of the data signal resulting from 889B conversion.

That is, in the case of a frame signal, a code that is not used for data signal conversion, for example, a code having the following structure can be used as a unique word.

The signal subjected to 889B conversion in this manner and to which a frame synchronization signal is added is applied to a parallel-to-serial conversion circuit 27 via a flip-flop circuit 26, where it is converted into a serial signal and sent to a transmission line.

In FIG. 4, 22 indicates the waveform of the frame signal. Every time the frame signal 22 is supplied to the 889B conversion circuit,
The unique word (3) is transmitted as a synchronization signal. Continuing from this, the signal in the region (2), which has been converted to an 889B code of the television signal, is sent out.

The receiving side device is shown in the block circuit diagram of FIG.

The received serial signal is converted into parallel signals by the serial/parallel conversion circuit 31.
The 9888 decoding circuit 32 detects a unique word and outputs it as a frame signal 35, and the image signal converted to 8 bits is output as an image output signal 34 via a flip-flop circuit 33.

〔Effect of the invention〕

According to the present invention, the frame signal can be configured as a unique word in the (n+1) bit configuration without providing it as a separate code. Furthermore, the present invention provides a synchronization device that can lower the transmission bit rate, suppress the increase in the number of circuit elements, keep the circuit scale small, and reduce power consumption, which has extremely large effects.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention. FIG. 2 is a block circuit diagram of a transmitting side device according to an embodiment of the present invention. FIG. 3 is a diagram of the 889B code configuration according to an embodiment of the present invention. , FIG. 5 is a block circuit diagram of a receiving side device according to an embodiment of the present invention. In the figure, 1.21 is an input signal, 2 is an nB (n+1)B conversion circuit, 3 is a data conversion section, 4 is a unique word creation section, 5.27 is a parallel-to-serial conversion circuit, 6.22 is a frame signal, 8 23.24, 26, 33.36 are flip-flop circuits FF, 25 is an 889B conversion circuit, 31 is a serial-parallel conversion circuit, 32 is a 9888 decoding circuit, ■ is a unique word area, ■ is an 889B code configuration area shows. Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A specific (n+1)B code that converts a data signal with an n-bit code to nB(n+1)B code, and uses a frame synchronization signal as a unique word that is not used for code conversion of the data signal.
A code conversion method characterized by adding a code.