JPS62216361A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62216361A JPS62216361A JP5823986A JP5823986A JPS62216361A JP S62216361 A JPS62216361 A JP S62216361A JP 5823986 A JP5823986 A JP 5823986A JP 5823986 A JP5823986 A JP 5823986A JP S62216361 A JPS62216361 A JP S62216361A
- Authority
- JP
- Japan
- Prior art keywords
- barrier
- carrier
- height
- hetero
- effective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 239000000969 carrier Substances 0.000 claims description 8
- 238000005452 bending Methods 0.000 claims description 4
- 125000005842 heteroatom Chemical group 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract description 3
- -1 HET in which InGaAs Chemical class 0.000 abstract 1
- 230000001788 irregular Effects 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001803 electron scattering Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7606—Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ヘテロ接合面垂直方向に移動するキャリヤが越す障壁の
実効高さを、障壁側に選択ドーピングを施こすことによ
って、調整し、半導体装置の特性向」−に寄与する。[Detailed Description of the Invention] [Summary] The effective height of the barrier over which carriers moving in the direction perpendicular to the heterojunction surface is adjusted by selectively doping the barrier side, thereby improving the characteristics of semiconductor devices. Contribute to
本発明はへテロ接合面に対し垂直方向の輸送現象を利用
する半導体装置に係り、特にヘテロ障壁の高さをヘテロ
接合半導体の組成調整に３Ｊらず、調整できる化合物半
導体装置に関する。The present invention relates to a semiconductor device that utilizes a transport phenomenon perpendicular to a heterojunction surface, and particularly to a compound semiconductor device in which the height of a heterobarrier can be adjusted without adjusting the composition of a heterojunction semiconductor.
ヘテロ接合構造を有する半導体装置としてはＡｌＧａＡ
ｓ／ＧａＧａＡｓ１ｌＥが著名であるが、ＩＩＥＭＴと
は輸送方向が異なりへテロ接合面に対し垂直方向の輸送
方向を有するホットエレクトロントランジスタ（ＩＩＥ
Ｔ）、なども近年注目されている。１１［Ｔでは、一般
に半絶縁性バリヤとして＾ｌＧａＡｓを用い、エミッタ
、ベースおよびコレクタとしてｎ１４ＱＧａＡｓが用い
られる。ＩＩＢＴでは、エミッタ・ベース間のバリヤ（
＾］ＧａＡｓ）およびベース（ＧａＡｓ）をエレクトロ
ンがピコ秒程度の高速で横切る。As a semiconductor device having a heterojunction structure, AlGaA
s/GaGaAs11E is well-known, but the transport direction is different from that of IIEMT, and hot electron transistor (IIE
T), etc. have also received attention in recent years. 11[T generally uses ^lGaAs as the semi-insulating barrier and n14QGaAs as the emitter, base and collector. In IIBT, the emitter-base barrier (
^]GaAs) and the base (GaAs) at a high speed of about picoseconds.
１１８１においてバリヤの高さが低ずぎるとリーク電流
が多くなり、逆に高すぎるとエレクトロンがバリヤを乗
り越えられなくなるのでＧａＡｌＡｓの組成調整により
所望のバリヤの高さが与えられている。In 1181, if the height of the barrier is too low, leakage current will increase, and if it is too high, electrons will not be able to overcome the barrier, so a desired barrier height is provided by adjusting the composition of GaAlAs.
ＨＥＴのエミッタに注入されたエレクトロンのうちコレ
クタに達したエレクトロンとコレクターに達せずベース
電流に収集されたエレクトロンの割合をＮ？Ｒ増幅率と
称する。電流増幅率を高めるうえでひとつの問題は、ベ
ース領域における伝導帯のＬ （エル）又はＸ（エック
ス）点におけるエネルギレベルが低いと、ベースに注入
されたエレクトロンが伝導帯で散乱されベース電流とな
り、このため電流増幅率が少なくなるという所にある。Among the electrons injected into the HET emitter, the ratio of electrons that reached the collector to those that did not reach the collector and were collected in the base current is N? It is called R amplification factor. One problem in increasing the current amplification factor is that if the energy level at the L or X point of the conduction band in the base region is low, electrons injected into the base will be scattered in the conduction band and become a base current. , therefore, the current amplification factor decreases.
第２図は、ベース領域におけるエレクトロンの散乱の概
念図であり、図中Ｅ、Ｂ、Ｃはそれぞれエミッタ、ベー
ス、コレクタであり、Ｂｒはバリヤ、ＥｃはベースＢに
おける１、点又はＸ点の伝導帯を示す。第２図に図解し
た如きエレクトロンの散乱を抑制する一つの方法として
、エミッタとベース間の障壁高さを変える方法がある。FIG. 2 is a conceptual diagram of electron scattering in the base region. In the figure, E, B, and C are the emitter, base, and collector, respectively, Br is the barrier, and Ec is the point 1 or point X in the base B. Indicates conduction band. One method for suppressing electron scattering as illustrated in FIG. 2 is to vary the barrier height between the emitter and the base.
従来から障壁高さを変える方法としては母体結晶の組成
を変える方法がある。A conventional method for changing the barrier height is to change the composition of the host crystal.
ところがＧａＡｓ −ＡｌＧａＡｓのような格子の整合
性がより系では上記の方法を採ることができるが、Ｉｎ
ＧａＡｓ／ＩｎＰ、 ＩｎＡｌ＾ｓ／ＴｎＧａＡｓのよ
うな系では母体結晶の組成を変化させた場合格子不整が
著しくヘテロ接合界面付近の結晶性を低下させる欠点が
ある。本発明は、ヘテロ障壁層の母体結晶の１１１成は
変化させずにヘテロ界面における実効的な障壁高さを変
化させる手段を捉供することによって、ヘテロ接合半導
体装置の特性を適切に設計することを目的とする。実効
的な障壁高さを変化させることによりエミッタからベー
スへのキャリヤのｎ人あるいはベースからコレクタのキ
ャリヤの注入を所望に制御することをも発明の目的とす
る。However, the above method can be used for systems with better lattice matching, such as GaAs-AlGaAs, but in
Systems such as GaAs/InP and InAl^s/TnGaAs have the disadvantage that when the composition of the host crystal is changed, the lattice misalignment is significant and the crystallinity near the heterojunction interface is degraded. The present invention makes it possible to appropriately design the characteristics of a heterojunction semiconductor device by providing a means for changing the effective barrier height at the hetero interface without changing the 111 structure of the host crystal of the hetero barrier layer. purpose. It is also an object of the invention to control the desired injection of carriers from the emitter to the base or from the base to the collector by varying the effective barrier height.
本発明は、ヘテロ接合を用い１つへテロ接合面に対し垂
直方向のキャリヤの輸送現象を利用する素子において、
ヘテロ接合の障壁層側の一部に選択ドーピングを施すこ
とによってバンドの曲りを生しさせキャリヤが越すべき
実効的な障壁の高さを調整できることを特徴とする。The present invention provides an element that utilizes a carrier transport phenomenon in a direction perpendicular to one heterojunction surface using a heterojunction.
It is characterized in that selective doping is applied to a part of the barrier layer side of the heterojunction to cause band bending and to adjust the effective height of the barrier over which carriers should pass.
本発明によれば、ヘテロ障壁層の一部に選択ドーピング
をほどこし、電子親和力の差によって起こる電子の移動
の結果性じるハンドの曲がりを利用しキャリヤが越えよ
うとする実効的な障壁の高さを変化させるので、格子不
整合を回避し、例えば格子定数比率ΔＡ／Ａ≦１０−３
を確保することができる。本発明は、ＩｎＰ基板上にＩ
ｎＧａＡｓ、 ＩｎＡｌＡｓを積層するｔｌＥＴ、 Ｇ
ａＡｓ基板上にＧａＡｓ、１ｎＧａＰを積層するＩＩＥ
Ｔなど格子不整合が問題になる各種化合物のへテロ接合
デバイスに適用される。According to the present invention, selective doping is applied to a part of the hetero barrier layer, and the effective barrier that carriers try to cross is increased by utilizing the bending of the hand caused by the movement of electrons caused by the difference in electron affinity. By changing the lattice constant ratio ΔA/A≦10-3, for example, lattice mismatch can be avoided.
can be ensured. The present invention provides I
tlET stacking nGaAs and InAlAs, G
IIE for stacking GaAs and 1nGaP on an aAs substrate
It is applied to heterojunction devices of various compounds such as T where lattice mismatch is a problem.
以下、ＩｎＧａＡｓ／ ＩｎＧａＡｓ ＨＥＴの実施例
を説明する。Examples of InGaAs/InGaAs HETs will be described below.
ＩｎＰ（Ｐｅ） ％板を用い、基板温度４７０℃、成長
速度０．５μｍ ／ ｈの条件下でＭＢＥ法により第１
図に層構造を示すＨＥＴを製造した。第１図のＩＩＥＴ
のエネルギバンド図を第３図に示す。図中、３〜９はそ
れぞれ第１図の層の番号に該当する。第１図において各
層は次のとおりである。ｌ −１ｎＰ（Ｆｅ）基板、２
はコレクタコンタクトとして用いられる２５００人厚の
０ ’ −１ｎｏ、 ｓ＋Ｇａｏ、 ａｑ層、３４．
＋１ ルクタであって、５００人厚０ｎ −Ｉｎ６．５
３Ｇａｏ、 ４７＾Ｓ層（コレクタ層、キャリヤ濃度１
×１Ｏ１８／Ｃ１ｎ″）、４，５はベース、コレクタ間
のバリヤであって、４はノーンドープｌｎｏ、 ５Ｊｌ
ｏ、 ＜ａＡｓ層（厚さ１５００人）、５はＩｎｏ、
５ＺＡＩＩ１． ａｓＡｓ層（厚さ１００人、キャリヤ
濃度、ｌ Ｘ Ｉ ＯＩ′／ｃ７） 、６ 、７はベー
スであって、６は２００人厚０ノーンドープＩｎｏ、
５３Ｇａｏ、 ａｑＡｓ層、７は２００人厚０ノｎｏ、
５３Ｇａ０．４’ｌ＾Ｓ層（キャリヤ濃度、Ｉ Ｘ
１０ ”／ｃ＋ＩＩ） 、８はハ’）ヤテｔｒ）−）”
’（，３００人厚０ノンドープＩｎ６．５ＪＩｏ、 ４
８＾Ｓ層、９はエミッタであって、１０００人厚の人厚
ｏ、 ５ｓＧａｏ１７八Ｓ層、１０は３０００人厚のＩ
ｎｏ、 ５ｓＧａｏ、 ４？Ａ３層（エミッタコンタク
ト）である。ベースとコレクタの間のバリヤのエレクト
ロン注入側（５）をドープすることによってハンドの曲
りを生ぜしめた。また、バリヤ４゜５のうちコレクタ側
（４）はノンドープとしているためコレクタ３から見た
障壁の高さは高い。よってコレクタ３に一旦注入された
エレクトロンがバリヤ４，５をとび越してベースにエレ
クトロンがベースに流れることはなくなる。Using an InP(Pe)% plate, the first step was performed using the MBE method under conditions of a substrate temperature of 470°C and a growth rate of 0.5 μm/h.
A HET whose layered structure is shown in the figure was manufactured. IIET in Figure 1
The energy band diagram of is shown in Fig. 3. In the figure, 3 to 9 correspond to the layer numbers in FIG. 1, respectively. In FIG. 1, each layer is as follows. l −1nP(Fe) substrate, 2
is a 2500-layer thick 0'-1no, s+Gao, aq layer used as a collector contact, 34.
+1 Lucta, 500 people thickness 0n -In6.5
3Gao, 47^S layer (collector layer, carrier concentration 1
×1O18/C1n''), 4 and 5 are barriers between the base and collector, 4 is undoped lno, 5Jl
o, <aAs layer (thickness 1500 layers), 5 is Ino,
5ZAII1. asAs layer (thickness 100, carrier concentration, lXIOI'/c7), 6 and 7 are bases, 6 is 200 layers thick, 0 undoped Ino,
53 Gao, aqAs layer, 7 is 200 people thick 0 no,
53Ga0.4'l^S layer (carrier concentration, I
10 "/c+II), 8 is ha') Yatetr)-)"
'(, 300 people thickness 0 non-doped In6.5 JIo, 4
8^S layer, 9 is the emitter, 1000 people thick O, 5sGao178S layer, 10 is 3000 people thick I
no, 5sGao, 4? This is the A3 layer (emitter contact). Hand bending was created by doping the electron injection side (5) of the barrier between base and collector. Further, since the collector side (4) of the barrier 4.5 is non-doped, the height of the barrier seen from the collector 3 is high. Therefore, the electrons once injected into the collector 3 will no longer jump over the barriers 4 and 5 and flow to the base.
さらに、ベース６．７のエレクトロン注入側（７）にも
ドーピングした。Furthermore, the electron injection side (7) of the base 6.7 was also doped.
上記１１ＥＴをベース接地、Ｖｅｂ＝０．６ Ｖ、Ｖｃ
ｂ−１■の条件で電流増幅率を測定したところ４であっ
た。一方、比較のために、第１図の５をノンドープｌｎ
ｏ、 ｓ□Ａ１゜、４８＾Ｓに変えたＨＵＴの電流増幅
率を測定したところｌであった。Ground the base of the above 11ET, Veb=0.6 V, Vc
When the current amplification factor was measured under the conditions of b-1■, it was 4. On the other hand, for comparison, 5 in Fig. 1 is undoped ln
o, s□A1°, and the current amplification factor of the HUT changed to 48^S was measured and was l.
本発明によればエミッタより注入されたキャリヤが越す
べきコレクター障壁の高さを低くできるので電流利得を
大きくできる効果がある。またコレクター領域から見た
障壁の高さは変わらない利点も有する。According to the present invention, the height of the collector barrier that carriers injected from the emitter must overcome can be lowered, resulting in the effect of increasing the current gain. It also has the advantage that the height of the barrier as seen from the collector area does not change.
第１図は本発明の一実施例によるＩＩＥＴの層構造を示
す図面、
第２図はへテロ接合垂直方向にキャリヤを注入する半導
体装置における散乱の説明図、第３図は第１図のＨ１！
Ｔのエネルギパン１゛図である。
３・・・コレクター、 ４．５・・・バリヤ、６．
７・・・ベース、 ８・・・バリヤ、９・・
・エミッタ。FIG. 1 is a diagram showing the layer structure of an IIET according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of scattering in a semiconductor device in which carriers are injected vertically to a heterojunction, and FIG. 3 is an illustration of H1 in FIG. !
It is an energy pan diagram of T. 3...Collector, 4.5...Barrier, 6.
7...Base, 8...Barrier, 9...
・Emitter.
Claims (1)
のキャリヤの輸送現象を利用する素子において、ヘテロ
接合の障壁層側の一部に選択ドーピングを施すことによ
てバンドの曲りを生じさせキャリヤが越すべき実効的な
障壁の高さを調整できることを特徴とする半導体装置。1. In a device that uses a heterojunction and utilizes the transport phenomenon of carriers in the direction perpendicular to the heterojunction surface, selective doping is applied to a part of the barrier layer side of the heterojunction to cause band bending and transport the carriers. A semiconductor device characterized in that the height of an effective barrier to be overcome can be adjusted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5823986A JPH07105488B2 (en) | 1986-03-18 | 1986-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5823986A JPH07105488B2 (en) | 1986-03-18 | 1986-03-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62216361A true JPS62216361A (en) | 1987-09-22 |
| JPH07105488B2 JPH07105488B2 (en) | 1995-11-13 |
Family
ID=13078550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5823986A Expired - Lifetime JPH07105488B2 (en) | 1986-03-18 | 1986-03-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105488B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4999697A (en) * | 1988-09-14 | 1991-03-12 | At&T Bell Laboratories | Sequential-quenching resonant-tunneling transistor |
| JPH0380543A (en) * | 1989-08-24 | 1991-04-05 | Fujitsu Ltd | Semiconductor device |
| US5012318A (en) * | 1988-09-05 | 1991-04-30 | Nec Corporation | Hybrid semiconductor device implemented by combination of heterojunction bipolar transistor and field effect transistor |
| US5111265A (en) * | 1988-12-06 | 1992-05-05 | Nec Corporation | Collector-top type transistor causing no deterioration in current gain |
| US5138408A (en) * | 1988-04-15 | 1992-08-11 | Nec Corporation | Resonant tunneling hot carrier transistor |
| JP2006297273A (en) * | 2005-04-20 | 2006-11-02 | Nippon Steel Corp | Catalyst for f-t synthesis reaction |
-
1986
- 1986-03-18 JP JP5823986A patent/JPH07105488B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5138408A (en) * | 1988-04-15 | 1992-08-11 | Nec Corporation | Resonant tunneling hot carrier transistor |
| US5012318A (en) * | 1988-09-05 | 1991-04-30 | Nec Corporation | Hybrid semiconductor device implemented by combination of heterojunction bipolar transistor and field effect transistor |
| US4999697A (en) * | 1988-09-14 | 1991-03-12 | At&T Bell Laboratories | Sequential-quenching resonant-tunneling transistor |
| US5111265A (en) * | 1988-12-06 | 1992-05-05 | Nec Corporation | Collector-top type transistor causing no deterioration in current gain |
| JPH0380543A (en) * | 1989-08-24 | 1991-04-05 | Fujitsu Ltd | Semiconductor device |
| JP2006297273A (en) * | 2005-04-20 | 2006-11-02 | Nippon Steel Corp | Catalyst for f-t synthesis reaction |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07105488B2 (en) | 1995-11-13 |
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