JPS60149169A - Field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To enable superhigh-speed action at a low temperature by utilizing that the eletron concentration in two bi-dimensional electron gas layers generated between two hetero junctions in a quantum well is given and taken by an electric field. CONSTITUTION:A source electrode 11 and a drain electrode 12 are formed on n<++> GaAs layers 10 and are in substantially ohmic contact with either one of the bi-dimensional electron gas layers 7A or 7B generated in the quantum well in the neighborhood of the double hetero junction constituting the quantum well. A gate electrode 13 is formed after the surface of an n type AlGaAs layer 9 is exposed by selective removal of the GaAs layer 10 on the part scheduled for gate electrode formation. A back gate bias electrode 14 is formed on an exposed non-doped Al0.3 Ga0.7As layer 6. Then, the electron temperatures of channel layers 7A and 7B are controlled by impressing a bias voltage on the hetero junction in a vertical direction by utilizing the electrodes 13 and 14. Therefore, the electron temperature varies rapidly thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a field effect semiconductor device called a floating channel transistor (FCT) which is capable of ultra high speed operation.

Prior Art and Problems Conventionally, high electron mobility transistors have been used as field effect transistors having a heterojunction.
n mobility transistor:HF,
M'l') is known.

However, in HEMT, electrons to the channel generated in the non-doped GaAs layer are supplied from deep impurity (Si) units in the n-type A11GaAs layer, which limits the switching speed. It cannot be avoided.

In addition, it has two heterojunctions, and a two-dimensional connection between the petrojunctions is formed through a potential barrier created by a non-doped GaAs layer in a quantum well (QW) generated by the two heterojunctions. Speed modulation transistor using exchange of electron gas layer (HoSakaki
JJAP Vol.

21 Magneto 6 (1982) LaB5-L383)
has also been proposed, but in that case, the source and drain contacts are made to the two two-dimensional electron gas layers generated near the two heterojunctions, so the exchange of the two-dimensional electron gas layers and the electron The disadvantage is that the exchange of concentrations does not correspond.

Purpose of the Invention The present invention utilizes the fact that the electron concentrations in two two-dimensional electron gas layers generated between two heterojunctions in a QW are exchanged by an electric field. A field effect semiconductor device called FCT that operates at high speed is provided.

Structure of the Invention The field effect semiconductor device of the present invention includes a double heterojunction that constitutes a quantum well, and a two-dimensional electron gas layer that is a channel generated in the quantum well near the double heterojunction. A source electrode and a drain electrode that are in substantially ohmic contact with one of them, and an electric field formed between the source electrode and the drain electrode in a direction crossing the heterojunction to control the electron concentration in the channel. The structure includes a gate electrode.

In this way, the exchange of electron concentrations in the two two-dimensional electron gas layers generated between the two heterojunctions is controlled by the electric field applied in the direction crossing the heterojunction by the gate electrode. Therefore, the electron concentration in the two-dimensional electron gas layer serving as the channel, that is, the current value, can be controlled at high speed.

Examples of the invention FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention.

In the figure, l is a semi-insulating GaAs 1 plate, 2 is a non-doped GaAs buffer layer, and 3 is an impurity concentration of, for example, 6.
X 10 I9 (cm-') and the thickness is, for example, 10
The n++ type GaAs back gate layer has a thickness of, for example, l 000' (person).
Doped A 126,3 Ga o, I As layer, 5
For example, if the impurity concentration is 2 x I O” (cm-”)
n-type A6Ga with a thickness of, for example, 100 [people]
6 is a non-doped A 140,3G a □, 7A s layer having a thickness of, for example, 60 [people], 7 is a non-doped GaAs layer having a thickness of, for example, 500 [people];
7A and 7B are two-dimensional electron gas layers, and 8 is a layer with a thickness of, for example, 6.
゜ [person] Non-dope A It6.3G a O
, 7A s layer, 9 has an impurity concentration of, for example, 2×1OIll.
(CIll-3) with a thickness of, for example, 500 [people], IO has an impurity concentration of, for example, 6
X10” (cm −3) and the thickness is, for example, 300 [
n++ type GaAs layer 11, source electrode 1
2 is a drain electrode, 13 is a gate electrode, and 14 is a back electrode.
Gate bias electrodes, 14A each indicate an alloyed layer.

As can be seen from the figure, this example uses AlGaAs/GaAs
The system has a multi-layered heterostructure.

Each semiconductor layer is formed by MBE (molecular beam)
It can be easily formed by applying the epitaxy method.

The source electrode 11 and the drain electrode 12 are formed by depositing Au on the Sn-doped n++ type GaAs layer 10, and an ohmic contact can be obtained without requiring any heat treatment for alloying.

The gate electrode 13 is placed on the portion where the gate electrode is to be formed (7)
It is formed by selectively etching and removing the n''+ type GaAs layer 10 to expose the surface of the n type AIGaAs Jif9(7), and then depositing AJ.

The bank gate bias electrode 14 is made of non-doped A#o, 3Ga (
The alloyed layer 14A is formed by depositing Au-Ge/Au on the 1,7As layer 6, and by performing alloying heat treatment.

To form each of the electrodes, first, the bank, gate, and bias electrodes 14 and their alloying are formed, then the source electrodes 11 and the train electrodes 12 are formed, and finally the gate electrodes 1
Perform in the order of formation in step 3.

FIG. 2 is an energy hand diagram directly below the gate electrode 13 in the non-biased state of the embodiment shown in FIG. 1, and the same parts as those explained in connection with FIG. .

In the figure, %EF indicates the Fermi level, G indicates the gate electrode side, and BG indicates the back gate bias electrode side.

The third page is a diagram showing the results of theoretical calculations of the wave function of electrons in the quantum well shown in Figure 2, with the vertical axis representing energy (e V) and the horizontal axis representing distance [person]. ] are taken respectively.

In the figure, 1ζ5 12 represents the square of the absolute value of the wave function ζ1 of the i-th excited state, and therefore represents the electron density distribution of electrons in this state, and EL represents the energy level in that state. It shows.

The concentration of electrons in the i-th excited state (sheet carrier concentration) ni is approximately ni = (Ey
E=)xi).

h" m″: Effective mass of electron h blank constant is given by

Therefore, in the case of FIG. 3, the electrons are mainly i=Q.

1 (0 represents the ground state), and the electron density is localized at the two heterointerfaces.

FIG. 4 shows the gate electrode 1 seen in the embodiment shown in FIG.
3 and the back gate bias electrode 14 to apply a bias voltage (0,4 (V)
) is a diagram showing the state of the wave function when applying
The same parts as those explained in connection with FIG. 3 are indicated by the same symbols.

As is clear from the figure, electrons are mainly on the surface side (left side of the figure)
The electrons move to a new ground state localized at the hetero interface (channel interface) of the substrate, and there are no electrons at the hetero interface (floating channel interface) on the substrate side (right side of the figure).

FIG. 5 shows i=0.1 when changing the bias voltage.
FIG. 2 is a diagram showing the distribution of electron concentration at each level of FIG.

In this figure, No is ζ seen in Figure 3.

In addition, N1 similarly corresponds to ζ1, and N3 similarly corresponds to ζ3.

FIG. 6 is a diagram showing the characteristics of the field effect semiconductor device (FCT) of the present invention determined from the above data, in which the vertical axis represents the drain current 4, and the horizontal axis represents the drain voltage Va.

The gate voltage vg in this figure is between the left and right vertical axes in Figure 3, that is, the distance from -100 [person] to 60
0 You can think of it as a voltage applied between [people].

The operating speed in the embodiment can be estimated in the same manner as in the case of the speed modulation transistor.

That is, the electron velocity V in the direction perpendicular to the heterointerface in the quantum well is V=2X10? (cm/s), the layer thickness of the quantum well is d, and d=500 (
-5X 10-', (cm), the electron transfer time τLr between the heterointerfaces is τt, = =2.5
x 10-'' [seconds] ■ 10.25 (ps), and extremely high-speed operation is possible.

FIG. 7 is a main part cutaway side view showing another embodiment of the present invention.

In the figure, 21 is a semi-insulating GaAs substrate, 22 is an n+
+ type GaAs layer, 23 is n type AllGaAs layer, 24 is GaAs layer, 24A and 24B are two-dimensional electron gas layers, 2
5 is an n-type AAGaAs layer, 26 is an n-type GaAs layer, 27
27A is a source electrode, 27A is an alloyed layer, 28 is a drain electrode, 28A is an alloyed layer, 29 is a gate electrode, 30 is a back gate bias electrode, and 31 is a surface depletion layer.

In this embodiment, the source electrode 27 and the drain electrode 28
Alloying layers 27A and 28A are formed by applying heat treatment for alloying, and are brought into contact with the two-dimensional electron gas layer 24B generated at the heterointerface on the substrate side.

In this case, since the alloyed layers 27A and 28B are also in contact with the two-dimensional electron gas layer 24A on the surface side, by generating the surface depletion layer 31, the alloyed layers 27A and 28B are
813 and a two-dimensional electron gas layer 24 that can operate as a channel. It is cut off from part A.

Therefore, unlike the conventional example shown in FIG. 1, the two-dimensional electron gas layer 24A on the surface side is a floating channel, and the two-dimensional electron gas layer 24B on the substrate side operates as an actual channel. .

In this embodiment, the channel is in a conductive state, that is, 2
If the operation is performed in a range where a dimensional electron gas layer exists, it is possible to apply a bias voltage to the quantum well without a back gate bias. Also, the back gate bias electrode 30 may not be provided.

In each of the above embodiments, in order to supply electrons to the quantum well to generate a two-dimensional electron gas layer, electrons are supplied from the n-type AlGaAs layers existing on both sides of the quantum well. For the supply, the GaAs layer in the quantum well may be doped with an n-type impurity, for example, St, and electrons may be supplied from there. In that case, in order to take advantage of the high mobility characteristics of the two-dimensional electron gas layer that becomes the channel, modulation doping is applied in which the GaAs layer on the channel side is non-doped and the GaAs layer on the floating channel side is n-type. It is preferable.

FIG. 8 is a cutaway side view of essential parts of such an embodiment,
It shows the state where voltage is applied.

In the figure, 31 is a non-doped Al1GaAs layer;
2 is a non-doped GaAs layer, 32A is a non-doped G layer
For example, if St is added as an impurity to the aAs layer 32, 2X IQ
The n-type GaAs layer 33 is a non-doped AnGaAs layer introduced to have a concentration of approximately
Layer 34 indicates a two-dimensional electron gas layer, respectively. In this case, the non-doped GaAs layer 32 and the n-type G
The thickness of each a A s layer 32A is 250 [people]
It is.

Effects of the Invention The field-effect semiconductor device of the present invention includes a double heterojunction that constitutes a quantum well, and a two-dimensional electron gas layer that is a channel generated within the quantum well in the vicinity of the double heterojunction. The electron concentration in the channel is increased by applying an electric field for 1 hour to the source electrode and the drain electrode that are in substantial ohmic contact with one of them, and to the one formed between the source electrode and the drain electrode that intersects the heterojunction. Since the configuration includes a gate electrode for controlling, the two electrodes are in ohmic contact with the source electrode and the drain electrode.
The concentration of electrons in a channel consisting of a dimensional electron gas layer,
Therefore, the conductivity changes extremely rapidly depending on the gate voltage applied to the gate electrode, and the response speed of current value modulation between the source and drain when the gate voltage is modulated is on the order of picoseconds (ps). It is much faster than conventional HEMTs, and can provide greater conductivity modulation than velocity modulated transistors.

[Brief explanation of drawings]

Fig. 1 is a cutaway side view of essential parts of an embodiment of the present invention, Fig. 2 is an energy band diagram when the embodiment shown in Fig. 1 is in a non-biased state, and Fig. 3 is the same as Fig. 1. A diagram showing the state of the wave function in the quantum well in the example shown. Figure 4 is a diagram similar to Figure 3 when a bias voltage is applied. Figure 5 is a diagram showing the state of the wave function in the quantum well in the example shown. FIG. 6 is a diagram showing the voltage/current characteristics, FIG. 7 is a cutaway side view of main parts of another embodiment of the present invention, and FIG. 8 is a diagram showing the distribution of electron concentration when FIG. 7 is a cross-sectional side view of a main part of still another embodiment of the present invention. In the figure, l is a semi-insulating GaAs substrate, 2 is a non-doped GaAs buffer layer, and 3 is an impurity concentration of, for example, 5.
X jQ I9 (cm-3) and the thickness is, for example, 10
00 (person) n++ type GaAs back gate layer, 4 is a non-doped A E g, 3G a (1,7A s layer) whose thickness is, for example, 1000 (person), 5 is an impurity concentration of, for example, 2 n-type AlGaAs with a thickness of, for example, 100 [cm-3]
A non-1'-layer whose thickness is, for example, 60 [people].
7 is a non-doped GaAs layer with a thickness of, for example, 500 [layers], 7A and 7B are two-dimensional electron gas layers, and 8 is a layer with a thickness of, for example, 60 [layers]. Non-dope A1! 0.3G
a O,? The A S layer 9 has an impurity concentration of, for example, 2X
10” (cm-”) and the thickness is e.g.
The n-type AlGaAs layer 10 has an impurity concentration of, for example, 6×10" [CII+-3] and the thickness is, for example, 300 [people]. The n+ type GaAs layer 11 is a source electrode, and 12 is a drain. electrode, 13 is a gate electrode, 14
14A indicates a back gate bias electrode, and 14A indicates an alloy layer. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - (80), "c/I(-kT (80), 6/(Zero-cho Figure 6 Figure 7)

Claims (1)

[Claims] 2, which is a double heterojunction constituting a quantum well and a channel generated within the quantum well near the double heterojunction;
A source electrode and a drain electrode are in substantially ohmic contact with either one of the dimensional electron gas layers, and an electric field is applied in a direction crossing the heterojunction formed between the source electrode and the drain electrode to form the channel. A field effect semiconductor device comprising a gate electrode for controlling electron concentration.