JPS62216063A - Switching method for common bus line - Google Patents

Abstract

PURPOSE:To avoid wrong access of a common memory by switching a command bus line after inhibiting the generation of a bus access permitting signal when a switch indicating signal is produced. CONSTITUTION:When an active processor 1 has a fault, a switch indicating circuit 3 outputs automatically or manually the switch indicating signal to a bus access control circuit 19 via a signal line 17. Then the circuit 19 inhibits all permitting signals except for that of an IO device that is allowed to use a common bus line. Furthermore, said allowed permitting signal is also inhibited when no bus use request is delivered any more. Thus a bus switch signal 18 is outputted to a bus switch circuit 8 after the bus access of all IO devices is inhibited. Then the common bus line is switched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] Akira Hongo relates to a common bus line switching method for switching common bus lines of a duplex device.

[Conventional technology]

Conventionally, there were two systems, an active system and a standby system, and an IO control device and common memory were connected to both the common bus line of the active system processor and the common bus line of the standby system processor, and the IO control device and common memory were connected to the common bus line of the active system processor and the standby system processor. In a redundant device that always operates subordinate to the active processor, when a failure occurs in the active processor, the operating processor switches to the standby processor,
The common bus line was also dependent on the processor and switched to the standby system at the same time.

[Problem that the invention seeks to solve]

In the conventional method, if the common bus line is switched while the IC control device is accessing the common memory, incorrect data may be written to the memory or incorrect data may be read from the memory and output to the IO device. There was a case.

[Means for solving problems]

In order to solve these drawbacks, the present invention prohibits generation of a bus access permission signal when a signal instructing switching is generated.

[Effect]

The common bus line is switched in a state where the IO control device does not access the common bus line.

〔Example〕

Next, the present invention will be explained with reference to color planes.

The figure shows one embodiment of the invention. 1 is the active processor,
2 is a standby processor, which connects the common bus line 9 of the active processor 1 and the common bus line 10 of the standby processor 2 to a common memory 4 and l0791j equipment 5 to 7.
is connected. When the IO control devices 5 to T access the common memory 4 using the common bus line, the signal line 1
A bus use request signal is output to ports 1 to 13. The parallel priority type bus access control circuit 19 uses one of the common bus line use permission signal lines 14 to 16 only for the signal with the highest priority among the signals on the signal lines 11 to 13. outputs a usage permission signal. I Off with permission to use
The 1li control device outputs a memory address, data, read or write command to the active common bus line,
A read or write operation to the common memory 4 is executed. When the IO control device finishes using the common bus line, it stops outputting the bus use request signal, so the bus switching circuit 8 uses the bus switching signal 18 to switch between the active common bus line and the standby common bus line. Let's do it. In such a duplex device, when a failure occurs in the active processor 1, a switching instruction signal is automatically or manually input from the switching instruction circuit 3 to the bus access control circuit 19 via the signal line 17. This circuit currently prohibits all signals other than the use permission signals of the IO control devices that are permitted to use the common bus line, and also prohibits the signals that are permitted to use the common bus line when there is no longer a request to use the bus. In this way, after sending bus access permission signals to all ■0 control devices,
A bus switching signal 18 is output to the bus switching circuit 8 to switch the common bus line.

〔Effect of the invention〕

As explained above, in the present invention, when a signal instructing switching is generated, the common bus line is switched after prohibiting the generation of the bus access permission signal, thereby preventing erroneous writing to the common memory. This has the effect that the common bus line can be switched without reading erroneous data from the common memory.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the present invention. 1... Current system processor, 2. Hobby/Kenmachiiso system processor, 3...@-switching instruction circuit, 4... Common memory, 5, 6, 7-... IO system? iKl acupuncture, 8...
Switching control circuit, 9... Active system common bus line, 10
...Standby system common bus line, 11-16... Life common bus line use request signal line, 17...φ fist switching instruction signal line, 19 @@ll - Bus access control circuit.

Claims (1)

[Claims] It has two systems, an active system and a standby system, in which bus access is performed by a bus access permission signal, and the IO control device and common memory are connected to both the common bus line of the active system processor and the common bus line of the standby system processor. However, in the common bus line switching method for switching these common bus lines as necessary, when a signal instructing switching between the active system and the standby system is generated, generation of a bus access permission signal to the IO control device is prohibited, A common bus line switching method characterized by switching a common bus line in a state where an IO control device does not access the common bus line.