JPS62212854A - Automatic error correcting memory device - Google Patents

Abstract

PURPOSE:To correct soft errors to be increased in accordance with time passage by specifying the addresses of a memory element and an error correction detecting memory element to write error-corrected data in all the address spaces of the memory element and the error correction detecting memory element periodically at the time of an automatic reading data correction mode. CONSTITUTION:Data read out by the memory element 2 are sent to an error correcting circuit 5 and data read out by the error correction detecting memory element 3 are detected about the existence of an error by an error detecting circuit 6. When there is no error, the data of the memory element 2 are transferred to a data bus D, but if there is any error, the error is corrected by the circuit 5 and the error-corrected data are transferred to the data bus D and also rewritten in the memory element 2 through a data multiplexer 11. The corrected data are also sent to an error correction detecting bit forming circuit 4 through the data multiplexer 11 and error correction detecting bit data are formed again and written in the circuit 6 and the element 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an automatic error correction storage device used in an electronic control unit mounted on an artificial satellite.

[Technical background of the invention and its problems]

Conventionally, a storage device used in an electronic device 8 for an artificial satellite has a circuit configuration shown in FIG. 2 or 3. Of these, FIG. 2 shows the simplest configuration, in which the memory element 1 is connected to the data bus D, the address bus A1, and the control line C.
Based on the collateral signal sent through the control line Ct, the address signal of the address bus A specifies the address of the storage element 1, and the stored data is read out and transferred to the data bus D. , data from the data bus D is read into the storage element 1.

In the case of the storage device shown in FIG. 2, in devices exposed to radiation such as artificial satellites, the storage element 1 due to radiation
There was a drawback that the soft error (memory error that can be corrected by rewriting) could not be corrected, resulting in a malfunction in the storage device of the electronic device on board the satellite. In the figure, in addition to the memory element 2, an error correction memory element 3, an error correction detection bit generation circuit 4, a bounce detection circuit 6, and an error correction circuit 5t are used to store the control signal of the control line C during writing. Based on this control signal, the address bus A
The address signal of the memory element 2%J4 is used to specify the address of the memory element 3 for correction detection.

In this case, the data from the data path D is temporarily inputted to the correction detection bit generation circuit 4 to generate error correction detection bit data and stored in the 'F4 detection bit generation circuit 3. put.

Furthermore, the data on the data bus D is stored in the memory element 2 at the address specified by the address signal.

On the other hand, when reading the data stored in the memory element 2,
A control signal on the control line C is input to the memory element 2 and the error correction detection memory element 3, an address is designated by the address signal on the address bus A, and the data in the memory element 2 is sent to the error correction detection 5. The data in the error correction detection storage element 3 is read out by the error detection circuit 6 and sent to the error correction circuit 5.

The entertainment correction circuit 5 corrects the read data of the storage element 2 based on the output of the error detection circuit 6 and transfers the corrected data to the data bus D.

In the case of this m3 diagram, it is possible to correct several bits (l to n) of 'fJ4' when reading data from the memory element 2, but if there is an error of one more bit (
2~n+1), m cannot be corrected. Soft errors caused by radiation are related to time; the longer the time, the higher the pA degree of soft errors.

Furthermore, in the case of Fig. 3, several bits (1
Some devices have a function to automatically rewrite when a correctable error (~n) is detected, but some memory elements that are not read frequently may be exposed to radiation, which increases as time passes. There are disadvantages in that soft errors cannot be corrected and problems occur in the storage device of the electronic device onboard the artificial satellite.

[Purpose of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology.
It is an object of the present invention to provide an error correction storage unit Wt for an electronic control unit mounted on an artificial satellite that can be corrected and is resistant to radiation.

[Summary of the invention]

The eye movement VJ4 correction memory device of the present invention generates data for detecting error 9 corrections of data when writing data to a readable memory element, stores it in an error correction detection memory element, and stores the data. When reading the data of the element, the presence or absence of w4b in the data of the storage element for w4 correction detection is detected by the error detection circuit, and if there is no error as a result of the detection of this error detection circuit, the read data of the storage element is unmodified. If there is an error, it is corrected and written to the memory element, and in the automatic correction mode of the output data of the memory element, the error-corrected data between all addresses of the memory element and the memory element for error correction detection is output. 6 times in a periodic manner.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the eye movement V4 correction storage device of the present invention will be described below with reference to the drawings. Figure wIJ1 is a block diagram without the configuration of one embodiment.

In addition to the conventional configuration shown in #43 to the embodiment shown in Figure @1,
Newly, the part indicated by the code 1 onward is added□ In other words, the control signal from the line C is controlled @4.
The address signal on the address bus is input manually to the idQ multiplexer 7, and the address signal on the address bus is input manually to the address multiplexer 8.

On the other hand, the output of w4@signal generation port 9 is output to address counter 10 and control signal multiplex 7. The output of the address counter 10 is sent to the address multiplexer fll.

Control signal multiplexer 1 is connected to f of control line C.
The control signals outputted from the fill signal generation circuit 9 are multiplexed and stored in the memory element 2.
, K so as to be sent to the storage element 3 for error correction StE detection.

Similarly, the address multiplexer 8 multiplexes the address (No. 4 1) from the address bus ^ and the address signal d output from the address counter IO and sends it to the memory element 2.
, and is sent to the slope correction detection storage element 3.

Also, data 6 of data bus D and #J49 are output from correction circuit 5! The data f is multi-electronized by a data multiplexer 1) and outputted to a storage element 2 and a bit generation circuit 4 for detecting one-fold correction.

The output of the error correction detection bit generating circuit 4 is sent to the error detection circuit 6 and the error correction detection storage element St/C.

When reading data from the memory element 2, the data from the memory element 2 is sent to the ridge correction circuit 5, and the data from the error correction detection memory element 3 is sent to the error detection circuit 6. ing. This section detection circuit 6
The output of the error correction circuit n1 is configured to deliver 5Vc.
A data multiplexer 11 for the data of the error correction circuit 5;
Next, the operation of the automatic entertainment correction detection device of the present invention configured as described above will be explained.

The embodiment shown in Figure 1 has an automatic correction mode in addition to the write mode and the read mode. Among these modes, first, in the write mode,
The control signal C on the control line C is sent to the control signal multiplexer 2.
Address signal IF of the address bus A is sent to the memory element 2 and the memory element 3 for error correction detection through the address multiplexer 8'fr: Addressing of the memory element 2 and the memory element 3 for error correction detection is sent through and taper xD
The data d is stored in the storage element 2 through the data multiplexer 11, and is also input to the error correction detection bit generation circuit 4, where the error correction detection bit data is generated.This data is used for error correction detection. Memory element 3
be memorized.

Next, in the data read mode of the storage element 2, the control signal C on the control line C is passed through the control signal multiplexer 7 to the storage element 2 and the memory element 3t/c for detecting the closing correction.
At the same time, the address signal 1 of the address bus
is input to the memory element 2 and the error correction detection memory element 3 through the address multiplexer 8, and the data is read by adding the nl, son, and n addresses. The data read from the memory element 2 is error corrected. The data read out from the storage element 3 for error correction detection and sent to the circuit 5 is sent to the error detection circuit 6. In this error detection circuit 6, the data read out by the storage element 3 for error correction detection is It detects whether there is an error in the error correction circuit 5 and sends the detection output to the error correction circuit 5.

The error correction circuit 5 receives data from the error detection circuit 6, and also
If the error detection circuit 6 detects that there is no error, the data in the storage element 2 is transferred as is from the error correction circuit 5 to the data bus D.Next, the case of the 1 automatic correction mode will be explained. In this case, the input side of the control signal multiplexer 7 is automatically switched to the control signal generation circuit 9 side, and the input side of the address multiplexer 8 is automatically switched to the address counter 10 side.

Assuming that it is now the read mode, the control signal from the control signal generation circuit 9 is sent to the memory element 2 and the memory element 3 for detecting correction of w4 through the control signal multiplexer 7.
L. Further, the output of the suppressing signal generating circuit 9 is sent to the address counter 10, which increases or decreases the n-% count. Specify the address in step 3.

With this, in the same way as in the read mode described above,
The data read out by the memory element 2 is sent to the error correction circuit 5, and the data read out by the error correction detection memory element 3 is detected by the error detection (b) path 6, and the presence or absence of vA is detected. If there is no error, the data in the memory element 2 is transferred to the data bus D in the same manner as described above, but if there is an error, the error is corrected by the error correction circuit 5 and the data is transferred to the data bus D. , through the data multiplexer Ilf, this modified data is sent to the memory element 2 again through the data multiplexer 1lt- to the W14 correction detection bit generation circuit n1 again for error correction detection. Bit data is generated and written into the vA error detection circuit 6 and the error 9 correction detection memory element 3.

The above automatic correction operation is performed as if output from the address counter 1°, and in the end, the error-corrected data of the entire address space of the memory element 2 and the memory element 3 for entertainment correction detection is periodically transferred to the memory element 2. , is written to the error correction detection storage element 3.

〔Effect of the invention〕

As described above, the self-error correction storage device of the present invention can correct data against soft errors that increase over time, is resistant to radiation, and has high reliability over a long period of time. It can be used as a storage device for a required electronic device onboard an artificial satellite.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the automatic read correction storage device of the present invention, and Figures 2 and 3 are blocks of a storage device used in a conventional electronic control unit for artificial satellites. It is a diagram. 2... Memory element, 3... Memory element for error correction detection,
4... WI4 correction detection bit generation circuit, 5...
・Win correction circuit, 6...11#4#) detection circuit, 9・
...Control signal generation circuit □ Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] A read/write memory element, a data generation means for generating data for error correction detection when data is written to the memory element, and an error correction detection memory element for storing data generated by the data generation means. and an error detection circuit that detects the presence or absence of an error in the data of the error correction detection storage element when reading the data of the storage element;
Correction and writing means for outputting the read data of the storage element without modification if there is no error as a result of detection by the error detection circuit, and correcting and outputting the data if there is an error and writing it into the storage element; means for specifying the address of the memory element and the error correction detection memory element in order to periodically write error-corrected data in the entire address space of the memory element and the error correction detection memory element in an automatic correction mode of read data of the memory element; An automatic error correction storage device comprising: