JPH0383300A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve reliability by providing an error correction circuit in EEPROM. CONSTITUTION:A memory cell array for redundant word 3b and the error correction circuit 5 are provided for EEPROM provided with an input buffer 1, an address decoder 2, a memory cell array for data word 3a, a control circuit 4, an input/output buffer 6 and the like. When data is written, a redundant word is generated by the circuit 5 from write data and it is written into the array 3b. At the time of reading, data and the redundant word are read, and an error is detected in the circuit 5. When the error occurs, it is corrected in the circuit 5 and correct data is written into the array 3a and is outputted outside. The reliability of EEPROM is improved with constitution in which the error can be corrected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a non-volatile ROM that has an error detection and correction function and can electrically write and erase data.
EP ROM (Electrically Erased
able and programmable RO
1. [Prior art] A conventional EEFROM is shown in FIG. 2. An example of such a circuit is, for example, 88 Mitsubishi Semiconductor Data Book Memory Edition (P.

9-3). In the figure (11 is an address input buffer, (2) is an address decoder, (3a is
) is a memory cell array, (4) is a control circuit, and (6) is a human output buffer for data.

Next, the operation of this circuit will be explained. First, writing data will be explained. An externally applied address signal is applied to an address decoder (2) via an input buffer (1). Address decoder (2) selects a memory cell designated by an address signal.

On the other hand, data is applied to and stored in the memory cell (3a) selected by the address signal through the cover sofa (6). Next, reading data will be explained. The address signal received from the outside is input to the cover sofa (
1) and is added to the 1 theater Tecoder (2).

The address decoder (2) selects the cell specified by the address signal. The data word is output from the selected memory cell and transferred to the traffic buffer (6).
Output to the outside.

[Problem to be solved by the invention]

The conventional EEFROM is configured as described above and is 1i? υ、
When writing data, the data is written to the memory cell specified by the address, and when reading data, the data is simply read from the memory cell specified by the address. Therefore, even if an error occurs in the data, it cannot be detected and the erroneous data must be used as is, reducing reliability.

This release E! Method A was developed to solve the above-mentioned problems, and its purpose is to provide an EEFROM that can detect and correct errors.

Means for Solving the C'R Problem] The EEPROM according to the present invention is provided with a circuit for detecting and correcting errors, and when writing data, a redundant word for error detection is written into the memory cell together with the data.1. When reading data, it is detected whether an error has occurred from the read data and the redundant word, and if an error has occurred, the correct data is not written into the memory.

[Effect]

The EEFROM according to the present invention has a circuit that detects and corrects errors, and if an error occurs in the read data, it corrects the data to be correct and rewrites it to the memory.
The reliability of the EEFROM is increased because it is output to the outside.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory according to an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. 2 indicate the same or equivalent parts, (1) is an address input buffer, (2) is an address decoder, and (3a) is a [P-tower for storing the Memory cell array % (3b) is a memory cell array for storing redundant words, (4)
is a control circuit, (5) is an error detection and correction circuit, and (6) is a data input/output buffer. Next, the operation will be explained with reference to FIG. First, writing data will be explained. An externally applied address signal is applied to an address decoder (2) via an input buffer (11). The address decoder (2) selects the memory cell specified by the address signal. 6) to the memory cell (3a) for storing the data word, and an error detection and correction circuit (3a).
5). The error detection and correction circuit (6) generates redundant words necessary for error detection and correction based on the added data.The input data is stored in the data memory cell array (3a). The redundant words generated by the error detection and correction circuit (5) based on the data are stored in the memory cell array (3b) for redundant words.Next, reading out the data will be explained. The received address signal is applied to the address decoder (2) via the input buffer lt-.The address decoder (2) selects the memory cell specified by the address signal.Data words and redundant data are sent from the selected memory cell. The word is output and applied to the false detection and correction circuit (6).

Erroneous detection and correction path (5) examines the data words and redundant words for errors.

If no error has occurred, the data word is output to the outside. If an error υ occurs, the error detection and correction circuit (6) corrects the error, writes correct data into the memory cell, and outputs it to the outside.

Of course, since it is an EEFROM, even if the power supply to the EEPROM is stopped, the data and redundant words in the EEFROM will not be lost and will remain stored.

〔Effect of the invention〕

As described above, according to the present invention, since a circuit for detecting and correcting errors is provided in the EEPROM, a highly reliable EEPROM that can detect and correct errors even if they occur is provided.
This has the effect of providing ROM.

[Brief explanation of drawings]

FIG. 31 is a block diagram of a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor memory. (1)...Input cover sofa, (2)...Address decoder, (3a)...Memory cell array for data word% (3b)...Memory cell array for redundant word,
(4)...control circuit, (6)...error detection and correction circuit, (6)...input/output buffer. In the figures, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] A semiconductor integrated circuit is equipped with a non-volatile ROM array that can electrically write and erase data, and a circuit that can detect and correct errors. generating a redundancy word and writing data and the redundancy word to the ROM array;
When reading data, data and redundant words are read from the ROM array, errors are detected from the data and redundant words by a circuit capable of detecting and correcting errors, and if an error has occurred, the error is detected and corrected. A semiconductor memory characterized by correcting errors using a circuit capable of correcting errors, rewriting correct data into memory cells, and outputting correct data to the outside.