JPS62211994A - Multilayer circuit board and manufacture of the same - Google Patents
Multilayer circuit board and manufacture of the sameInfo
- Publication number
- JPS62211994A JPS62211994A JP61053729A JP5372986A JPS62211994A JP S62211994 A JPS62211994 A JP S62211994A JP 61053729 A JP61053729 A JP 61053729A JP 5372986 A JP5372986 A JP 5372986A JP S62211994 A JPS62211994 A JP S62211994A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- holes
- circuit board
- copper
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 32
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 11
- 238000007639 printing Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 55
- 238000007747 plating Methods 0.000 description 18
- 238000005476 soldering Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000123 paper Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 206010000059 abdominal discomfort Diseases 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 239000007822 coupling agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- BDHFUVZGWQCTTF-UHFFFAOYSA-M sulfonate Chemical compound [O-]S(=O)=O BDHFUVZGWQCTTF-UHFFFAOYSA-M 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000004065 wastewater treatment Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、基板表面に複数の導電回路層がそれぞれ絶
縁層を介して積層された多層回路基板およびその製造法
に関し、より詳細には部品挿入孔（スルホール部）の周
辺部で各導電回路層を接続させることにより、回路の信
頼性および原価を改善した多層回路基板に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multilayer circuit board in which a plurality of conductive circuit layers are laminated on the surface of the board with an insulating layer interposed therebetween, and a method for manufacturing the same, and more specifically to a method for manufacturing the same. The present invention relates to a multilayer circuit board that improves circuit reliability and cost by connecting conductive circuit layers at the periphery of an insertion hole (through-hole portion).
プリント配線板は、ＩＣ，ｔｓＩなとの半導体素子や電
子部品を搭載したり、また回路システムを構成するため
に用いられている。近年のＯ／ＩＮ器、ＦＡ機器などに
おいて顕著であるように、電子機器の小型化、高性能、
低価格への要請に伴って、このプリント配線板に対する
高密度化、高信頼性、低価格化の要求が強まっている。Printed wiring boards are used to mount semiconductor elements and electronic components such as ICs and TSIs, and to configure circuit systems. As is noticeable in recent O/IN devices, FA equipment, etc., electronic devices are becoming smaller, have higher performance,
With the demand for lower prices, demands for higher density, higher reliability, and lower prices for printed wiring boards are increasing.
このような要請に対して種々の基板が提案・開発されて
いる。Various substrates have been proposed and developed in response to such demands.
例えば、両面銅張積層板を準備し、この両面をエツチン
グしてそれぞれに導電回路（パターン〉を形成し、さら
にスルホール内壁を銅メッキして各回路間を＞う通さけ
る。このような製造方法でｊｑられた多層回路基板１は
、例えば第２図に示すにうに、絶縁基板２両面上にエツ
チングされた銅箔回路３おにび３′が設りられ、両面の
回路間は、スルホール（部品挿入孔）４の、内壁の銅メ
ッキ５にＪ一つて導通され、さらに銅箔回路３おにび３
′は絶縁層６によって被覆されている。For example, a double-sided copper-clad laminate is prepared, both sides are etched to form conductive circuits (patterns) on each, and the inner walls of the through holes are plated with copper to allow passage between each circuit.Such a manufacturing method For example, as shown in FIG. 2, the multilayer circuit board 1 is provided with etched copper foil circuits 3 and 3' on both sides of the insulating board 2, and there are through holes (through holes) between the circuits on both sides. The copper plating 5 on the inner wall of the component insertion hole 4 is electrically connected to the copper foil circuit 3.
' is covered with an insulating layer 6.
しかしながら、この製造法、およびこの方法により１ワ
られたプリント配線板については、パ？−ン形式におい
てレジメ１〜印刷、ハンダ（又は金） 。However, regarding this manufacturing method and printed wiring boards made by this method, is there any performance? -Regime 1 ~ Printing, soldering (or gold) in the form.
メッキ、レジメ１〜剥離、エツチング等の工Ｑ必要とし
、またスルホ、−ルａｔ（のメッキにおいて、活性化無
電解銅メッキおよび電気銅メッキ等を必要どりるにうに
、製造二「程が非常に繁雑であって製造コストが高く、
得られたプリント配線板においてメッキにＪ：る接続で
あるのでその信頼性が低く、さらに、製品ライフ→）−
イクルの短縮ににる繁雑な設置変更に追随しｈ胃こいと
いった問題点がある。Plating, Regime 1 - Processes such as peeling and etching are required, and activated electroless copper plating and electrolytic copper plating are required in the plating of sulfonate and -ru at. It is complicated and the manufacturing cost is high;
In the resulting printed wiring board, the connection is based on the plating, so its reliability is low, and furthermore, the product life is shortened.
There is a problem of stomach upset due to the complicated installation changes required to shorten the cycle time.
上記の基板の欠点、特にロス１〜高を低減するために、
絶縁基板の両面に銅導電ペーストを印刷によって導電回
路に形成し、スルホール部には別に銅導電ペーストをス
ルホール内に流し込みその内、壁に付着硬化させ、次い
でう９電回路の一部または全体を無電解銅メツ：１−ま
たはニッケルメッキし、最後に絶縁層で被覆する方法が
提案されている。In order to reduce the drawbacks of the above substrates, especially the loss 1~high,
Copper conductive paste is printed on both sides of the insulating substrate to form a conductive circuit, and a copper conductive paste is separately poured into the through hole and hardened to adhere to the wall. Electroless copper plating: 1- or nickel plating and finally covering with an insulating layer have been proposed.
このようにして得られ１＝回路基板１は、第３図に示す
ように、絶縁基板２両面上に印刷された導電回路層７お
よび７′が設（プられ、別にスルホール部４には両回路
間の導通用回路８および８′、ならびにメッキ膜９おに
び９′が設けられ、導電回路７および７′は絶縁層で被
覆されている。As shown in FIG. Circuits 8 and 8' for conduction between the circuits and plating films 9 and 9' are provided, and the conductive circuits 7 and 7' are covered with an insulating layer.
、 このよ、うな製・造法、おＪ：びこの方法にＪ：つ
て帽られた基板は、前述した製造法おにびその基板につ
いての問題点を大幅に改善り−るが、スルホール部の導
通化の信頼性に乏しいという問題点がある。Although this method of manufacturing and manufacturing method greatly improves the problems associated with the manufacturing method and the substrate described above, the through-hole portion There is a problem that the reliability of conduction is poor.
上述の両面板とは別に、従来の片面プリント配線板の銅
箔パターン上に絶縁層を施し、その上に銀導電ペースＩ
〜をスクリーン印刷で回路に形成した多層回路基板が提
案されている。この基板にＪニって高密度化を図ること
ができるが、銅箔パターン間を高価な銀ペースで絶縁層
を介して導通させており、・特に導電回路間および実装
部品との間の接続に信頼が乏しいという問題点がある。Apart from the above-mentioned double-sided board, an insulating layer is applied on the copper foil pattern of the conventional single-sided printed wiring board, and a silver conductive paste I is applied on top of the insulating layer.
A multilayer circuit board in which circuits are formed by screen printing has been proposed. Although it is possible to achieve higher density on this board, conduction is established between the copper foil patterns via an insulating layer using expensive silver paste, especially for connections between conductive circuits and mounted components. The problem is that there is a lack of trust.
この発明は上述の事情を背景□にしてなされたものであ
゛す、その目的とするところは高密度、高信頼性および
低コス１〜を備えたプリント配線板を提供すると共に、
製造工程の簡略化された製造法をも提供覆ることである
。This invention was made against the background of the above-mentioned circumstances, and its purpose is to provide a printed wiring board with high density, high reliability, and low cost.
It also provides a manufacturing method that simplifies the manufacturing process.
本発明者らは、高密度化、高信頼性、低コスト化および
工程簡略化のために種々の試作研究の結果、廉価な銅導
電ペーストの印刷による導電回路形成ならびにスルホー
ル周辺部での回路接続がこの目的達成に有効であること
を見出しこの発明を完成するに到った。As a result of various prototyping research aimed at increasing density, high reliability, lowering costs, and simplifying the process, the present inventors have succeeded in forming a conductive circuit by printing an inexpensive copper conductive paste and connecting the circuit around the through-hole. They found that this is effective in achieving this objective and have completed this invention.
すなわち、この発明の多層回路基板は、スルホールを有
する絶縁基板表面に、複数の銅導電回路層がそれぞれ絶
縁層を介して積層された回路基板であって、スルホール
周辺部で銅導電回路層が直接に接続されて各回路間の導
通が行なわれていることを特徴とする一ｂのである。That is, the multilayer circuit board of the present invention is a circuit board in which a plurality of copper conductive circuit layers are laminated on the surface of an insulating substrate having through holes, each with an insulating layer interposed therebetween, and the copper conductive circuit layers are directly stacked around the through holes. 1b, characterized in that the circuits are connected to each other to establish continuity between the respective circuits.
また、この発明の多層回路基板の製造法は、スルホール
を有する絶縁基板表面に、銅導電ペーストを印刷によっ
て少なくともスルホール周辺部が導電域である銅導電回
路層に形成し、次いでスルホール周辺部を除く銅導電回
路層表面を絶縁層で被覆する工程を繰り返すことを特徴
とするものである。Further, the method for manufacturing a multilayer circuit board of the present invention includes printing a copper conductive paste on the surface of an insulating substrate having through holes to form a copper conductive circuit layer in which at least the area around the through hole is a conductive area, and then removing the area around the through hole. This method is characterized by repeating the step of covering the surface of the copper conductive circuit layer with an insulating layer.
発明の詳細な説明 以下この発明を、図面を参照してより詳細に説明する。Detailed description of the invention The present invention will be explained in more detail below with reference to the drawings.
この発明の・製造法において、スルホールを右する絶縁
基板の表面に銅導電ペーストを印刷して導電回路を形成
する。In the manufacturing method of this invention, a conductive circuit is formed by printing a copper conductive paste on the surface of an insulating substrate on the right side of the through holes.
この発明で用いることのできる絶縁基板としては、通常
、プリン１〜配線板として利用されている基板、例えば
、紙、布、ガラスなどの基月にフェノール樹脂、エポキ
シ樹脂などの熱硬化性樹脂を積層した基板などの他に、
アルミナ、窒化ホウ素などの無機絶縁材料を用いた基板
などがある。この絶縁基板には、搭載電子部品の挿入孔
（スルホール）が設けられる。そのスルホールの個数、
寸法、位買などは任意であり、回路設計、搭載部品の種
類に応じて適宜変更することが望ましい。Insulating substrates that can be used in this invention include substrates that are normally used as wiring boards, such as paper, cloth, glass, etc., and thermosetting resins such as phenol resins and epoxy resins. In addition to laminated substrates, etc.
There are substrates using inorganic insulating materials such as alumina and boron nitride. This insulating substrate is provided with insertion holes (through holes) for mounting electronic components. The number of through holes,
The dimensions, dimensions, etc. are arbitrary, and it is desirable to change them as appropriate depending on the circuit design and the type of mounted components.
この発明の製造法において導電回路形成に用いられる銅
導電ペーストは、導電性材料牽ペースト状に調整したも
のである。例えば、本発明者らの提案ように、少量の銀
およびチタネートカップリング剤で被覆された銅粉を主
成分とする銅賞ペースト（特願昭５９−１８６５９５号
、参照）がある。The copper conductive paste used for forming the conductive circuit in the manufacturing method of the present invention is prepared into a conductive paste. For example, as proposed by the present inventors, there is a bronze medal paste (see Japanese Patent Application No. 186,595/1989) which consists mainly of copper powder coated with a small amount of silver and a titanate coupling agent.
通常、回路に印刷された導電ペーストは、大気、不活性
気体また真空などの雰囲気で加熱・硬化されて導電回路
層を形成する。Usually, the conductive paste printed on the circuit is heated and hardened in an atmosphere such as air, an inert gas, or a vacuum to form a conductive circuit layer.
導電ペーストの塗布は、一般にスクリーン印刷法による
が、必要に応じて他の塗布方法を採用することができる
。The conductive paste is generally applied by screen printing, but other application methods can be used as necessary.
この発明における特徴の一つは、電気的接続が必要なス
ルホール周辺部が、印刷による導電回路形成において、
導電域になるにうに導電ペーストで被覆されることであ
る。One of the features of this invention is that the area around the through-hole that requires electrical connection can be formed by printing to form a conductive circuit.
The conductive area is coated with a conductive paste.
導電回路層が形成された後、導電回路層の表面に絶縁材
料が塗布されて絶縁層が形成される。この形成において
、この発明ではスルホール周辺の導電回路層表面に絶縁
材料は塗布されない。この発明において用いることので
きる絶縁材料としては、一般に入手可能な絶縁ペースト
であり、このペーストは塗布後に大気中で加熱して硬化
する。After the conductive circuit layer is formed, an insulating material is applied to the surface of the conductive circuit layer to form an insulating layer. In this formation, no insulating material is applied to the surface of the conductive circuit layer around the through holes in the present invention. The insulating material that can be used in the present invention is a commonly available insulating paste, and this paste is cured by heating in the atmosphere after application.
絶縁層形成後、さらに導電ペーストを印刷して導電回路
層を形成する。この導電ペース１−の印刷・塗布は、前
述と同様にして実施される。この回路層の形成において
、少な（ともスルホール周辺部は導電域になるように導
電ペーストで被覆される。従って、下層の導電回路層と
上層の導電回路層とは、このスルホール周辺部で直接に
接続して電気的に導通ずる。After forming the insulating layer, a conductive paste is further printed to form a conductive circuit layer. Printing and application of this conductive paste 1- is carried out in the same manner as described above. In forming this circuit layer, the area around the through hole is covered with a conductive paste so that it becomes a conductive area. Therefore, the lower conductive circuit layer and the upper conductive circuit layer are directly connected to each other around the through hole. Connect for electrical continuity.
この発明の多層回路基板は、上記した導電回路層形成お
よび次の絶縁層形成の工程を繰り返すことにより製造さ
れる。The multilayer circuit board of the present invention is manufactured by repeating the above-described steps of forming the conductive circuit layer and forming the next insulating layer.
この発明の製造法によって得られた多層回路基板の一例
を第１図に示ザ。この多層回路基板１では、絶縁基板２
の片面上に第１の導電回路層１１、第１の絶縁ｔｊ １
２、第２の導電回路層１３、および第２の絶縁層１４が
順次積層されている。スルホール４の周辺部１５では、
各々の導電回路層の導電域でありかつ絶縁層が形成され
ていないので、各導電回路層が直接に接続している。An example of a multilayer circuit board obtained by the manufacturing method of the present invention is shown in FIG. In this multilayer circuit board 1, an insulating substrate 2
A first conductive circuit layer 11, a first insulating layer tj 1 on one side of
2, a second conductive circuit layer 13, and a second insulating layer 14 are sequentially laminated. In the peripheral part 15 of the through hole 4,
Since this is the conductive region of each conductive circuit layer and no insulating layer is formed, the conductive circuit layers are directly connected.
第１図の例に示すように、所望によって、スルホール周
辺部の露出表面に無電解Ｎｉメッキ、もしくはＣＵメッ
キ等の処理を施してメッキ層１６を形成することもでき
る。導電回路形成に利用した導電ペーストがハンダ付は
可能に配合されたものであれば、メッキ処理を省略する
ことができる。As shown in the example of FIG. 1, if desired, a plating layer 16 can be formed by subjecting the exposed surface around the through hole to electroless Ni plating, CU plating, or the like. If the conductive paste used to form the conductive circuit is formulated to allow soldering, plating can be omitted.
この発明の多層回路基板は、スルホールに部品１７を挿
入して、通常のハンダ付で部品を搭載することができる
。In the multilayer circuit board of the present invention, the components 17 can be inserted into the through holes and mounted using normal soldering.
（発明の効果〕 ） この発明によって次のような効果を得ることかできる。(Effect of the invention〕 ) The following effects can be obtained by this invention.
（ａ） この発明の製造法では、従来の方法で必要で
あったエッチングエ稈を必要としないために、製造工程
を大幅に簡略化でき、コストの低減および製造時間の短
縮をはかることができる。(a) Since the manufacturing method of the present invention does not require the etching process required in conventional methods, the manufacturing process can be greatly simplified, reducing costs and manufacturing time. .
（ｂ） この発明の製造法は主に乾式プロセスである
ので、エツチングのように廃水処理の問題がなく、公害
の必要が少ない。(b) Since the manufacturing method of the present invention is mainly a dry process, there is no problem of wastewater treatment unlike etching, and there is little need for pollution.
（Ｃ） 従来のプリント配線板での接続トラブルがス
ルホール部で多く発生していたが、この発明の多層回路
基板ではスルホール周辺部で導電回路間の導通が図られ
、しかも接続が直接に層間で行なわれるので接続信頼性
を著しく向上させることができる。(C) In conventional printed wiring boards, many connection problems occurred at the through-hole area, but in the multilayer circuit board of the present invention, conduction between conductive circuits is achieved around the through-hole, and the connection is directly between layers. Since this is done, connection reliability can be significantly improved.
（ｄ） 搭載部品のスルホールでのハンダ付（プは、
従来のプリント配線板においてトラブル発生の原因であ
ったが、この発明の多層回路基板では、ハンダ付は加熱
がスルホール周辺部の層間接触を強化して、むしろトラ
ブル発生を防ぐ働きをし、信頼性の高い基板を提供する
ことができる。(d) Soldering through-holes of mounted components (
This was a cause of trouble in conventional printed wiring boards, but in the multilayer circuit board of the present invention, heating during soldering strengthens the interlayer contact around the through-holes, which actually works to prevent trouble and improve reliability. It is possible to provide a high-quality substrate.
（ｅ） 導電回路形成および絶縁層形成の工程を繰り
返すだけで多層化を図ることができるので、設計変更が
容易であり、また高密度化を図ることができる。(e) Multi-layering can be achieved by simply repeating the steps of forming a conductive circuit and forming an insulating layer, so design changes are easy and high density can be achieved.
この発明を、実施例によって具体的に説明する。 This invention will be specifically explained by examples.
実施例１
１＃径のスルホールを有する１＃厚の紙フエノール絶縁
基板（日立化成製、Ｌ Ｐ −４３Ｎ ）の片面に、銅
ペースト（三井金属鉱業製、Ｌ−１０００）をスクリー
ン印刷して回路層を形成した。この形成に際しＣ、スル
ホール周辺部には銅ベーストを塗布し、ランド幅を２
ｍｍ以上とした。Example 1 A circuit was created by screen printing copper paste (L-1000, manufactured by Mitsui Mining and Mining Co., Ltd.) on one side of a 1# thick paper phenol insulating substrate (manufactured by Hitachi Chemical, L P-43N) having through holes of 1# diameter. formed a layer. When forming this, apply copper base to the area around the through hole and make the land width 2.
mm or more.
次いでこの基板をボックスオーブン中で１６０℃２０分
間で加熱し、ペーストを硬化させて厚さ３０μｍの導電
回路層を形成した。This substrate was then heated in a box oven at 160° C. for 20 minutes to harden the paste and form a 30 μm thick conductive circuit layer.
次いで、エポキシ樹脂を主成分とする絶縁ペースト（同
右抵抗〉１０１２Ω・ｃｍ ）を、ランド径５面のスル
ホール周辺部を残して、導電回路層の全面にわたってス
クリーン印刷し、１２０℃１０分間で加熱してペースト
を硬化させ、厚さ３０μｍの絶縁層を形成した。Next, an insulating paste containing epoxy resin as the main component (resistance on the right) 1012 Ω cm was screen printed over the entire surface of the conductive circuit layer, leaving the area around the through-holes on five land diameters, and heated at 120°C for 10 minutes. The paste was cured to form an insulating layer with a thickness of 30 μm.
第２の導電回路層を形成覆るために、銅ペーストを絶縁
層上にスクリーン印刷し、その際、スルホール周辺部に
銅ペーストを２＃以上のランド幅で塗布した。この基板
をボックスオーブン中で１６０℃、２０分間加熱硬化さ
せ、厚さ３０μｍの導電回路層を形成した。In order to form and cover the second conductive circuit layer, a copper paste was screen printed on the insulating layer, and at that time, the copper paste was applied around the through holes with a land width of 2 # or more. This substrate was heated and cured in a box oven at 160° C. for 20 minutes to form a conductive circuit layer with a thickness of 30 μm.
第２の絶縁層は、次いで、第１の絶縁層の形成と同様に
形成した。このようにして１ｒｔられた多層回路基板全
体を、無′ｒｉ解Ｎｉメッキ液〈日本カニゼン製、５Ｓ
−５５）中に浸漬し、６３℃３０分間処理し、５μｍ厚
のＮｉメッキ層を得た。The second insulating layer was then formed similarly to the formation of the first insulating layer. The entire multilayer circuit board thus prepared for the first time was coated with a non-resolving Ni plating solution (manufactured by Nippon Kanigen, 5S).
-55) and treated at 63° C. for 30 minutes to obtain a 5 μm thick Ni plating layer.
製造された多層回路基板にチップ部品を搭載し、噴流ハ
ンダ装置でハンダ付けして使用することができた。Chip components were mounted on the manufactured multilayer circuit board and could be used by soldering with a jet soldering machine.
実施例２
銅ペーストとして下記組成のハンダ付は可能な銅ペース
トを用いたこと以外、実施例１と同様に多層回路基板を
製造した。この基板はＮｉメッキ処理なしに、直接チッ
プ部品をハンダ付けすることができた。Example 2 A multilayer circuit board was manufactured in the same manner as in Example 1, except that a copper paste capable of soldering having the following composition was used as the copper paste. Chip components could be directly soldered to this board without Ni plating.
第１図は、この発明による多層回路基板の一例を示す断
面図、第２図および第３図は、従来技術による基板の例
を示す断面図である。
１・・・多層回路基板、２・・・絶縁基板、３・・・導
電回路層、１・・・スルホール、５・・・メッキ、６・
・・絶縁層、７・・・導電回路層、８・・・導通回路、
９・・・メッキ膜、１１・・・導電回路層、１２・・・
絶縁層、１３・・・導電回路層、１４・・・絶縁層、１
５・・・スルホール周辺部、１６・・・メッキ層、１７
・・・搭載部品。
出願人代理人 佐 藤 −雄
″ 躬
９′
躬
３図FIG. 1 is a sectional view showing an example of a multilayer circuit board according to the present invention, and FIGS. 2 and 3 are sectional views showing examples of boards according to the prior art. DESCRIPTION OF SYMBOLS 1... Multilayer circuit board, 2... Insulating board, 3... Conductive circuit layer, 1... Through hole, 5... Plating, 6...
... Insulating layer, 7... Conductive circuit layer, 8... Continuity circuit,
9... Plated film, 11... Conductive circuit layer, 12...
Insulating layer, 13... Conductive circuit layer, 14... Insulating layer, 1
5... Surrounding area of through hole, 16... Plating layer, 17
...Installed parts. Applicant's agent: Mr. Sato 9' Tsutomu 3 Figure
Claims (1)
回路層がそれぞれ絶縁層を介して積層された回路基板で
あつて、スルホール周辺部で銅導電回路層が直接に接続
されて各回路間の導通が行なわれていることを特徴とす
る多層回路基板。 ２、スルホールを有する絶縁基板表面に、少なくともス
ルホール周辺部を銅導電層が被覆するように、銅導電ペ
ーストを印刷によって銅導電回路層に形成し、次いでス
ルホール周辺部を除く銅導電回路表面を絶縁層で被覆す
る工程を繰り返すことを特徴とする多層回路基板の製造
法。[Claims] 1. A circuit board in which a plurality of copper conductive circuit layers are laminated on the surface of an insulating substrate having through-holes with respective insulating layers interposed therebetween, and the copper conductive circuit layers are directly connected around the through-holes. A multilayer circuit board characterized in that the circuits are connected to each other to provide continuity between each circuit. 2. Form a copper conductive circuit layer by printing a copper conductive paste on the surface of an insulating substrate having through holes so that the copper conductive layer covers at least the area around the through holes, and then insulate the surface of the copper conductive circuit except for the area around the through holes. A method for manufacturing a multilayer circuit board, characterized by repeating the process of coating with layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61053729A JPS62211994A (en) | 1986-03-13 | 1986-03-13 | Multilayer circuit board and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61053729A JPS62211994A (en) | 1986-03-13 | 1986-03-13 | Multilayer circuit board and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62211994A true JPS62211994A (en) | 1987-09-17 |
Family
ID=12950917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61053729A Pending JPS62211994A (en) | 1986-03-13 | 1986-03-13 | Multilayer circuit board and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62211994A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51119973A (en) * | 1975-03-25 | 1976-10-20 | Philips Nv | Screen printing paste and thick film electrically conductive array |
| JPS592198A (en) * | 1982-06-29 | 1984-01-07 | 日本警備保障株式会社 | Security system |
| JPS60180186A (en) * | 1984-02-22 | 1985-09-13 | 松下電器産業株式会社 | Printed board |
| JPS61154197A (en) * | 1984-12-27 | 1986-07-12 | 株式会社東芝 | Thick film multilayer substrate |
-
1986
- 1986-03-13 JP JP61053729A patent/JPS62211994A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51119973A (en) * | 1975-03-25 | 1976-10-20 | Philips Nv | Screen printing paste and thick film electrically conductive array |
| JPS592198A (en) * | 1982-06-29 | 1984-01-07 | 日本警備保障株式会社 | Security system |
| JPS60180186A (en) * | 1984-02-22 | 1985-09-13 | 松下電器産業株式会社 | Printed board |
| JPS61154197A (en) * | 1984-12-27 | 1986-07-12 | 株式会社東芝 | Thick film multilayer substrate |
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