JPS62211574A - Formation of logical verification inspection pattern - Google Patents

Abstract

PURPOSE:To facilitate the logical verification of a circuit including a multibit bus by setting the number of inspection patterns to (n) (n>=5) and extracting and arranging binary numbers which have all transition states of 0 1, 0 1, 1 0, and 1 1 among 2<n> patterns. CONSTITUTION:When binary numbers which increase by '1' as to seven inspec tion patterns t=1-7 of an all-state transition verification pattern 2 and the respective data are checked longitudinally up to t=1-7, it is checked whether or not there are four kinds of state transition (0 0, 0 1, 1 0, and 1 1) includ ed; and data which include the all-state transition are marked with '0' in fields of verification and others are marked with 'X'. For example, data No.7 includes state transition 0 0 at t=1-2, t=2-3, and t=3-4, 0 1 at t=4-5, 1 1 at t=5-6, and 1 0 at t=6-7, thus including all four kinds of state transition. Consequently, the logical verification of the circuit including a multibit bus is easily performed without any omission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of creating a test pattern for easily and completely performing logic verification of a circuit including a multi-bit bus.

[Conventional technology]

Conventionally, in logic verification of circuits including multi-bit buses,
Test patterns as shown in FIGS. 4 and 5 were used.

FIG. 4 is a diagram showing an example of a conventional test pattern for detecting connection errors between arbitrary pits, and FIG. 5 is a diagram showing an example of a conventional test pattern for verifying all state transitions of each bit. Inspection pattern 3 for detecting connection errors between arbitrary bits shown in FIG.
Both of the test patterns 4 for verifying all state transitions of each bit shown in FIG. 5 are for a 32-bit bus.

For example, in order to verify that there are no connection errors (twisted bits) between arbitrary bits of a 32-bit bus, conventionally,
Inspection pattern 3 for finding connection errors between arbitrary bits in Figure 4
As shown in the figure, logic verification is performed by sequentially applying a pattern in which only one of the 32 bits is set to a logical value of ``1'' and all remaining bits are set to ``0'' for a number of patterns equal to the number of bits. was.

On the other hand, a test pattern for a circuit including a memory such as a multi-bit counter requires a pattern that tests all state transitions. All state transitions refer to four state transitions, 0→0, 0→1, 1→0.1→1, when focusing on a certain bit. The minimum pattern including this is, for example, rO−+O
→1→1→0", 5 patterns are required. Therefore,
After verifying that there are no subsequent errors between each bit, the fifth
As shown in test pattern 4 for verifying all state transitions of each bit in the figure, the above five patterns were given to each of the 32 bits.

As described above, in the case of 32 bits, the 32 patterns of the test pattern 3 for detecting connection errors between arbitrary bits shown in FIG. 4 and the test pattern 4 for verifying all state transitions of each bit shown in FIG. Including the 5 patterns, 37 patterns were required.

[Problem to be solved by the invention]

In the conventional logic verification of a circuit including a multi-bit bus as described above, in order to detect connection errors between arbitrary bits and check all state transitions of each bit, it is necessary to at least check the number of bits as described above. +5'' patterns are required, and as the number of bits of the bus increases, the number of patterns increases, resulting in the problem that logic verification takes time.

This invention was made to solve these problems, and is a logic verification test that can easily and quickly detect connection errors between arbitrary bits and check all state transitions of each bit. The goal is to learn how to create patterns.

[Means for solving problems]

In the method for creating a logic verification test pattern according to the present invention, when the number of test patterns is n (however, n≧5), O→O2O→1°1→0, 1→1 is selected from two binary numbers. By extracting and arranging patterns including all state transitions, a test pattern corresponding to a multi-bit bus can be obtained.

[Effect]

In the method for creating a logic verification test pattern of the present invention, the test pattern obtained by this method can be obtained by applying the obtained test pattern to a multi-bit bus in this order, so that any bits can be exchanged. It is possible to detect short circuits or short circuits, and it is also possible to inspect all state transitions.

〔Example〕

FIG. 1 is a diagram showing a test pattern used in a method for creating a logic verification test pattern which is an embodiment of the present invention, and FIGS. 2 and 3 show all states of data for obtaining the test pattern shown in FIG. FIG. 3 is a diagram showing a transition verifiability pattern.

1 shown in FIG.

This represents a test pattern for detecting connection errors between arbitrary bits and verifying all state transitions using 7 test patterns, and 2 shown in FIGS. 2 and 3 represents a pattern for verifying all state transitions using 7 test patterns.

All state transition verifiability pattern 2 using 7 test patterns shown in FIGS. 2 and 3 is - For example, for 7 test patterns that can handle buses up to 54 bits, continuous error detection between arbitrary bits and all state transitions can be verified. This shows a method of creating a test pattern for verification. Figures 2 and 3
All state transition verifiability pattern 2 using the 7 inspection patterns shown in the figure
is ``1'' for 7 inspection patterns from t=1 to 7o.
'' are arranged horizontally as each data (a total of 2'-128 pieces of data), and when each data is viewed vertically from t=i to 7, there are four of the above-mentioned This is a check to see if it includes state transitions (O→0, 0→1, 1→0, 1→1). Mark ○, and mark X for those that do not. For example, data A7 includes state transition O→0 at t=1-2, t=2-3, or t-3-4, and similarly includes state transition O→1 at t-4-5, t- 5 to 6 include state transition 1→1, and t-6 to 7 include state transition 1→0, including all four state transitions. However, data store 6 does not include state transition 1→1. In this way, among the 128 data,
It can be seen that a total of 54 pieces of data include all state transitions.

Test pattern 1 for detecting connection errors between arbitrary bits and verifying all state transitions using the 7 test patterns shown in FIG.
Only the test patterns including all the state transitions in the all-state transition verification pattern 2 using the seven test patterns shown in FIG. 3 and FIG. 3 are extracted. This is the desired test pattern. For example, if seven test patterns are applied to the circuit under verification, a bus of up to 54 bits in total can be tested. here,
Be sure to give t-1 to t-7 to the circuit under verification in this order. In this way, it is possible to discover even if any bit is replaced, and also to check all state transitions.

As mentioned above, the minimum number of patterns that include all state transitions is 5 patterns, but considering the above, 5 patterns means 2'-32 data (all state transitions by 7 test patterns shown in Figure 2). Among the data t-3 to t-7 of verifiability pattern 2 (corresponding to data 41 to 32), only four that include all state transitions are obtained (data 47, 13, 20,
26). Also, in 6 patterns, 2'-62
Of these pieces of data, 18 pieces of data include all state transitions. Therefore, when considering a bass of 8 degrees (32 pitches), 7 or more patterns are required.

In this example, in a bus of less than 54 bits, data is generated from an arbitrary position in the binary notation field of test pattern 1 for connection error detection and all state transition verification of f14 using the 7 test patterns shown in Figure 1. You can take it out. For example, in a 32-bit bus, if bits 48 to 39 are extracted as a test pattern, a test pattern suitable for the purpose can be obtained.

In the above embodiment, a method for creating 7 test patterns that can handle buses up to 54 bits was explained, but if a test pattern for a multi-bit bus is required, the same method can be used for 8 patterns and 9 patterns. By using this method, a desired inspection pattern can be obtained.

〔Effect of the invention〕

As explained above, in the method for creating logic verification test patterns, this invention enables detection of connection errors between arbitrary bits and verification of all state transitions on a multi-bit bus at the same time using only a few patterns. , it is possible to extremely easily create and verify a test pattern for logic verification of a circuit including a multi-bit bus, and it has excellent effects such as being able to reduce the time required.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a test pattern used in a method for creating a logic verification test pattern which is an embodiment of the present invention, and FIGS. 2 and 3 show all states of data for obtaining the test pattern shown in FIG. Diagram showing transition verifiability pattern, fs4
5 is a diagram showing an example of a conventional test pattern for detecting connection errors between arbitrary bits, and FIG. 5 is a diagram showing an example of a conventional test pattern for verifying all state transitions of each bit. In the figure, a test pattern for detecting connection errors between arbitrary bits and verifying all state transitions using 1...7 test patterns,
2... A pattern for verifying all state transitions using 7 test patterns, 3... A test pattern for detecting connection errors between arbitrary bits, and 4... A test pattern for verifying all state transitions of each bit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a method for creating a test pattern for logic verification of a circuit that includes a multi-bit bus and also includes a memory such as a counter, if the number of test patterns is n (however, n≧5), 2^n binary numbers are generated. From 0 → 0, 0 → 1, 1 → 0
A method for creating a logic verification test pattern, characterized in that a test pattern corresponding to a multi-bit bus is obtained by extracting and arranging test patterns including all state transitions from 1 to 1.