JPS62209925A - D/a converter - Google Patents

Abstract

PURPOSE:To raise the resolution and to increase a response speed only by heightening the repeating period of a rectangular wave output by calculating a duty ratio from an input digital value, obtaining the rectangular wave output of the duty ratio, integrating this and obtaining an analog output. CONSTITUTION:A digital value fetched to a register 11 is supplied to a duty modulator 12 and the duty ratio is calculated from the digital value. A signal SC is outputted which comes to be a high level at an on time and a low level at an off time. The signal SC is supplied to a switch circuit 13, porality-inverted by an inverter 14 and supplied to a switch circuit 15. By a resistance 16 and a capacitor 17, the signal SC is integrated and smoothed and removed through an amplifier 18 as the analog output of an output edge 19. When the rectangular wave output from a duty modulator 12 is made into, for example, an on time and two clock period parts and three clock period parts are alternately outputted, the output of the accuracy of a 0.5 clock period can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a D/A converter.

[Conventional technology]

As a p/^ converter for converting a digital output value of a frequency counter or the like into an analog output, there have conventionally been a method using resistors and a pulse averaging method using a so-called rate multiplier.

FIG. 4 is an example of a D/A converter using the pulse averaging method using this rate multiplier.

In the figure, (2) (31 and (4) are rate multipliers, which are connected in series sequentially, and the oscillator (5
) is the constant frequency clock from the multiplier (2)
is supplied to Each rate multiplier (2) +3)
+4) is given input digital data, and this rate multiplier (2) (3) +4) outputs the number of input clocks set by each input data.

Therefore, from the counter (inclination), a number N of pulses is generated according to the set value by the input data.Therefore, if this output pulse is supplied to the integrator (5) and integrated, an analog voltage corresponding to the number N of pulses is generated. is obtained.

At this time, the value Eo of this analog voltage is, for example, a three-digit B
In the case of a CD rate multiplier, [Problem to be solved by the invention] In the case of the above-mentioned rate multi-based D/^ converter, in order to increase the resolution, it is necessary to increase the number of digits of the BCD code, Therefore, the number of counters increases and becomes complicated. Furthermore, the response speed is determined by the output clock frequency from the oscillator (5), but since there is a limit to the clock frequency, there is a drawback that it is difficult to achieve a fast response.

[Means for solving problems]

The invention comprises a means for calculating a duty ratio from input digital data, a means for generating a rectangular wave for switching between a high level period and a low level period of a rectangular wave signal obtained as an output according to the duty ratio, and a means for generating a rectangular wave signal. and means for integrating the signal to obtain an analog output.

[Effect]

The rectangular wave generating means generates a rectangular wave with a duty ratio corresponding to the digital value, and by integrating this rectangular wave, an analog conversion output of the input digital value can be obtained.

〔Example〕

FIG. 1 shows an example of a D/A converter according to the present invention, in which input digital data is taken into a counter register (11). The digital value taken into this register (11) is supplied to the duty modulator (12), and the duty ratio is calculated from this digital value.

In this case, in this duty modulator (12), as shown in Fig. 2, the time corresponding to the maximum value of the human input digital value is determined as the full scale time, and the The on time within the full scale time is determined, and the off time is determined as off time - (full scale time) - (on time).

This full-scale time may be equal to the sampling period of input data, or may be a fixed period of time shorter than the sampling period of human data.

As shown in FIG. 2, this modulator (12) outputs a signal SC that is at a high level during the on-time and at a low level during the off-time.

This signal SC is supplied to a switch circuit (13), has its polarity inverted by an inverter (14), and is supplied to a switch circuit (15). Switch circuit (13)
(15) is turned on when the signal supplied to it is at a high level. Therefore, during the on time of the signal SC, the switch circuit (13) is turned on, and the power supply terminal +Vcc is turned on.
A charging current flows into the capacitor (17) via the resistor (16), and during the off time of the signal SC, the switch circuit (15) is turned on and the capacitor (17) is discharged. That is, the signal SC is integrated by the resistor (16) and the capacitor (17), smoothed, and taken out as an analog output at the output terminal (19) via the amplifier (18).

In this case, the current input data and the previous data are compared in the comparison circuit (20), and if the difference is large, the switch circuit (21) is turned on by the output CO of this comparison circuit (20). , resistor (16) to resistor (22
) are connected in parallel to reduce the charging time constant (integration time constant), so that the response to large changes in input data becomes faster.

Furthermore, when the input data value is small and the duty ratio is small, the full scale time is shortened to increase the repetition frequency of the on time and off time, thereby speeding up the response and reducing ripple.

Note that the counter register (11) and duty modulator (12) can be realized by a microcomputer, and a flowchart 1 in that case is shown in FIG.

In addition, duty strange ma! The rectangular wave output from (12) has an on time and an off time that are integral multiples of the reference clock period, and a rectangular wave output with a precision finer than this clock period cannot be obtained as it is, but for example, the on time is 2 clocks. By alternately outputting the period and 3 clock periods, an output with an accuracy of 0.5 clock period can be obtained. Furthermore, for example, if the on time is set to 2 clock cycles twice and then the output is repeated once for 3 clock cycles, the output with an accuracy of 0.33 clock cycles will be shorter than 1 clock cycle. It is possible to obtain output with arbitrarily fine precision.

〔Effect of the invention〕

As described above, in this invention, the duty ratio is calculated from the input digital value, the rectangular wave output of each duty ratio is obtained, and this is integrated to obtain the analog output. It has the advantage of increasing the resolution and speeding up the response speed simply by reducing the repetition period.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a D/A converter according to the present invention, and FIG. 2 is a diagram for explaining the same. Fig. fj43 is a flowchart of an example of the invention implemented by a microcomputer, and Fig. 4 is a block diagram of an example of a conventional D/^ converter. (12) is a duty modulator that calculates the duty ratio and outputs a rectangular wave output, and (1B) and (17) are integrating resistors and capacitors. %konnogofu's two swords figure 1, power rIL's figure 2

Claims (1)

[Claims] means for calculating a duty ratio from digital data; and a square wave generating means for switching between a high level period and a low level period of an output square wave signal according to the duty ratio;
A D/A converter comprising means for integrating the rectangular wave signal and obtaining an analog output.