JPS62209485A - Character pattern generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a character pattern generation device that stores ten dot patterns of characters expressed in a matrix in a pattern buffer memory and generates a dot pattern of each character. It is related to.

[Conventional technology]

Conventionally, in a character display device that does not have a rotated character pattern as a character pattern, a device has been proposed that is configured to store a character pattern in a pattern buffer or the like and generate a rotated character pattern when reading the character pattern from the pattern buffer. ing.

[Problem that the invention seeks to solve]

However, when storing a character pattern in a pattern buffer memory, there is a problem in that a desired rotated character pattern cannot be obtained unless the previous character pattern is erased. In other words, the dot pattern of a character is composed of bytes in the horizontal direction, but in the vertical direction, it is not structured in bytes due to the reduction in the amount of memory, so it is 90'.
Or, when rotated by 270 degrees, since processing is performed in byte units, the dot pattern written in the previous pattern buffer remains, resulting in problems such as significantly inhibiting the generation of the desired dot pattern. Was.

The present invention has been made to solve the above-mentioned problems, and when storing character patterns in a pattern buffer, the character patterns stored previously in the pattern buffer are not erased.

The present invention relates to a character pattern generating device that can continuously store character patterns.

[Means for solving problems]

The character pattern generating device according to the present invention includes a write control means for serially writing a dot pattern into a pattern buffer memory, a read control means for reading out the dot pattern stored in the pattern buffer memory in parallel, and a read control means for reading out the dot pattern stored in the pattern buffer memory. A masking means for masking required bits of the dot pattern with a mask pattern prepared in advance is provided.

[Effect]

In this invention, when the write control means serially writes the dot pattern into the pattern buffer memory, and when the read control means reads out the dot pattern stored in the pattern buffer memory in parallel, the mask means writes the dot pattern in advance according to the read dot pattern. The required bits of the read dot pattern are masked using the created mask pattern.

〔Example〕

FIG. 1 is a block diagram illustrating the configuration of a character pattern generating device showing an embodiment of the present invention, and 1 is, for example, 12
Character patterns are stored in a pattern buffer memory composed of 8 x 128 x 1 bits. Reference numeral 2 designates a shift register for parallel-in/serial-out, which serves as a write control means of the present invention, and receives an input clock signal PSCLK.
A character pattern input in synchronization with is written into the pattern buffer memory 1. Reference numeral 3 denotes a serial-in/parallel-out shift register serving as a read control means of the present invention, in which the dot pattern stored in the pattern buffer memory 1 is written into the pattern buffer memory 1 in synchronization with the input clock signal 5PCLK. Reference numeral 4 denotes a mask control circuit which also serves as masking means of the present invention, and sets a specific bit pattern for ANDing the dot pattern read from the pattern buffer memory 1 with a specific bit pattern. 5 is an AND gate which performs an AND operation between a specific bit pattern output from the mask control circuit 4 and a dot pattern written in the shift register 3. HAD is an address signal that determines the horizontal address of the pattern buffer memory 1. VAD is an address signal that determines the vertical address of the pattern buffer memory 1.

Next, the character pattern generation operation according to the present invention will be explained with reference to FIGS. 2(a) to 2(e).

FIGS. 2(a) to 2(e) are schematic diagrams illustrating the character pattern generation operation according to the present invention, and in FIG. 2(a),
11 is a dot pattern of the number "7", for example, and is composed of a 7×8 dot matrix. In the same figure (b), 1
2 is a dot pattern, and the state in which the dot pattern 11 is stored in the pattern buffer memory 1 is shown. Same figure (
In C), 13 is a rotated dot pattern, which shows the case where the dot pattern 11 is rotated by 90 degrees. In the figure (d), 14 is a dot pattern, which is generated after developing the dot pattern 11 in the pattern buffer memory 1. In FIG. 15 is a mask pattern, which is a dot pattern 14 generated by the mask control circuit 4.
This is a specific pattern that is ANDed with.

First, the operation of storing the dot pattern 11 shown in FIG. 2(a) into the pattern buffer memory 1 will be explained.

A horizontal address signal HAD of the zero-order pattern buffer memory 1 sets one row of dot patterns of the dot pattern 11 shown in FIG. 2(a) in the shift register 2.
(rlJ') and vertical address signal VAD
Set (ri). In this state, the clock signal P
When SCLK is input, a dot pattern of one column and one row is written into the pattern buffer memory 1. Next, the horizontal address signal HAD is incremented by "1" to "2". When the clock signal PSCLK is input here, a dot pattern of one column and two rows is written into the pattern buffer memory 1. This operation is performed using the vertical address signal VAI.
) until the value of ``7'' becomes the horizontal address signal HA.
When the process is repeated until the value of D reaches "8", the dot pattern 11 shown in FIG. 2(a) is written into the pattern buffer memory 1 as shown in FIG. 2(b). At this time, the dot pattern previously stored in the 8.9th column in the vertical direction remains in the pattern buffer memory 1, as shown in FIG. 2(b).

Next, the operation of generating the dot pattern 13 shown in FIG. 2(C) will be explained. Note that the pattern buffer memory 1 has already stored the dot pattern 12 shown in FIG. 2(b).

Horizontal address signal HA of pattern buffer memory 1
D (“8” in the case of Fig. 2(b)), and set the vertical address signal VAD (“8” in the case of Fig. 2(b)).
”). Here, when the clock signal 5PCLK is input, 8 columns and 8 rows of dots shown in FIG. When the signal 5PCLK is input, the first
The dot pattern in the column is written. However, the first
Previously written dots remain in the eighth row of the column. For this purpose, the mask control circuit 4 generates the mask pattern in the first column of the mask pattern 15 shown in FIG. The first row of dot patterns of the dot pattern 13 shown in FIG. This operation is sequentially performed until the horizontal address signal HAD becomes rlJ, and the mask patterns 15 from the second column to the eighth column shown in FIG. 2(e) generated by the mask control circuit 4 are By performing an AND operation, a dot pattern 13 shown in FIG. 2(e) can be generated. In this embodiment, the case where the dot pattern 11 is rotated by 90 degrees has been described, but the rotation can be similarly performed even if the dot pattern 11 is rotated by 270 degrees.

Further, in the above embodiment, the mask control circuit 4 performs an AND operation on the specific mask pattern 15 with the dot pattern read out from the pattern buffer memory 1, thereby controlling the specific mask pattern 15 as shown in FIG.
Although we have described the case where the dot pattern 13 shown in FIG.
It may be configured such that the CPU (PU) makes the determination, the CPU generates a mask pattern, and ANDs the two.

[Effects of the Invention] As explained above, the present invention includes a write control means for serially writing dot patterns into a pattern buffer memory, a read control means for reading out dot patterns stored in the pattern buffer memory in parallel, and a read control means for reading dot patterns stored in the pattern buffer memory in parallel. Since a masking means is provided for masking the required bits of the dot pattern read by the control means with a mask pattern created in advance, when storing the dot pattern of each character in the pattern buffer memory, the previously stored character pattern can be used. Because it can be stored without erasing it,
For example, it has an excellent advantage of greatly improving the pattern generation processing speed of rotated dot patterns.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the configuration of a character pattern generator showing an embodiment of the present invention, and FIGS. 2(a) to (e)
FIG. 1 is a schematic diagram illustrating a pattern generation operation according to the present invention. In the figure, 1 is a pattern buffer memory, 2.3 is a shift register, 4 is a mask control circuit, and 5 is an AND gate. Procedural amendment (method) August 17, 1981 [

Claims (1)

[Claims] A character pattern generation device that temporarily stores a dot pattern of a character in a pattern buffer memory and generates a dot pattern of each character, comprising a write control means for serially writing the dot pattern in the pattern buffer memory, and the pattern buffer memory. A character pattern characterized by comprising a readout control means for reading out the dot pattern stored in parallel in parallel, and a masking means for masking required bits of the dot pattern read by the readout control means with a mask pattern prepared in advance. Generator.