JPS6220693B2 - - Google Patents

Info

Publication number
JPS6220693B2
JPS6220693B2 JP56023989A JP2398981A JPS6220693B2 JP S6220693 B2 JPS6220693 B2 JP S6220693B2 JP 56023989 A JP56023989 A JP 56023989A JP 2398981 A JP2398981 A JP 2398981A JP S6220693 B2 JPS6220693 B2 JP S6220693B2
Authority
JP
Japan
Prior art keywords
chip
frame
chip mounting
printed circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56023989A
Other languages
English (en)
Other versions
JPS57138149A (en
Inventor
Kozo Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindo Denshi Kogyo KK
Original Assignee
Shindo Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindo Denshi Kogyo KK filed Critical Shindo Denshi Kogyo KK
Priority to JP56023989A priority Critical patent/JPS57138149A/ja
Publication of JPS57138149A publication Critical patent/JPS57138149A/ja
Publication of JPS6220693B2 publication Critical patent/JPS6220693B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 本発明は、長尺のプリント基板にIC等のチツ
プを定間隔に設けて保護層で覆つたチツプ実装方
法に関する。
従来、この種の実装方法は、プラスチツクで成
型した単体の囲い枠を、プリント基板のチツプ取
付部を囲むように接着固定し、そのチツプ取付部
にIC等のチツプを固着後、絶縁性の硬化剤を充
填している。
しかし、チツプ取付部を囲むようにして単体の
囲い枠を１つずつ接着することは、作業上の手間
がかかるばかりでなく、接着位置がずれてチツプ
の取付けに正確さを欠く虞れがあつた。
本発明は、上記欠点を解消して囲い枠を正確に
位置付けしてチツプを正しく固着できるチツプ実
装方法を提供する目的にある。
以下に本発明の実施例を図に基づいて詳述す
る。第１図は、プリント基板の平面図である。長
尺の絶縁基板１上には、チツプ取付部２および複
数の導電リード部３…を、銅箔により繰返し同じ
パターンでプリント配線している。導電リード部
３は、チツプ取付部２の囲りから外方に向けて延
びる細巾の配線部であり、その末端は、他の電子
部品等に接続するための接続端３ａにしてある。
このようなプリント基板４上には、第２図に示す
ように、枠打抜板５を載置する。
第３図は、上記枠打抜板５の平面図である。枠
打抜板５は、略四角形の囲い枠６を、その四隅で
支持腕７……に支持されるように打ち抜いたもの
である。すなわち、囲い枠６の内側は略矩形の抜
き孔８を有しかつその外側は４つの透孔９…を有
しており、このような囲い枠６を一定間隔で複数
設けている。そして、枠打抜板５の板厚は、チツ
プ取付部２に取り付ける後述のチツプより厚く、
プリント基板４の絶縁板１と同じ材質を用いてい
る。
プリント基板４に枠打抜板５を載置するととも
に、囲い枠６のみを接着剤１０で固着する（第２
図参照）。囲い枠６は、枠打抜板５とプリント基
板４との幅員を同じにしておいて両者の側縁を揃
えて重ね合わせると、チツプ取付部２の周囲に配
置されるように枠打抜板５に設けてある。囲い枠
６をプリント基板４に接着後、第４図に示す如
く、４つの支持腕７…をヒートプレスによつて切
断して囲い枠６を残す。切断箇所は、囲い枠６と
支持腕７との付け根が好ましく、囲い枠６が突起
のない四角形になるからである。囲い枠６のプリ
ント基板４に残して他の部分５′を廃棄し、第５
図に示す如く、チツプ取付部２にIC、LSI等のチ
ツプ１１を固着する。チツプ１１は、そのバンプ
１１ａと導電リード部３とをワイヤ１２でボンデ
イングする。その後、囲い枠６内には、エポキシ
樹脂等の絶縁性の硬化剤１３を充填して保護層を
形成する。硬化剤１３は、囲い枠６の上端まで充
填してチツプ１１およびワイヤ１２を覆つて硬化
させる。
また、本発明の他の実施例を以下に説明する。
第６図にあつては、プリント基板１４上に枠打抜
板１５を設置した後、プリント基板１４にチツプ
挿入孔１６を打ち抜いて薄板１７を貼り付けてい
る。すなわち、プリント基板１４は、第１図にお
けるプリント基板４と同様に、絶縁基板上に銅箔
で配線パターンを形成したものである。このよう
なプリント基板１４上には、第３図に示す枠打抜
板５と同様な形状を有す枠打抜板１５を載置して
囲い枠１８のみを接着剤１９で固着する。囲い枠
１８で囲まれたチツプ取付部２０の中央部にチツ
プ挿入孔１６を打ち抜いてプリント基板１４の裏
側（図中下側）に薄板１７を貼り付け、この薄板
１７でチツプ挿入孔１６の開口部を塞いでチツプ
挿入孔１６の底面を形成する。その後、第４図に
示すのと同様に、枠打抜板１５の支持腕を切断し
て囲い枠１８のみを残す（第７図参照）。チツプ
挿入孔１６には、第８図に示す如く、チツプ２１
を挿入して薄板１７に固着する。チツプ２１は、
そのバンプ２１ａにワイヤ２２をボンデイングし
た後、絶縁性の硬化剤２３で覆う。この硬化剤２
３を囲い枠１８の上端まで充填して硬化させる。
このように、プリント基板１４にチツプ挿入孔
１６を設けると、厚みのあるチツプを実装する場
合には全体的に薄くなるので効果が生ずる。
なお、上記実施例において、囲い枠の形状を四
角形にしたが、四角形に限ることなく丸形あるい
は四角形以外の多角形にしてもよく、また、囲い
枠を支持する支持腕は、４つに限られるものでは
ない。支持腕の数は、囲い枠を切離しやすい程度
の数であればよい。
以上説明したように、本発明によれば、チツプ
およびこれにボンデイングするワイヤを保護する
ための硬化剤を有効に充填するための囲い枠は、
複数個が同時にかつ正確に位置決めされて固定さ
れ、チツプの取付位置もずれることなく正規の位
置に固着でき、さらに、手間がかからず作業が迅
速になる利点がある。また、従来の囲い枠のよう
に、成型でなくパンチングでできるので安価にな
る。
【図面の簡単な説明】
第１図は本発明の実施例におけるプリント基板
の平面図、第２図はプリント基板に枠打抜板を載
置した状態の拡大断面図、第３図は枠打抜板の平
面図、第４図は囲い枠のみをプリント基板に固着
した状態の平面図、第５図はチツプを実装した状
態の拡大断面図、第６図は本発明の他の実施例を
示すもので、プリント基板に枠打抜板を載置した
状態の拡大断面図、第７図は囲い枠のみをプリン
ト基板に固着した状態の拡大断面図、第８図はチ
ツプを実装した状態の拡大断面図である。 １……絶縁基板、２，２０……チツプ取付部、
３……導電リード部、４，１４……プリント基
板、５，１５……枠打抜板、６，１８……囲い
枠、７……支持腕、１１，２１……チツプ、１
２，２２……ワイヤ、１３，２３……硬化剤。

Claims (1)

    【特許請求の範囲】
  1. １ チツプ取付部を有する配線パターンを長尺の
    絶縁基板上に繰り返し形成するプリント基板に、
    前記チツプ取付部と対応して抜き孔を繰り返し設
    けてその抜き孔をそれぞれ複数の支持腕で支える
    囲い枠で囲つて形成してなる枠打抜板を、その抜
    き孔を各々前記チツプ取付部と対応する位置に位
    置決めして重ね合わせ、前記囲い枠部分のみを接
    着し、その後前記支持腕を切り離して該囲い枠部
    分を残してその他を除去して後、前記チツプ取付
    部にチツプを取り付けてワイヤボンデイングし、
    そのチツプおよびボンデイングワイヤを被つて前
    記囲い枠内に絶縁性の硬化剤を充填してなる、チ
    ツプ実装方法。
JP56023989A 1981-02-20 1981-02-20 Mounting method for chip Granted JPS57138149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023989A JPS57138149A (en) 1981-02-20 1981-02-20 Mounting method for chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023989A JPS57138149A (en) 1981-02-20 1981-02-20 Mounting method for chip

Publications (2)

Publication Number Publication Date
JPS57138149A JPS57138149A (en) 1982-08-26
JPS6220693B2 true JPS6220693B2 (ja) 1987-05-08

Family

ID=12125982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023989A Granted JPS57138149A (en) 1981-02-20 1981-02-20 Mounting method for chip

Country Status (1)

Country Link
JP (1) JPS57138149A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303587A (ja) * 1989-05-16 1990-12-17 Dainippon Ink & Chem Inc 浄水装置および浄水方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793391B2 (ja) * 1988-09-14 1995-10-09 松下電工株式会社 半導体パッケージの封止枠の装着方法
CN102469693A (zh) * 2010-11-12 2012-05-23 速码波科技股份有限公司 覆晶封装结构及其可携式通信装置与芯片封胶的工艺方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303587A (ja) * 1989-05-16 1990-12-17 Dainippon Ink & Chem Inc 浄水装置および浄水方法

Also Published As

Publication number Publication date
JPS57138149A (en) 1982-08-26

Similar Documents

Publication Publication Date Title
JP2509595B2 (ja) 電子構成要素のパツケ−ジおよびその製造方法
US5018005A (en) Thin, molded, surface mount electronic device
AU671868B2 (en) Electronic module of extra-thin construction
US5717252A (en) Solder-ball connected semiconductor device with a recessed chip mounting area
US6664615B1 (en) Method and apparatus for lead-frame based grid array IC packaging
US5053357A (en) Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon
US20040046256A1 (en) Semiconductor device and method of manufacturing semiconductor device including semiconductor elements mounted on base plate
JP2001326236A (ja) 半導体装置の製造方法
US20020031867A1 (en) Semiconductor device and process of production of same
EP0214621B1 (en) A package comprising a substrate and at least one electronic component
EP0058068A2 (en) Integrated circuit chip carrier
JPS6220693B2 (ja)
JPS60245291A (ja) 半導体装置
US6551855B1 (en) Substrate strip and manufacturing method thereof
JPH0228261B2 (ja)
JPH0517709B2 (ja)
JPH10173085A (ja) 電子モジュール及び電子モジュールの製造方法
JP3511656B2 (ja) リードレスチップキャリアの製造方法
JP2975782B2 (ja) 混成集積回路装置およびこれに用いるケース材
JP2515693Y2 (ja) 半導体モジュール
JPH03160751A (ja) 半導体装置
JPH0530363Y2 (ja)
JPS598067B2 (ja) 半導体装置の製造方法
JPH0543294B2 (ja)
JPH0546276Y2 (ja)