JPS62206854A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a multilayer interconnection having high reliability with excellent controllability by a method wherein pure W is used as the lower layer section of wiring metal film thickness, N2 is mixed with W extending over an upper layer from an intermediate layer, a mixing ratio of which is increased toward the upper layer, and a W group wiring metal, a nitriding ratio of which is altered, is shaped. CONSTITUTION:A first layer wiring metal 21 is formed through a sputtering method. Sputtering is conducted by an Ar atmosphere in a lower layer, and N2 is added gradually extending over intermediate and upper layers and the intermediate and upper layers are shaped. The first layer wiring metal 21 is processed through PIE under specific conditions, using a photo-resist 22 as a mask to form a first layer wiring in a tapered manner. A layer insulating film 23 is deposited, and a through-hole 24 is completed. A second layer metallic film 25 is also shaped and processed similarly, thus completing a two-layer wiring. Three layers or more of multilayer interconnection structure can be formed by employing the same process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor integrated circuit that improves the manufacturing process of metal wiring.

[Technical background of the invention and its problems]

In recent years, as semiconductor integrated circuits have become highly integrated, wiring metals have become finer, and multilayer wiring structures have been used, from two layers to three layers. Etching technology using reactive ion etching (RIE) is being studied for miniaturization of wiring, but when RIB is used, miniaturization is possible due to the anisotropy of the etching. Because it is a vertical process, when a multi-layer structure is used, as shown in Figure 4, it becomes difficult to overcome the gap between the eyebrow insulating film and the upper layer wiring metal (step coverage), resulting in problems such as short-circuits between layers and breaks in the wiring metal, resulting in problems with wiring reliability. Therefore, a taper etching technique with good controllability as shown in FIG. 3 is required.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a taper etching technology for wiring metal that is useful as a wiring technology for high-speed semiconductor integrated circuits, and to enable a highly reliable multilayer wiring structure.

[Summary of the invention]

The present invention is a method for manufacturing a semiconductor integrated circuit using a W-based metal as a wiring metal, in which when forming a W-based wiring metal, the lower layer of the wiring metal film thickness is made of pure W, and from the middle layer to the upper layer, N2 is added to this. By mixing them, the upper layer has a W-based multilayer wiring metal structure with a high mixing ratio.

The formation method is, for example, when forming by sputtering, sputtering is performed in a mixed gas of argon (Ar) and N2 against a W target, but the mixture ratio of N2 is 0% for the lower layer, 10% for the middle layer, and 20% for the upper layer. By increasing the mixing ratio of % and N8 in multiple steps, a W-based wiring metal with a varying nitridation rate is formed.

Alternatively, when chemical vapor deposition (CVO) is used, tungsten hexafluoride (SPS) and ammonia (NH3) are used as reaction gases, but in this case, by increasing the flow rate ratio of N+13. Formable.

For the W-based wiring metal formed in this way, C
When processing is performed by RIE using a mixed gas of F4 and 0□, as shown in Figure 2, the lateral etching speed varies depending on the nitridation rate of the W metal, making it possible to perform taper etching with good control. .

〔Effect of the invention〕

By applying the wiring metal film formation and etching technology according to the present invention to the formation of wiring metal in semiconductor integrated circuits, more reliable multilayer wiring can be formed with good controllability.

[Embodiments of the invention]

FIG. 1 is a diagram showing a specific example of a method for manufacturing a multilayer wiring semiconductor integrated circuit using the wiring metal forming method of the present invention.

First, the first layer wiring metal 21 is formed by sputtering. The lower layer is sputtered in an Ar atmosphere, and the middle and upper layers are sputtered with N.
2 is gradually added (0 to 20%) to form (first
Figure (a)).

Next, using the photoresist 22 as a mask, apply CF, 20cc.
, PI under the conditions of 0.10cc gas pressure 10Pa and 80W
The first layer wiring metal 21 is processed by E to form the first layer wiring into a tapered shape (FIG. 1(b)).

Next, an interlayer insulating film 23 is deposited to form a through hole 24 (FIG. 1(c)).

Further, a second layer metal 1g525 is formed in the same manner as in FIG. 1(a) and processed in the same manner as in FIG. 1(b) to complete the two-layer wiring (FIG. 1(d)).

Furthermore, by using the steps shown in FIGS. 1(c) and 1(d), a multilayer wiring structure of three or more layers is possible.

[Brief explanation of drawings]

Fig. 1 is a process sectional view for explaining one embodiment of the present invention, Fig. 2 is a diagram for explaining the technical contents of the present invention in detail, and Figs. FIG. 21... First M wiring, 22... Photoresist, 23... Interlayer insulating film, 24... Through hole, 25... Second layer wiring, 26... Semiconductor substrate. Agent Patent Attorney Noriyuki Chika Yudo Kikuo Takehana Figure 1

Claims (2)

[Claims] (1) When forming a tungsten (W)-based metal as a wiring metal on a semiconductor substrate, pure W is used in the lower part of the wiring metal film thickness, and nitrogen (N_2) is mixed in W from the middle to upper layers. tungsten nitride (WN), and its N
_2 A method for manufacturing a semiconductor integrated circuit, characterized by forming a W-based wiring metal such that the mixing ratio increases as the upper layer increases, and taper etching the wiring metal using this component ratio. (2) The semiconductor according to claim 1, wherein the taper etching is performed by reactive ion etching (RIE) using a mixed gas of freon (CF_4) and oxygen (O_2). A method of manufacturing integrated circuits.