JPS62205451A - Repeatedly reading memory - Google Patents

Abstract

PURPOSE:To shorten a reading time by holding input data having a reading starting address value and a repeating frequency value and providing a register, etc., to hold the input data to designate the destination address of the read data. CONSTITUTION:Input data INLD has the reading starting address A0 of the upper-most layer of social data and a value (repeating frequency) to show what social data the data are, a reading starting address A1 is outputted to a multiplexer 15 and a repeating frequency 2 is outputted to a comparator 18. When an input request signal IRQ comes to be 0, counting is started by a clock CLK. The second memory 16 reads an output signal IN1 of a register 11, namely, the data processing to the reading starting address in the input data. The comparator 18 compares the output of a counter 9 and a repeating frequency value. Until the output of the comparator comes to be 0, the reading contents of the memory come to be the reading address and the action to read the memory one more time is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to repetitive read memories, and more particularly to memories accessed by dataflow type processors.

[Conventional technology]

Conventionally, in this type of repetitive read memory, when accessing data that is indirectly specified in many layers by an address pointer, software on the processor accesses the memory multiple times and finally stores the required memory. The contents were being read.

[Problem that the invention seeks to solve]

As described above, the conventional method has the drawback that it takes time to read the necessary memory contents.

[Means for solving problems]

The repetitive read memory of the present invention includes a first register for holding input data having a read start address value and a repeat count value, and a second register for holding input data specifying a destination address of the read data. a first memory that is referenced by the output of the second register and stores a new destination address, a counter that counts based on an externally applied clock, and a comparison that compares the repeat count value and the counter output. an AND gate which inputs the output of the comparator and the external clock, a second memory, and a second memory which inputs read data from the second memory and latches the output of the AND gate as latch timing. a multiplexer that selects either the read start address of the input registers or the output of the third register and outputs it as the read address of the second memory; , input control to the second register, input to the counter), permission signal, clear signal control,
It has a control section that controls output to the outside.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows time charts of various parts in this embodiment. In FIG. 1, this embodiment uses external input data INLD and INHD.
ROM 13 connected to the second register 12 and outputting the output data OUT HD 3, and connected to the first register 11 via a multiplexer 15. is,
a second memory 16 that sends output data 0UTLD;
A third register 14 inputs the output data of the second memory 16 and outputs it to the multiplexer 15, an input request signal IRQ, an output end signal 0ACK and a clock C,
A selection signal SEL, a clear signal CLR, and a count enable C input the LK, send the output request signal ORQ and the input completion signal IACK, and control each part.
A control unit 21 that sends out EN and a count enable CE
Antogame I.20 which inputs N and clock CLK,
The output signal of the AND gate 20 is counted, and the output signal C
One counter that sends out 0UNT and inputs a clear signal CLR, a comparator 18 that compares the output signal C0UNT and the output signal INI of the first register 11, and a clock C
LK and the output signal G of the comparator 18 are input thereto and output to the third register 14. In this embodiment, input data INHD and INLD from the outside are first . Second register 12.11 input request signal IRQ
is input to the control unit 21. After performing a predetermined memory read operation, the first memory (ROM) 13 outputs output data 0UTHD, the second memory 16 outputs output data DT, and the control unit 21 outputs an output request signal ORQ.

In this control section 21, when the output end signal 0ACK is input, it is assumed that the memory read operation is completed, and outputs the input completion signal IACK. Input data INHD
, INLD and output data 0tJTHD, 0LJTLD are connected via buses so that they are supplied to separate external modules, and when input data from the previous stage is input, a memory read is performed and output data is output to the subsequent stage. Actions are performed in the form. The data input/output signals for the previous and subsequent stages are an input request signal IRQ, an input completion signal IACK, an output request signal ORQ, and an output end signal 0AC.
This is done using K. The input data INHD and INLD are respectively input to the second register 12. in FIG. It is latched into the first register 11. This latch is performed when the input request signal IRQ from the outside becomes 0' and the clock CLK rises. Input data I NHD is R0M13
is outputted to the outside as output data INHD. Input data I N HD is data for determining what destination address to attach to the read data.
By storing a new destination address in the ROM 13 in advance, the corresponding destination address is read and output data 0UTHD is sent. Input data IN
As shown in FIG. 2, the LD starts reading the top layer of hierarchical data, has an address AO and a value 3 indicating what layer the data is (i.e., the number of repetitions), and the read start address A1 is sent to the multi-brefter 15. The number of iterations 2 is output to the comparator 18. Input request signal IRQ is 0
゛When it becomes empty〉・ri19 count enable CEN
becomes "1", and counting is started by the clock CLK.

In addition, during the time period from when IRQ becomes 0° until the rise of the next clock CLK, the selection signal SEL of the multiplexer 15 becomes 1°, and as a result, in the first diagram, the output signal INI of the first register 11 is selected and the memory address AD is output as

The second memory 16 reads the output signal IN1 of the register 11, that is, the data (DIO> in FIG. 2) corresponding to the read start address (AO in FIG. 2) in the input data. The output of COU N T
and the repetition count value from the - section of the first register 11, and if they do not match, the signal G is set to 1. Signal G is “1”
When the clock CLK rises at '', a latch signal is sent to the register 14, and as a result, the second memory 16
Read data DIO from is latched. At this time, the selection signal LEL is 0', so the multiplexer 15 selects the output signal IN2 of the register 14, and the output of the register 14 is output as the memory read address AD. , the memory 16 reads the contents of DIO and outputs DII.

Furthermore, the value of DII is latched in register 14, and the value of DTI
is output as the memory read address AD. Therefore, the operation of reading the memory again using the read contents of the memory as the read address is repeated until the output G of the comparator reaches 0°. When this operation is repeated for the number of repetition days, the output G of the comparator 18 becomes °O゛, and the latch signal to the register 14 is not inputted to AD,
The value of DT does not change, and when the output request signal ORQ is 1, G
When the clock CLK rises to 0°, the output request signal i is set to 0°. This corresponds to the output request signal to the outside. When the output request signal from the subsequent stage becomes 0°, the rising The ORQ is set to "1" and a clear signal CLR is output to the counter 19 to set the counter value to O. When the counter value reaches O, the signal G becomes “1” again.
It becomes ゛. In addition, the output end signal OACK゛0 from the subsequent stage
The input end signal IAτ ball to the previous stage is set to 0° in accordance with the change in degree. When the input request signal IRQ from the previous stage becomes 1°, the input completion signal IACK is set to 1°.

In this way, the embodiment of the present invention inputs the value read from the memory as the read address of the memory.
Since a loop circuit is provided inside the memory, by repeating this loop the number of times specified from the outside, the value of data that is indirectly specified in many layers can be transferred between the memory and the processor many times. can be read without going back and forth.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for signals to go back and forth between the processor and memory as in the past.
This has the effect of reducing time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing signal timing in one embodiment. 1.2.4...Register, 13...Memory (ROM)
), 15...Multiplexer, 16...Memory, 1
7゜20...antogame-1, 18...comparator, 1
9...Counter, 21...Control unit. Purchasing mother's mouth 0 arts 1. fg

Claims (1)

[Claims] a first register for holding input data having a read start address value and a repetition count value; a second register for holding input data specifying a destination address of the read data; a first memory that is referenced by the output of the register and stores a new destination address; a counter that counts based on an externally applied clock; a comparator that compares the repetition count value with the counter output; an AND gate that receives the output and the external clock as input; a second memory; a third register that inputs read data from the second memory and latches the output of the AND gate as latch timing; a multiplexer that selects one of the read start address of the first register and the output of the third register and outputs it as the read address of the second memory; a control unit that controls input to the counter, a count permission signal to the counter, a clear signal control, and an output control to the outside; reads the contents of the second memory according to a read start address input from the outside; A repeat read memory characterized in that the operation of inputting a value as a read address to the second memory and reading the contents is performed a number of times equal to an externally given repeat count value.