JPS62204535A - Manufacture of semiconductor silicon wafer - Google Patents

Manufacture of semiconductor silicon wafer

Info

Publication number
JPS62204535A
JPS62204535A JP4757186A JP4757186A JPS62204535A JP S62204535 A JPS62204535 A JP S62204535A JP 4757186 A JP4757186 A JP 4757186A JP 4757186 A JP4757186 A JP 4757186A JP S62204535 A JPS62204535 A JP S62204535A
Authority
JP
Japan
Prior art keywords
back surface
silicon
mirror
silicon wafer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4757186A
Other languages
Japanese (ja)
Inventor
Kazutoshi Kamibayashi
和利 上林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4757186A priority Critical patent/JPS62204535A/en
Publication of JPS62204535A publication Critical patent/JPS62204535A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To eliminate the adherence of dust and an exposure gradation by forming a crystal defect on the back surface of a semiconductor silicon wafer, adhering an amorphous silicon on the back surface having the crystal defect, and mirror-polishing the amorphous silicon to eliminate the uneven back surface of the wafer. CONSTITUTION:A semiconductor silicon wafer 1 is back-damaged to roughen the back surface to form an amorphous silicon 3 of 2-15mum. After the silicon 3 is formed, the polysilicon face of the back surface is mirror-polished. To provide similar effect, polycrystalline silicon, Si3N4 film, SiO2 or other conductor, semiconductor, insulator can be irrespectively used, and similar effect can be expected even in the formation of a multilayer of 2 or more layers of the above material by matching to the formation of an element on the front surface. Since the back surface is mirror-polished so that dusts, contaminants are hardly adhered, dusts adhered or generated in the step or manufacturing an LSI can be reduced by 20-90% to contribute to the improvement in the yield of the LSI proceeded in its miniaturization.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体シリコンウェハーの製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor silicon wafers.

〔従来の技術〕[Conventional technology]

従来、半導体シリコンウェハーは裏面にバックダメージ
と称しサンドブラスト等で荒らし、結晶欠陥を発生させ
ていた。この農−1のバックダメージの為に素子を形成
するウェハーの表面へは結晶欠陥は出す、LSIおよび
ICの歩留向上に寄与してきた。
Conventionally, the back surface of semiconductor silicon wafers has been roughened by sandblasting, a process known as back damage, which has caused crystal defects. This back damage causes crystal defects on the surface of wafers on which devices are formed, contributing to improved yields of LSIs and ICs.

一方、最近のLSI関係はパターンの微細化の為、バッ
クダメージによる裏面から鶴発されるゴミ、汚れ、また
目金露光の際裏面のゴミによる露光ボケ等が局部的に発
生し、LSI製造工程において歩留が低下する壁内とな
ってきた。
On the other hand, due to the miniaturization of patterns in recent LSI-related products, dust and dirt are emitted from the backside due to back damage, and exposure blur due to dust on the backside occurs locally during eyelid exposure, resulting in the LSI manufacturing process. It has become an intra-wall area where the yield decreases.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来技術は裏面をパックダメージ形成の為にサ
ンドブラスト等で荒らすのみであった。
The conventional technique described above only roughens the back surface by sandblasting or the like to form pack damage.

その荒れた共面は凹凸がある為に製造工程中でもゴミ・
汚れが付着しやすく、またそのゴミ等がウェハーの取り
扱い・その他の処置で汚れていない他のウェハーの底面
に付層していた。この為、底面の素子形成部にゴミが付
着し、パターン不良もしくはキズ不良となシ歩留の低下
を起こしている。
Because the rough coplanar surface has unevenness, dirt and condensation occur during the manufacturing process.
Dirt easily adhered to the wafer, and the dirt was deposited on the bottom surface of other clean wafers due to wafer handling or other treatments. For this reason, dust adheres to the element forming portion on the bottom surface, causing pattern defects or scratch defects, and a decrease in yield.

更に、ウェハー露光の際裏面にゴミが付着していると、
表面の露光時例えは稲小露光の時ゴミの厚さ分だけ局部
的に焦点が狂いW、元ボケを起こしてしまうなどの問題
を有していた。
Furthermore, if there is dust on the backside during wafer exposure,
For example, when exposing the surface of a rice grain, there is a problem in that the focus is locally deviated by the thickness of the dust, causing an original blur.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の目的は上述の従来技術で製造した半導体ウェハ
ーの裏面の凹凸を無くシ、ゴミの付着および露光ボケを
無くすことである。その為にバックダメージを与えた裏
面に非結晶貴シリコンを形成し、その後鏡面研磨を行い
、ゴミの付着する要因を除くことを特徴とするものであ
る。
An object of the present invention is to eliminate unevenness on the back surface of a semiconductor wafer manufactured by the above-mentioned conventional technique, as well as to eliminate dust adhesion and exposure blur. For this purpose, amorphous noble silicon is formed on the back surface that has been backdamaged, and then mirror polishing is performed to remove the factors that cause dust to adhere.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例で半導体シリコンウェハー1
にバックダメージを与え表面を荒らす、2゜その後2μ
m〜15μmの非結品質シリコン3を形成したものであ
る。
FIG. 1 shows a semiconductor silicon wafer 1 in an embodiment of the present invention.
Causes back damage and roughens the surface, 2° then 2μ
A non-forming quality silicon 3 having a thickness of m to 15 μm is formed.

第2図は非結晶貴シリコン3を形成後、裏面のポリシリ
面を鏡面研磨したものである。
In FIG. 2, after forming amorphous noble silicon 3, the back polysilicon surface is mirror polished.

本実施例ではシリコンウェハーの裏面に非結晶買シリコ
ンを用いたが同様な効果を出す為に多結昂シリコン、i
Mx、N、膜、810.膜その他碑寛体、半纏体、絶縁
体を問わず使用できると共に表面の素子の形成に合わせ
上記材質の2層化以上の多J−形成でも同様効果が期待
できる。
In this example, amorphous silicon was used on the back side of the silicon wafer, but in order to achieve the same effect, multilayer silicon, i
Mx, N, membrane, 810. It can be used regardless of whether it is a film, a flat body, a semi-coated body, or an insulator, and similar effects can be expected by forming two or more layers of the above-mentioned materials in accordance with the formation of surface elements.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は半導体シリコンウェハーの
裏面にバックダメージを与え裏面に結晶欠陥を与え、ト
ランジスタ、ダイオード、等の素子として使用する表面
での結晶欠陥発生を防止しつつ、裏面をゴミ、汚れの付
着しにくい鏡面とする為、LSI製造工程tこ付着もし
くは発生するゴミは20%〜90チ低減でき、微細、化
の進んでいるLSIの歩留向上に寄与できる。
As explained above, the present invention back-damages the back surface of a semiconductor silicon wafer to create crystal defects on the back surface, thereby preventing the occurrence of crystal defects on the surface used as elements such as transistors and diodes, and removing dust and dirt from the back surface. Since the mirror surface is difficult to attract dirt, the amount of dust attached or generated during the LSI manufacturing process can be reduced by 20% to 90%, contributing to an improvement in the yield of LSIs, which are becoming increasingly finer and smaller.

更に微細パターンの為に縮小露光が使われているが、シ
リコンウェノ・−裏面にゴミ等が付着しにくくなる為に
従来のように露光時の焦点ボケを楓少せしめる効果もあ
る。
Furthermore, reduction exposure is used for fine patterns, but since it becomes difficult for dust etc. to adhere to the back surface of the silicon wafer, it also has the effect of reducing the out-of-focus during exposure unlike the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

l・・・・・・シリコンウェハー、2・・・・・・裏面
の荒れ(バックダメージによる)、3・・・・・・非結
晶質シリコン、4・・・・・・非結晶質シリコンの鏡面
、5・・・・・・シリコンウェハー、6・・・・・・裏
面の荒れ(バックダメージによる)。 茅 1 M 茅 211ffi 第 3 図
l...Silicon wafer, 2...Rough back surface (due to back damage), 3...Amorphous silicon, 4...Amorphous silicon Mirror surface, 5...Silicon wafer, 6...Roughness on the back surface (due to back damage). Kaya 1 M Kaya 211ffi Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体シリコンウェハーの裏面に結晶欠陥を形成し、該
結晶欠陥の有する裏面に非結晶質シリコンを付着させ、
該裏面の非結晶質シリコン部を鏡面仕上げにすることを
特徴とする半導体シリコンウェハーの製造方法。
Forming crystal defects on the back surface of a semiconductor silicon wafer and attaching amorphous silicon to the back surface having the crystal defects,
A method for manufacturing a semiconductor silicon wafer, characterized in that the amorphous silicon portion on the back surface is mirror-finished.
JP4757186A 1986-03-04 1986-03-04 Manufacture of semiconductor silicon wafer Pending JPS62204535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4757186A JPS62204535A (en) 1986-03-04 1986-03-04 Manufacture of semiconductor silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4757186A JPS62204535A (en) 1986-03-04 1986-03-04 Manufacture of semiconductor silicon wafer

Publications (1)

Publication Number Publication Date
JPS62204535A true JPS62204535A (en) 1987-09-09

Family

ID=12778922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4757186A Pending JPS62204535A (en) 1986-03-04 1986-03-04 Manufacture of semiconductor silicon wafer

Country Status (1)

Country Link
JP (1) JPS62204535A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0588055A2 (en) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Method for manufacturing wafer
WO2003030251A1 (en) * 2001-09-27 2003-04-10 Shin-Etsu Handotai Co., Ltd. Silicon monocrystal wafer processing device, and method of manufacturing silicon monocrystal wafer and silicon epitaxial wafer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0588055A2 (en) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Method for manufacturing wafer
EP0588055A3 (en) * 1992-09-18 1994-08-10 Mitsubishi Materials Corp Method for manufacturing wafer
US5429711A (en) * 1992-09-18 1995-07-04 Mitsubishi Materials Corporation Method for manufacturing wafer
KR100299008B1 (en) * 1992-09-18 2001-11-30 후지무라 마사지카, 아키모토 유미 Wafer Manufacturing Method
WO2003030251A1 (en) * 2001-09-27 2003-04-10 Shin-Etsu Handotai Co., Ltd. Silicon monocrystal wafer processing device, and method of manufacturing silicon monocrystal wafer and silicon epitaxial wafer
US7214271B2 (en) 2001-09-27 2007-05-08 Shin-Etsu Handotai Co., Ltd. Silicon single crystal wafer process apparatus, silicon single crystal wafer, and manufacturing method of silicon epitaxial wafer

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