JPH0383320A - Bonded semiconductor substrate - Google Patents

Bonded semiconductor substrate

Info

Publication number
JPH0383320A
JPH0383320A JP22067289A JP22067289A JPH0383320A JP H0383320 A JPH0383320 A JP H0383320A JP 22067289 A JP22067289 A JP 22067289A JP 22067289 A JP22067289 A JP 22067289A JP H0383320 A JPH0383320 A JP H0383320A
Authority
JP
Japan
Prior art keywords
wafer
substrate
semiconductor substrate
bonded
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22067289A
Other languages
Japanese (ja)
Other versions
JP2862582B2 (en
Inventor
Kazuyoshi Furukawa
和由 古川
Katsujiro Tanzawa
丹沢 勝二郎
Kiyoshi Fukuda
潔 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22067289A priority Critical patent/JP2862582B2/en
Publication of JPH0383320A publication Critical patent/JPH0383320A/en
Application granted granted Critical
Publication of JP2862582B2 publication Critical patent/JP2862582B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To remove a part which is liable to break without decreasing the diameter of a substrate and to increase an element forming area by obliquely cutting the peripheral part of the substrate. CONSTITUTION:A first wafer 21 and a second wafer 22 are cleaned and then dried with a spinner. Both mirror surfaces are brought into contact tightly in a clean atmosphere. Then, heat treatment is performed in an nitrogen atmosphere containing a small amount of oxygen at 1,100 deg.C for one hour. Both wafers are directly bonded in this way. Then, a part shown by hatching in the figure at the outside of a straight line A is removed by grinding. The straight line A connects a point 28 on the peripheral surface of the second wafer 21 and a point 29 on the bonding surfaces of both wafers 21 and 22. Since the part which is liable to break in the second wafer 22 (element forming wafer) is removed in this way, the possible breakdown at this part does not give adverse effects on the succeeding process.

Description

【発明の詳細な説明】 [発明の目的〕 (産業上の利用分野) 本発明は、2枚の半導体基板を接着若しくは接合して一
体化した接着半導体基板に係わり、特に外周部を一部切
欠した接着半導体基板に関する。
[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a bonded semiconductor substrate in which two semiconductor substrates are bonded or joined to form an integrated structure, and in particular, the present invention relates to a bonded semiconductor substrate in which two semiconductor substrates are bonded or bonded to form an integrated structure, and in particular, the outer periphery thereof is partially cut out. The present invention relates to an adhesive semiconductor substrate.

(従来の技術) 近年、鏡面に研磨されたシリコン等の半導体基板(ウェ
ハ)に前処理を施した後、2枚のウェハの鏡面同士を接
触させ熱処理することにより、強固な接合体ウェハを形
成する技術が注目されている。この技術は、直接接着若
しくは直接接合と呼ばれている。直接接着された接着半
導体基板は接着剤を使用していないので、熱的にも化学
的にも安定であり、エピタキシャル成長、拡散の代替や
誘電体分離基板の製造等に用いられ、各種半導体素子に
利用されている。
(Prior art) In recent years, after performing pretreatment on mirror-polished semiconductor substrates (wafers) such as silicon, the mirror surfaces of the two wafers are brought into contact and heat-treated to form a strong bonded wafer. The technology to do this is attracting attention. This technique is called direct bonding or direct bonding. Since directly bonded semiconductor substrates do not use adhesives, they are thermally and chemically stable, and are used for epitaxial growth, as an alternative to diffusion, and in the production of dielectrically isolated substrates, making them suitable for various semiconductor devices. It's being used.

エピタキシャル成長や拡散の代替の場合は、例えば高濃
度のpタイプウェハと低濃度のnタイプウェハを接着す
る。誘電体分離基板の場合には、表面を酸化したウェハ
を接着する。いずれの場合も、素子が製造される方のウ
ェハの厚さは一般にLOJm以下である。これに対して
接着に使われるウェハは数100μ麿の厚さを持ってい
る。従って、接着後に一方のウェノ\を研磨等で厚さを
減らす必要がある。
As an alternative to epitaxial growth or diffusion, for example, a highly doped p-type wafer and a lightly doped n-type wafer are bonded together. In the case of a dielectric isolation substrate, a wafer with an oxidized surface is bonded. In either case, the thickness of the wafer on which the devices are fabricated is generally less than or equal to the LOJm. On the other hand, the wafer used for bonding has a thickness of several hundred micrometers. Therefore, after bonding, it is necessary to reduce the thickness of one of the weno sheets by polishing or the like.

ところで、第3図(a)に断面を示したように、ウェハ
31はその縁にラウンド加工と呼ばれる面取りがなされ
ている。ラウンド加工は、ウェハを鏡面に加工する際や
、ウェハに素子を製造する工程中に、ウェハの縁に欠は
等が発生しないようにするためになされる。このように
ラウンド加工が施されているウェハ同士を接着すると、
第3図(b)に示すようにウェハ31,32の縁の部分
33は接着しない。
By the way, as shown in the cross section of FIG. 3(a), the edge of the wafer 31 is chamfered, which is called round processing. The rounding process is performed to prevent chips from occurring at the edges of the wafer when processing the wafer into a mirror surface or during the process of manufacturing elements on the wafer. When wafers that have been rounded in this way are bonded together,
As shown in FIG. 3(b), the edge portions 33 of the wafers 31 and 32 are not bonded.

このような接着半導体基板に対し、第3図(C)に示す
ように一方のウェハ31を研磨すると、ウェハ31の周
辺部に本来の厚さ(中央部の厚さ)よりも極めて薄い部
分34が形成される。この薄い部分34は研磨中や後の
素子製造工程中に壊れ易い。ウェハの一部が壊れると破
片が異物となり素子の歩留りを低下させるだけでなく、
ウェハ自体や製造装置の破壊の原因にもなる。これを防
ぐために従来は、第3図(d)のように縁の部分を切り
落とし、未接着部分33を無くしてから研磨や新たなラ
ウンド加工を行っていた。
When one wafer 31 of such a bonded semiconductor substrate is polished as shown in FIG. is formed. This thin portion 34 is easily broken during polishing and subsequent device manufacturing steps. If a part of the wafer breaks, the debris becomes foreign matter and not only reduces the yield of devices, but also
It can also cause destruction of the wafer itself or manufacturing equipment. In order to prevent this, conventionally, as shown in FIG. 3(d), the edge portion was cut off to eliminate the unbonded portion 33 before polishing or new round processing was performed.

一般に接着しない部分33は縁から数i程度である。こ
れに対してウェハの大きさの規格は、100gg、12
5av、1501I1m等の25amおきである。規格
以外の大きさのウェハは人手が困難であり、また素子製
造工程中に使用されるプロセス装置で取り扱うことがで
きない。従って、接着後に縁を落とす際には、直径を2
5m5小さくする必要がある。ウェハの直径を25■も
小さくすることは、素子形成面積の低減につながり、1
枚のウェハに製造することのできる素子数が減ることに
なる。
Generally, the portion 33 that is not bonded is about several i from the edge. On the other hand, the wafer size standards are 100gg, 12
5av, 1501I1m, etc. every 25am. Wafers with a size other than the standard are difficult to handle manually and cannot be handled by process equipment used during the device manufacturing process. Therefore, when cutting the edges after gluing, reduce the diameter by 2
It is necessary to reduce the size by 5m5. Reducing the diameter of the wafer by 25 cm leads to a reduction in the area for forming elements, and
The number of devices that can be manufactured on a single wafer will be reduced.

(発明が解決しようとする課題) このように従来、2枚の半導体基板の接着後、基板直径
を1回り小さくすることは、基板周辺の加工が必要とな
るばかりでなく、素子形成面積の縮小につながり、1枚
の基板に製造することのできる素子数が少なくなる。
(Problem to be solved by the invention) Conventionally, reducing the substrate diameter by one size after bonding two semiconductor substrates not only requires processing around the substrates, but also reduces the element formation area. This leads to a decrease in the number of elements that can be manufactured on one substrate.

本発明は、上記事情を考慮してなされたもので、その目
的とするところは、基板直径を減らすことなく壊れ易い
部分を取り除くことができ、素子形成面積の増大をはか
り得る接着半導体基板を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to provide a bonded semiconductor substrate in which fragile parts can be removed without reducing the substrate diameter and the area for forming elements can be increased. It's about doing.

[発明の構成コ (課題を解決するための手段) 本発明の骨子は、基板直径を減らすことなく壊れやすい
部分(周辺部の厚さの薄い部分)を取り除くために、基
板周辺部を斜めにカットすることにある。
[Structure of the Invention (Means for Solving the Problems)] The gist of the present invention is to diagonally form the periphery of a substrate in order to remove a fragile portion (a thin portion at the periphery) without reducing the substrate diameter. It's about cutting.

即ち本発明は、第1の半導体基板上に第2の半導体基板
を接着一体化し、且つ第2の半導体基板の表面側を研磨
等で薄膜化した接着半導体基板において、第1及び第2
の半導体基板の周辺部を、各基板の中心を通り各基板と
垂直な断面において、第1の半導体基板の最外周部より
も内側で且つ第2の半導体基板側の周辺部に接する点と
、第1及び第2の半導体基板との接着部最外周よりも内
側の点とを結ぶ線で切って除去するようにしたものであ
る。
That is, the present invention provides a bonded semiconductor substrate in which a second semiconductor substrate is bonded and integrated onto a first semiconductor substrate, and the surface side of the second semiconductor substrate is made thin by polishing or the like.
A point that is inside the outermost peripheral part of the first semiconductor substrate and in contact with the peripheral part on the second semiconductor substrate side in a cross section passing through the center of each substrate and perpendicular to each substrate; The adhesive portion is removed by cutting along a line connecting a point inside the outermost periphery of the bonded portion with the first and second semiconductor substrates.

本発明の概要を、第1図を参照して説明する。An overview of the present invention will be explained with reference to FIG.

第1図は、第1の半導体基板11と第2の半導体基板1
2とを接着した接合体の断面を示している。m1図(a
)で両基板11.12は中心から16の点まで接着され
ている。第2の半導体基板12は接着後に研磨して破線
17で表わされた厚さまで薄くされる。本発明の特徴は
、第1の半導体基板11と第2の半導体基板12が接着
一体化された接着半導体基板であって、第1の基板11
の最も直径が大きい部分15が残されており、第1及び
第2の基板11.12が接着されている部分よりも外側
の少なくとも第2の基板12の部分が除去されているこ
とである。即ち、第1図(b)に示すような断面となっ
ていればよい。
FIG. 1 shows a first semiconductor substrate 11 and a second semiconductor substrate 1.
2 is a cross-sectional view of a joined body in which the two are bonded together. m1 diagram (a
), both substrates 11 and 12 are bonded to points 16 from the center. After bonding, the second semiconductor substrate 12 is polished and thinned to a thickness represented by a broken line 17. A feature of the present invention is a bonded semiconductor substrate in which a first semiconductor substrate 11 and a second semiconductor substrate 12 are bonded and integrated;
At least the portion of the second substrate 12 outside the portion where the first and second substrates 11.12 are bonded has been removed, with the largest diameter portion 15 remaining. That is, it is sufficient if the cross section is as shown in FIG. 1(b).

より望ましい本発明の接着半導体基板を第1図(c)を
用いて説明する。第1図(c)は第2の半導体基板12
が薄くされた後の断面を示す。
A more desirable adhesive semiconductor substrate of the present invention will be explained with reference to FIG. 1(c). FIG. 1(c) shows the second semiconductor substrate 12.
shows the cross section after it has been thinned.

第1図(c)中で、第1の点18と第2の点19と第3
の点20を結ぶ線Aの外側の、ハツチングで示された部
分が除去されていることであるここで、第1の点18は
第1の半導体基板11の最外周部15、若しくはこれよ
りも接着面に近い点である。また、第2の点19は、接
着界面上の内基板が接着している最も外側の部分16、
若しくはこれよりも内側の点である。線Aは直線若しく
は第2の基板側に凸(外側に凸となっていることが望ま
しい。第3の点20は線Aと第2の半導体基板12の表
面17との交点である。第3の点20は、第1の半導体
基板11の最外周部15より内側に12.5ms未満の
位置にあることが望ましい。
In FIG. 1(c), the first point 18, the second point 19 and the third point
Here, the first point 18 is located at the outermost peripheral portion 15 of the first semiconductor substrate 11 or more than this. This is a point close to the adhesive surface. The second point 19 is the outermost portion 16 to which the inner substrate is bonded on the adhesive interface;
Or a point inside this point. The line A is a straight line or is convex toward the second substrate (preferably outwardly convex. The third point 20 is the intersection of the line A and the surface 17 of the second semiconductor substrate 12. It is desirable that the point 20 be located at a position less than 12.5 ms inside the outermost peripheral portion 15 of the first semiconductor substrate 11 .

(作用) 本発明によれば、接着し周辺を加工した後でも第1の半
導体基板の最外周部が残されているので、全体としての
基板直径が減ることはない。
(Function) According to the present invention, even after bonding and processing the periphery, the outermost periphery of the first semiconductor substrate remains, so the overall substrate diameter does not decrease.

また、第2の半導体基板の薄く割れ易い部分が除去され
ているので、この部分の破壊が後のプロセスに悪影響を
与えることはない。
Further, since the thin and easily breakable portion of the second semiconductor substrate has been removed, destruction of this portion will not adversely affect subsequent processes.

接着し薄膜化した第2の半導体基板に半導体素子を製造
する際には、PEP工程で基板表面にレジストが塗られ
る。この際、基板周辺部の形状によってはこの部分でレ
ジストが段切れを起こし剥離が生じることがある。接着
して薄膜化した基板の周辺部の断面形状が第1図(c)
で表わされた断面形状であればレジストの剥離が起こり
難い。即ち、基板表面側の周辺部の断面形状を表わす線
Aが第2の基板側に凹(外側に凹)でなければ、この部
分でのレジストの段切れや剥離が起こり難い。また、線
Aと接着基板の表面17とが20の点でなす角度が大き
くなるので、やはりこの部分でのレジストの段切れや剥
離が起こり難い。具体的には、線Aは直線。
When manufacturing a semiconductor element on a second semiconductor substrate that has been bonded and thinned, a resist is applied to the surface of the substrate in a PEP process. At this time, depending on the shape of the peripheral area of the substrate, the resist may break off in this area and peeling may occur. Figure 1(c) shows the cross-sectional shape of the peripheral part of the substrate that has been bonded and thinned.
With the cross-sectional shape represented by , peeling of the resist is unlikely to occur. That is, unless the line A representing the cross-sectional shape of the peripheral portion on the front surface side of the substrate is concave toward the second substrate (concave outward), breakage or peeling of the resist at this portion is unlikely to occur. Furthermore, since the angle formed by the line A and the surface 17 of the adhesive substrate at the point 20 is large, breakage or peeling of the resist at this portion is less likely to occur. Specifically, line A is a straight line.

複数の直線の組み合わせ1曲線、若しくは曲線と直線の
組み合わせが考えられる。
A combination of a plurality of straight lines, a single curve, or a combination of a curve and a straight line can be considered.

一方、第3の点20は基板表面17と線Aの断面であり
、この内側の基板表面に素子が作られる。この点が接着
した基板の外周部、即ち第1の基板の最外周部よりも1
2.5ms以上基板中心側になると、従来行われていた
基板直径25層厘減らす方法に比べて、本発明の効果を
発揮することができない。
On the other hand, the third point 20 is a cross section between the substrate surface 17 and the line A, and an element is formed on the inner substrate surface. This point is 1 point lower than the outer periphery of the bonded substrate, that is, the outermost periphery of the first substrate.
When the distance is 2.5 ms or more toward the center of the substrate, the effect of the present invention cannot be exhibited compared to the conventional method of reducing the substrate diameter by 25 layers.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第2図は本発明の一実施例に係わる接着半導体基板の製
造工程を示す断面図である。
FIG. 2 is a sectional view showing the manufacturing process of a bonded semiconductor substrate according to an embodiment of the present invention.

まず、鏡面に研磨された2種類のシリコン基板(ウェハ
)を用意する。第1のウェハは比抵抗が0.O1ΩcI
lでpタイプ、第2のウェハは比抵抗が80Ωelでn
タイプ、ウェハの形状は両者とも同じで、直径150m
m 、厚さ80hi 、縁には半径30011■のラウ
ンド加工が施されている。
First, two types of mirror-polished silicon substrates (wafers) are prepared. The first wafer has a resistivity of 0. O1ΩcI
The second wafer has a resistivity of 80Ωel and is n type.
Both types and wafer shapes are the same, with a diameter of 150 m.
m, thickness 80hi, and the edges are rounded with a radius of 30011cm.

まず、両ウェハを洗浄処理した。洗浄は両ウェハとも硫
酸と過酸化水素の混合液処理、塩酸と過酸化水素水の混
合液処理、希弗酸処理、水洗処理である。洗浄後、両ウ
ェハをスピナーで乾燥し、鏡面同士を清浄な雰囲気下で
接触させ密着させた。次いで、熱処理を1100℃で1
時間、少量の酸素を含む窒素雰囲気中で行い、両ウェハ
を直接接着した。接着したウェハの縁の部分の断面を第
2図(a)に示す。ラウンド加工は半径300t■であ
るが、実際には鏡面研−磨の際に発生する面だれのため
に、両ウェハ21.22は縁(ijk外周部)から2〜
31111%図中26の点までの部分が接着していなか
った。
First, both wafers were cleaned. Both wafers were cleaned using a mixture of sulfuric acid and hydrogen peroxide, a mixture of hydrochloric acid and hydrogen peroxide, dilute hydrofluoric acid, and water washing. After cleaning, both wafers were dried using a spinner, and the mirror surfaces were brought into contact with each other in a clean atmosphere to make them adhere closely. Then, heat treatment was performed at 1100°C for 1
The bonding process was carried out in a nitrogen atmosphere containing a small amount of oxygen for a period of time, and both wafers were directly bonded. A cross section of the edge of the bonded wafer is shown in FIG. 2(a). The round processing has a radius of 300t■, but in reality, due to the surface sagging that occurs during mirror polishing, both wafers 21 and 22 are 2 to
31111% The area up to point 26 in the figure was not bonded.

次いで、第2図(b)に示すような周辺加工を行い、主
に第2のウェハ22の縁の部分を斜めに削除した。即ち
、第1のウェハ21の周辺表面上の点28と両ウェハ2
1,22の接着面上の点2つを結ぶ直線Aの外側の、図
中ハツチングで表わした部分を研削により取り除いた。
Next, peripheral processing as shown in FIG. 2(b) was performed, and mainly the edge portion of the second wafer 22 was obliquely removed. That is, a point 28 on the peripheral surface of the first wafer 21 and both wafers 2
The portion outside the straight line A connecting the two points on the adhesive surfaces of Nos. 1 and 22, indicated by hatching in the figure, was removed by grinding.

ここで、点28は第1のウェハ21の下から450μm
のところ(最外周部25よりも上側、即ち内側)に、点
29は第1のウェハ21と第2のウェハ22の接着面上
で、ウェハ最外周部25から内側に511の位置になる
ように設定した。
Here, the point 28 is 450 μm from the bottom of the first wafer 21.
(above the outermost periphery 25, that is, on the inside), the point 29 is located at a position 511 inward from the wafer outermost periphery 25 on the adhesive surface of the first wafer 21 and the second wafer 22. It was set to

また、点28の部分は、図示していないが面取り加工を
行って角を取った。
Further, although not shown in the drawings, the portion at point 28 was chamfered to have a corner.

周辺加工の後、第3図(e)のように第2のウェハ22
を50μmの厚さまで研磨して薄膜化した。研磨後の基
板表面27の端30は、研磨による面だれがあり、ウェ
ハの最外周部25から8■程度内側になった。この基板
に半導体素子を製造したところ、製造工程中にウニl\
の破損や、レジストの段切れ、剥離が生じることはなか
った。
After peripheral processing, the second wafer 22 is removed as shown in FIG. 3(e).
was polished to a thickness of 50 μm to form a thin film. The edge 30 of the substrate surface 27 after polishing had surface sag due to polishing, and was approximately 8 cm inward from the outermost peripheral portion 25 of the wafer. When semiconductor devices were manufactured on this substrate, sea urchins were removed during the manufacturing process.
No breakage, breakage, or peeling of the resist occurred.

かくして本実施例によれば、2枚のウェハ21.22を
接着一体化した接着半導体基板の周辺部を斜めにカット
して第2のウェハ22(素子形成用ウェハ)の壊れ易い
部分(厚さの薄い部分)を除去しているので、この部分
の破壊が後のプロセスに悪影響を与えることがない。
Thus, according to this embodiment, the periphery of the bonded semiconductor substrate in which two wafers 21 and 22 are bonded and integrated is cut diagonally to remove the fragile portion (thickness) of the second wafer 22 (device forming wafer). Since the thin part of the wafer is removed, destruction of this part will not adversely affect subsequent processes.

そしてこの場合、第1のウェハ21の最外周部が残され
ているので、基板の直径が減ることはなく、規格通りの
半導体基板として使用することができる。また、基板直
径を25mmも小さくする従来方法とは異なり、第2の
ウェハ22の直径減少は僅かであるため、従来方法に比
して素子形成面積の増大をはかることができる。これは
、基板の有効利用につながり、結果として製品コストの
低減をはかることができる。また、第2図(b)からも
判るように、基板周辺部の斜めカットは通常の研磨工程
により簡易に実施することができる。
In this case, since the outermost portion of the first wafer 21 remains, the diameter of the substrate does not decrease and can be used as a standard semiconductor substrate. Further, unlike the conventional method in which the substrate diameter is reduced by 25 mm, the diameter of the second wafer 22 is only slightly reduced, so the area for forming elements can be increased compared to the conventional method. This leads to effective use of the substrate, and as a result, it is possible to reduce product costs. Further, as can be seen from FIG. 2(b), diagonal cutting around the substrate periphery can be easily performed by a normal polishing process.

なお、本発明は上述した実施例に限定されるものではな
い。実施例では、直接接着若しくは直接接合と呼ばれる
方法により接着した基板について説明したが、本発明は
他の方法、例えば静電接着、接着剤、樹脂、金属等によ
る接着等で2枚の基板を張り合わせた基板についても同
様に適用することができる。また、2枚の基板間に酸化
膜その他の膜を介在させて一体化した基板にも適用でき
る。また、第1の基板は素子形成に供されるものではな
く、支持体として使用されるので、必ずしも半導体に限
るものではなく絶縁板或いは金属板を用いることも可能
である。その他、本発明の要旨を逸脱しない範囲で、種
々変形して実施することができる。
Note that the present invention is not limited to the embodiments described above. In the embodiments, substrates bonded by a method called direct adhesion or direct bonding have been described, but the present invention is also applicable to bonding two substrates by other methods such as electrostatic adhesion, bonding with adhesives, resins, metals, etc. The same can be applied to other substrates. Furthermore, the invention can also be applied to two substrates that are integrated by interposing an oxide film or other film between them. Further, since the first substrate is not used for forming elements but is used as a support, it is not necessarily limited to a semiconductor, and an insulating plate or a metal plate can also be used. In addition, various modifications can be made without departing from the gist of the present invention.

[発明の効果] 以上詳述したように本発明によれば、基板の壊れやすい
部分(周辺部の厚さの薄い部分)を取り除くために、基
板周辺部を斜めにカットしているので、基板直径を減ら
すことなく壊れ易い部分を取り除くことができ、素子形
成面積の増大をはかり得る接着半導体基板を実現するこ
とができる。
[Effects of the Invention] As detailed above, according to the present invention, the periphery of the substrate is cut diagonally in order to remove the fragile portion (thin peripheral portion) of the substrate. A bonded semiconductor substrate can be realized in which fragile parts can be removed without reducing the diameter, and the area for forming elements can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の詳細な説明するための断面図、第2図
は本発明の一実施例に係わる接着半導体基板の製造工程
を示す断面図、第3図は従来の問題点を説明するための
断面図である。 11.21・・・第1の半導体基板、 12.22・・・第2の半導体基板、 15.25・・・最外周部、 16.26・・・接着部最外周、 17.27・・・研磨表面、 18.28・・・第1の点 (最外周部よりも内側の点)、 1 つ。 29・・・第2の点 (接着部最外周より も内側の点) 20゜ 0・・・第3の点 (線Aと基板表面との交点)
Fig. 1 is a cross-sectional view for explaining the present invention in detail, Fig. 2 is a cross-sectional view showing the manufacturing process of a bonded semiconductor substrate according to an embodiment of the present invention, and Fig. 3 is a cross-sectional view for explaining conventional problems. FIG. 11.21...First semiconductor substrate, 12.22...Second semiconductor substrate, 15.25...Outermost periphery, 16.26...Outermost periphery of adhesive part, 17.27... - Polished surface, 18.28...1st point (point inside the outermost periphery), one. 29...Second point (point inside the outermost periphery of the adhesive part) 20°0...Third point (intersection of line A and substrate surface)

Claims (1)

【特許請求の範囲】 第1の半導体基板上に第2の半導体基板を接着一体化し
、且つ第2の半導体基板の表面側から厚さを減らして薄
膜化した接着半導体基板において、 前記第1及び第2の半導体基板の周辺部は、各基板の中
心を通り各基板と垂直な断面において、第1の半導体基
板の最外周部よりも内側で且つ第2の半導体基板側の周
辺部に接する点と第1及び第2の半導体基板との接着部
最外周よりも内側の点とを結ぶ線より外側が除去されて
なることを特徴とする接着半導体基板。
[Scope of Claims] A bonded semiconductor substrate in which a second semiconductor substrate is bonded and integrated on a first semiconductor substrate, and the thickness of the second semiconductor substrate is reduced from the front side to make it a thin film, comprising: The peripheral portion of the second semiconductor substrate is a point that is inside the outermost peripheral portion of the first semiconductor substrate and touches the peripheral portion on the second semiconductor substrate side in a cross section passing through the center of each substrate and perpendicular to each substrate. and a point inside the outermost periphery of the bonded portion of the first and second semiconductor substrates.
JP22067289A 1989-08-28 1989-08-28 Adhesive semiconductor substrate and method of manufacturing the same Expired - Lifetime JP2862582B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22067289A JP2862582B2 (en) 1989-08-28 1989-08-28 Adhesive semiconductor substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22067289A JP2862582B2 (en) 1989-08-28 1989-08-28 Adhesive semiconductor substrate and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH0383320A true JPH0383320A (en) 1991-04-09
JP2862582B2 JP2862582B2 (en) 1999-03-03

Family

ID=16754653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22067289A Expired - Lifetime JP2862582B2 (en) 1989-08-28 1989-08-28 Adhesive semiconductor substrate and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2862582B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096433A (en) * 1997-02-20 2000-08-01 Nec Corporation Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
JP2001345435A (en) * 2000-03-29 2001-12-14 Shin Etsu Handotai Co Ltd Silicon wafer, manufacturing method of laminated wafer and laminated wafer thereof
WO2011092795A1 (en) 2010-01-28 2011-08-04 信越半導体株式会社 Bonded wafer production method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096433A (en) * 1997-02-20 2000-08-01 Nec Corporation Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
US6346435B1 (en) 1997-02-20 2002-02-12 Nec Corporation Laminated substrate fabricated from semiconductor wafers bonded to each other without contact between insulating layer and semiconductor layer and process of fabrication thereof
JP2001345435A (en) * 2000-03-29 2001-12-14 Shin Etsu Handotai Co Ltd Silicon wafer, manufacturing method of laminated wafer and laminated wafer thereof
WO2011092795A1 (en) 2010-01-28 2011-08-04 信越半導体株式会社 Bonded wafer production method
KR20120116444A (en) 2010-01-28 2012-10-22 신에쯔 한도타이 가부시키가이샤 Bonded wafer production method
US8603897B2 (en) 2010-01-28 2013-12-10 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer

Also Published As

Publication number Publication date
JP2862582B2 (en) 1999-03-03

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