JPS63276228A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63276228A
JPS63276228A JP11281587A JP11281587A JPS63276228A JP S63276228 A JPS63276228 A JP S63276228A JP 11281587 A JP11281587 A JP 11281587A JP 11281587 A JP11281587 A JP 11281587A JP S63276228 A JPS63276228 A JP S63276228A
Authority
JP
Japan
Prior art keywords
substrate
main surface
glass plate
polishing
wax
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11281587A
Other languages
Japanese (ja)
Inventor
Kanichiro Ikeda
池田 乾一郎
Manabu Watase
渡瀬 学
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11281587A priority Critical patent/JPS63276228A/en
Publication of JPS63276228A publication Critical patent/JPS63276228A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the crack of a thin substrate by a method wherein a main surface photo resist coating process for applying a photo resist on the main surface of the substrate is added midway between a main surface electrode forming process and a rear polishing process. CONSTITUTION:Electrodes 2, 3 and 4 are formed on a substrate 1 in a main surface electrode forming process for forming the electrodes on the substrate 1. A photo resist 8 which is used for photo-engraving is applied on the side of the main surface of the substrate 1 by a spinner in a main surface photo resist coating process for applying the photo resist on the side of the main surface. The substrate 1 is adhered on a jig for the exclusive use of adhesion in a rear polishing process for polishing the rear of the substrate and the rear of the substrate 1 is polished. A wax 6 is spread on a glass plate 5 heated to the melting point of the wax 6 in a main surface glass plate adhering process for adhering the glass plate 5 on the main surface, and after the wax 6 is melted, the main surface side of the substrate 1 is adhered on the glass plate 5. Thereby, the crack of the thin substrate is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特に GaAsFETの裏面電極形成工程に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a step of forming a back electrode of a GaAsFET.

〔従来の技術〕[Conventional technology]

第3図および第4図は半導体装置製造方法の従来例を示
す工程説明図である。第3図は各工程の半導体装置の側
面断面説明図であり、第3図(a)は主面電極形成工程
後の説明図、第3図(b)は裏面研磨工程完了後の説明
図、第3図は(C)は主面ガラス板貼付工程完了後の説
明図、第3図(d)は裏面電極形成後の説明図、第3図
(e)は主面ガラス板除去工程後の説明図である。
FIGS. 3 and 4 are process explanatory diagrams showing a conventional example of a semiconductor device manufacturing method. FIG. 3 is a side cross-sectional explanatory view of the semiconductor device at each step, FIG. 3(a) is an explanatory view after the main surface electrode forming step, FIG. 3(b) is an explanatory view after the back surface polishing step is completed, In Figure 3, (C) is an explanatory diagram after the process of attaching the main glass plate is completed, Figure 3 (d) is an explanatory diagram after forming the back electrode, and Figure 3 (e) is an explanatory diagram after the process of removing the main glass plate. It is an explanatory diagram.

第4図は各工程ならびにその流れを示す概略工程説明図
である。
FIG. 4 is a schematic process explanatory diagram showing each process and its flow.

第3図中、1は半導体基板(以下基板という)、2,3
.4は基板inに形成された例えばソース、ドレイン、
ゲートの電極、5は基板1の主面に貼着するガラス板、
6はガラス板5と半導体基板1を貼着するワックス、7
は基板1の裏面に形成された裏面電極である。
In Fig. 3, 1 is a semiconductor substrate (hereinafter referred to as a substrate), 2, 3
.. 4 is formed on the substrate in, for example, a source, a drain,
a gate electrode, 5 a glass plate attached to the main surface of the substrate 1;
6 is wax for pasting the glass plate 5 and the semiconductor substrate 1; 7;
is a back electrode formed on the back surface of the substrate 1.

次に、本従来例の半導体装置製造方法を製造工程順に、
第3図、第4図を用いて概略説明する。
Next, the semiconductor device manufacturing method of this conventional example will be explained in order of manufacturing steps.
An outline will be explained using FIGS. 3 and 4.

先づ、主面電極形成工程(第4図(4a))ににおいて
、基板1の主面上にソース、ドレイン、ゲートの各電極
2,3.4を形成する(第3図(a))。
First, in the main surface electrode forming step (FIG. 4(4a)), source, drain, and gate electrodes 2, 3.4 are formed on the main surface of the substrate 1 (FIG. 3(a)). .

次に、裏面研磨工程(第4図(4b))において、基板
lの裏面の研磨を行う(第3図(b))。その後、主面
ガラス板貼着工程(第4図(4C))において、ガラス
板5上にワックス6を塗布し、その上に基板lの主面側
を貼着する(第3図(c) ) 。
Next, in the back surface polishing step (FIG. 4(4b)), the back surface of the substrate 1 is polished (FIG. 3(b)). After that, in the main surface glass plate adhesion step (Fig. 4 (4C)), wax 6 is applied on the glass plate 5, and the main surface side of the substrate l is adhered thereon (Fig. 3 (c)). ).

次に、裏面電極形成工程(第4図(4d))において、
基板lの裏面をエツチングにより鏡面にして、その上に
蒸着により裏面電極7を形成する(第3図(d))、裏
面電極7形成後、主面ガラス板等除去工程(第4図(4
e))において、ガラス板5を除去する(第3図(e)
)。
Next, in the back electrode formation step (FIG. 4 (4d)),
The back surface of the substrate l is made into a mirror surface by etching, and the back surface electrode 7 is formed thereon by vapor deposition (FIG. 3(d)). After the formation of the back surface electrode 7, the main surface glass plate, etc. is removed (FIG. 4(4)).
In e)), the glass plate 5 is removed (FIG. 3(e)
).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上のように、従来例においては、裏面研磨工程終了後
の基板1は厚さが100〜3001Lmと薄くなり、特
にca ASのように、非常に脆い基板1は割れ易く、
また、基板1の主面上の素子がワックス6に直接接触す
る部分があるため、素子が汚染され、信頼性が低下する
等の問題点があった。この発明は上記のような問題点を
解消するためになされたもので、裏面研磨工程後の薄い
基板lの割れを防止すると共に、主面上に形成された素
子を保護することを目的とする。
As described above, in the conventional example, the thickness of the substrate 1 after the back polishing process is as thin as 100 to 3001 Lm, and the substrate 1, which is extremely brittle like ca AS, is easily broken.
Furthermore, since there are parts of the main surface of the substrate 1 in which the elements come into direct contact with the wax 6, there are problems such as contamination of the elements and reduction in reliability. This invention was made to solve the above-mentioned problems, and aims to prevent the thin substrate l from cracking after the back polishing process and protect the elements formed on the main surface. .

〔問題点を解決するための手段〕[Means for solving problems]

このため、この発明においては、主面電極形成工程、裏
面研磨工程、主面ガラス板貼着工程、裏面電極形成工程
、主面ガラス板除去工程の各工程を順次実施する製造方
法であって、前記主面電極形成工程と裏面研磨工程の中
間に、基板の主面にフォトレジストを塗布する主面フォ
トレジスト塗布工程を付加することにより前記問題点を
解決し、目的を達成しようとするものである。
Therefore, the present invention provides a manufacturing method in which the following steps are sequentially performed: a main surface electrode forming step, a back surface polishing step, a main surface glass plate adhering step, a back surface electrode forming step, and a main surface glass plate removal step. The purpose is to solve the above problem and achieve the objective by adding a main surface photoresist coating step to apply a photoresist to the main surface of the substrate between the main surface electrode forming step and the back surface polishing step. be.

(作用〕 この発明における半導体装置の製造方法は、基板の主面
上にフォトレジストを塗布することにより、基板の強度
があがり、薄い基板の割れを防止する。
(Function) In the method of manufacturing a semiconductor device according to the present invention, the strength of the substrate is increased and cracking of a thin substrate is prevented by applying a photoresist on the main surface of the substrate.

〔実施例〕〔Example〕

以下、この発明の実施例を図面に基づいて説明する。第
1図および第2図はこの発明の半導体製造方法の一実施
例を示す工程説明図である。第1図は各工程後の半導体
装置の側面断面説明図であり、第1図(a)は主面電極
形成工程後の説明図、第1図(b)は主面フォトレジス
ト塗布二[程後の説明図、第1図(C)は裏面研磨工程
後の説明図、第1図(d)は主面ガラス板貼着工程後の
説明図、第1図(e)は裏面電極形成工程後の説明図、
第1図(f)は主面ガラス板等除去工程後の説明図であ
り、第2図は各工程ならびにその流第1図中、8は主面
電極形成工程後、基板1の主面上にスピンナーで厚さ2
〜3#Lmに塗布する通常の写真製版に用いられるフォ
トレジストである。
Embodiments of the present invention will be described below based on the drawings. FIGS. 1 and 2 are process explanatory diagrams showing an embodiment of the semiconductor manufacturing method of the present invention. FIG. 1 is an explanatory side cross-sectional view of the semiconductor device after each step, FIG. 1(a) is an explanatory view after the main surface electrode forming step, and FIG. Later explanatory diagrams, FIG. 1(C) is an explanatory diagram after the back surface polishing process, FIG. 1(d) is an explanatory diagram after the main surface glass plate adhesion process, and FIG. 1(e) is an explanatory diagram after the back surface electrode formation process. Later explanatory diagram,
FIG. 1(f) is an explanatory diagram after the process of removing the main surface glass plate, etc., and FIG. 2 is an explanatory diagram of each process and its flow. In FIG. with a spinner to a thickness of 2
This is a photoresist used in normal photolithography that is applied to ~3#Lm.

図中、前記従来例におけると同一または相当構成要素は
同一符号で表わし、その重複説明は省略する。
In the drawings, the same or equivalent components as those in the conventional example are represented by the same reference numerals, and redundant explanation thereof will be omitted.

次に、この発明の製造方法を工程順に第1図ならびに第
2図を用いて、前記従来例と一部重複して更に詳説する
Next, the manufacturing method of the present invention will be explained in more detail in the order of steps with reference to FIGS. 1 and 2, partially overlapping the conventional example.

先づ、基板1上に電極を形成する主面電極形成工程(第
2図(2a))において、基板1上に電極2,3.4を
形成する(第1図(a))。
First, in the main surface electrode forming step (FIG. 2(2a)) in which electrodes are formed on the substrate 1, the electrodes 2, 3.4 are formed on the substrate 1 (FIG. 1(a)).

その後、主面側にフォトレジストを塗布する主面フォト
レジスト塗布工程(第2図(2b”) )において、基
板1の主面側に通常の写真製版に用いられているフォト
レジスト8をスピンナーで厚さ2〜3#Lmに塗布する
(第1図(b))。
After that, in the main surface photoresist coating step (Fig. 2 (2b'')) in which photoresist is applied to the main surface side, a photoresist 8, which is used in ordinary photolithography, is applied to the main surface side of the substrate 1 using a spinner. Coat to a thickness of 2 to 3 #Lm (Fig. 1(b)).

次いで、裏面を研磨する裏面研磨工程(第2図(2c)
)においで、真田の9hfiに藁鼾1か■上41付は約
100〜300用mの厚さまで基板1の裏面を研磨する
。研磨後、薄くなった基板1を治具から取り外す(第1
図(C))。
Next, a back surface polishing step (Fig. 2 (2c)) is performed to polish the back surface.
), polish the back side of the substrate 1 to a thickness of about 100 to 300 m using Sanada's 9hfi and 41cm polishing method. After polishing, remove the thinned substrate 1 from the jig (first
Figure (C)).

次いで、主面にガラス板を貼着ける主面ガラス板貼着工
程(第2図(2d))において、ワックス6の融点まで
加熱したガラス板5上にワックス6を塗り、ワックス6
が溶融した後、基板1の主面側をガラス板5に貼着する
(第1図(d))。
Next, in the main surface glass plate adhesion step (FIG. 2 (2d)) in which a glass plate is attached to the main surface, wax 6 is applied on the glass plate 5 heated to the melting point of the wax 6.
After melting, the main surface side of the substrate 1 is attached to the glass plate 5 (FIG. 1(d)).

その後、裏面に電極を形成する裏面電極形成工程(第2
図(2e))において、ガラス板5に貼着した基板1の
裏面をエツチングして鏡面に仕上げ、その上に蒸着で裏
面電極7を形成する(第1図(e))。
After that, a back electrode formation step (second
In FIG. 2e), the back surface of the substrate 1 attached to the glass plate 5 is etched to give it a mirror finish, and the back electrode 7 is formed thereon by vapor deposition (FIG. 1e).

その後、主面ガラス板5等を取り外す主面ガラス板等除
去工程第2図(2f)において、基板1をガラス板5か
ら取り外し、ワックス6を洗浄にて除去し、最後にフォ
トレジスト8の剥離を行う(第1図(f))。
After that, in the main glass plate etc. removal step in FIG. 2 (2f) in which the main glass plate 5 etc. are removed, the substrate 1 is removed from the glass plate 5, the wax 6 is removed by cleaning, and finally the photoresist 8 is peeled off. (Fig. 1(f)).

以上のように、本実施例によれば、基板1の主面にフォ
トレジスト8を塗布後、薄く研磨を行い、ガラス板5に
ワックス6で貼り付けを行うので、基板1の割れを防止
できるとともに基板l上の素子をワックス6等の汚染か
ら保護することができる。
As described above, according to the present embodiment, after applying the photoresist 8 to the main surface of the substrate 1, it is polished thinly and is attached to the glass plate 5 with wax 6, so that cracking of the substrate 1 can be prevented. At the same time, the elements on the substrate 1 can be protected from contamination by the wax 6 and the like.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、半導体基板の主面電
極形成工程と、裏面研磨工程と、主面ガラス板貼着工程
と、裏面電極形成工程と、主面ガラス板等除去工程の各
工程を順次実施する半導体製造方法であって、前記主面
電極形成工程と裏面研磨工程の中間に該基板の主面にフ
ォトレジストを塗布する主面フォトレジスト塗布工程を
付加することにより、基板1の割れを防止できるととも
に基板1上の素子をワックス等から汚染されないように
保護することができる効果がある。
As described above, according to the present invention, each of the steps of forming an electrode on the main surface of a semiconductor substrate, polishing the back surface, attaching the main surface glass plate, forming a back electrode, and removing the main surface glass plate, etc. A semiconductor manufacturing method in which steps are performed sequentially, and a main surface photoresist coating step of applying a photoresist to the main surface of the substrate is added between the main surface electrode forming step and the back surface polishing step. This has the effect of preventing cracking of the substrate 1 and protecting the elements on the substrate 1 from being contaminated by wax or the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による製造方法の各工程にお
ける半導体装置の側面断面説明図であり、第1図(a)
は主面電極形成工程後の説明図、第1図(b)は主面フ
ォトレジスト塗布工程後の説明図、第1図(C)は裏面
研磨工程後の説明図、第1図(d)は主面ガラス板貼着
工程後の説明図、第1図(e)は裏面電極形成後の説明
図、第1図(f)は主面ガラス板等除去工程後の説明図
であり、第2図は第1図の各工程ならびにその流れを示
す概略工程説明図、第3図は従来例による製造方法の各
工程における半導体装置の側面断面説明図であり、第3
図゛(a)は主面電極形成工程後の説明図、第3図(b
)は裏面研磨工程後の説明図、第3図(C)は主面ガラ
ス板貼着工程後の説明図、第3図(d)は裏面電極形成
後の説明図、第3図(e)は主面ガラス板除去工程後の
説明図であり、第4図は第3図の各工程ならびにその流
れを示す概略工程説明図である。 1・・・・・・半導体基板 2.3.4・・・・・・電極 5・・・・・・ガラス板 7・・・・・・裏面電極 8・・・・・・フォトレジスト
FIG. 1 is a side cross-sectional explanatory view of a semiconductor device in each step of a manufacturing method according to an embodiment of the present invention, and FIG. 1(a)
is an explanatory diagram after the main surface electrode forming process, FIG. 1(b) is an explanatory diagram after the main surface photoresist coating process, FIG. 1(C) is an explanatory diagram after the back surface polishing process, FIG. 1(d) 1(e) is an explanatory diagram after the process of attaching the main surface glass plate, FIG. 1(e) is an explanatory diagram after forming the back electrode, and FIG. 2 is a schematic process explanatory diagram showing each process and its flow in FIG. 1, and FIG.
Figure 3 (a) is an explanatory diagram after the main surface electrode formation process, Figure 3 (b)
) is an explanatory diagram after the back surface polishing process, FIG. 3(C) is an explanatory diagram after the main surface glass plate adhesion process, FIG. 3(d) is an explanatory diagram after the back surface electrode formation, and FIG. 3(e) is an explanatory diagram after the back surface polishing process. 4 is an explanatory view after the main surface glass plate removal process, and FIG. 4 is a schematic process explanatory view showing each process of FIG. 3 and its flow. 1... Semiconductor substrate 2.3.4... Electrode 5... Glass plate 7... Back electrode 8... Photoresist

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に電極を形成する主面電極形成工程
、該基板裏面を研磨する裏面研磨工程、該基板主面にワ
ックスでガラス板を貼付する主面ガラス板貼付工程、該
基板の裏面を鏡面研磨後裏面電極を形成する裏面電極形
成工程、該基板の主面ガラス板等を除去する主面ガラス
板除去工程の各工程を順次実施する半導体装置の構造方
法であって、前記主面電極形成工程と裏面研磨工程の中
間に、該基板の主面にフォトレジストを塗布する主面フ
ォトレジスト塗布工程を付加したことを特徴とする半導
体装置の製造方法。
(1) Main surface electrode formation step of forming electrodes on a semiconductor substrate, back surface polishing step of polishing the back surface of the substrate, main surface glass plate attaching step of attaching a glass plate to the main surface of the substrate with wax, back surface of the substrate A method for structuring a semiconductor device, comprising sequentially performing a back electrode forming step of forming a back electrode after mirror polishing a substrate, and a main glass plate removing step of removing a main glass plate of the substrate, the method comprising: 1. A method for manufacturing a semiconductor device, characterized in that a main surface photoresist coating step of applying a photoresist to the main surface of the substrate is added between the electrode forming step and the back surface polishing step.
(2)前記主面フォトレジスト塗布工程は半導体基板の
主面に写真製版用フォトレジストを2〜3μmの膜厚に
塗布する工程であることを特徴とする特許請求の範囲第
1項記載の半導体装置の製造方法。
(2) The semiconductor according to claim 1, wherein the main surface photoresist coating step is a step of applying a photolithographic photoresist to a film thickness of 2 to 3 μm on the main surface of the semiconductor substrate. Method of manufacturing the device.
JP11281587A 1987-05-07 1987-05-07 Manufacture of semiconductor device Pending JPS63276228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11281587A JPS63276228A (en) 1987-05-07 1987-05-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11281587A JPS63276228A (en) 1987-05-07 1987-05-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63276228A true JPS63276228A (en) 1988-11-14

Family

ID=14596224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11281587A Pending JPS63276228A (en) 1987-05-07 1987-05-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63276228A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244818A (en) * 1992-04-08 1993-09-14 Georgia Tech Research Corporation Processes for lift-off of thin film materials and for the fabrication of three dimensional integrated circuits
WO1993021663A1 (en) * 1992-04-08 1993-10-28 Georgia Tech Research Corporation Process for lift-off of thin film materials from a growth substrate
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
US5244818A (en) * 1992-04-08 1993-09-14 Georgia Tech Research Corporation Processes for lift-off of thin film materials and for the fabrication of three dimensional integrated circuits
WO1993021663A1 (en) * 1992-04-08 1993-10-28 Georgia Tech Research Corporation Process for lift-off of thin film materials from a growth substrate
US5401983A (en) * 1992-04-08 1995-03-28 Georgia Tech Research Corporation Processes for lift-off of thin film materials or devices for fabricating three dimensional integrated circuits, optical detectors, and micromechanical devices

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