JPS6220361A - Mounting method for heat sink fin - Google Patents

Mounting method for heat sink fin

Info

Publication number
JPS6220361A
JPS6220361A JP15950285A JP15950285A JPS6220361A JP S6220361 A JPS6220361 A JP S6220361A JP 15950285 A JP15950285 A JP 15950285A JP 15950285 A JP15950285 A JP 15950285A JP S6220361 A JPS6220361 A JP S6220361A
Authority
JP
Japan
Prior art keywords
pattern
mounting
heat dissipation
oxide film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15950285A
Other languages
Japanese (ja)
Inventor
Shigeru Miyagawa
宮川 滋
Toyokazu Nakamura
中村 豊和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP15950285A priority Critical patent/JPS6220361A/en
Publication of JPS6220361A publication Critical patent/JPS6220361A/en
Pending legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the solderability by mechanically removing an oxide film of a portion to be soldered with a semiconductor element of the surface of a conductor layer formed by metallizing, and immediately soldering the cap of the element on the removed portion after removing. CONSTITUTION:The surface of an aluminum substrate 1 is roughed by sand- blasting, fine alumina powder is melted in a plasma arm to form a mounting pattern electrically independent from the substrate, the liquefied powder is injected to form an alumina insulating layer 3 only the prescribed range on the substrate. Copper fine powder is melted in a plasma, and injected to obtain a pattern 4 on a mounting pattern 2 and the layer 3. Then, a semiconductor element mount in the pattern 2 and a conductor pattern 4 are ground and removed at six portions over the depth of 50-100mum in diameter larger than the cap 10a of the element with a rotary abrasive formed with grinding surface on the cylindrical surface. Thus, soldering with high reliability can be performed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、発熱部品への放熱フィンの実装方法に関する
もので、特に電源素子の実装に使用されるものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for mounting a radiation fin on a heat generating component, and is particularly used for mounting a power supply element.

〔発明の1に術的背県〕 整流素子等発熱の多い半導体素子については性能を糾持
J−るために適当な放熱が必要で、このため一般に放熱
フィンが使用される。
[Technical Background of Invention 1] Semiconductor elements that generate a lot of heat, such as rectifier elements, require appropriate heat radiation to maintain their performance, and for this reason, heat radiation fins are generally used.

この放熱フィンは複数の整流素子を同時に実装した整流
アセンブリ製品等にも使用される。
These heat dissipation fins are also used in rectifier assembly products in which multiple rectifier elements are mounted simultaneously.

第3図おにびイのB−8断面図Cある第4図はこのよう
な従来の整流アセンブリに使用される放熱フィンの構成
を示すもので、アルミニウム製のL1板1上に直接銅溶
射により形成され1こ素子取令1のための第1の導体パ
ターン2、溶射形成されl、:アルミナ(M化アルミニ
ウム)絶縁層3を介して銅溶射で形成された素子取付の
ための第2の導体パターン1、アルミニウム基板1から
電気的接続をとるための銅溶射による引出しパターン5
が形成されでいる。
Figure 4, which is a cross-sectional view of B-8 in Figure 3, shows the configuration of the radiation fins used in such conventional rectifying assemblies. A first conductor pattern 2 for mounting the element 1 formed by thermal spraying: A second conductor pattern 2 for mounting the element formed by thermal spraying copper through an alumina (aluminum Mide) insulating layer 3. conductor pattern 1, copper sprayed lead-out pattern 5 for electrical connection from aluminum substrate 1
has been formed.

このように形成された銅の取イ・1パターン2および4
」−には第4図に示t 、J:うに整流素子等の半導体
素子10がそのキセップ部10aをはんだ付Jることに
にり取(SF +)られている。
Copper pattern 1 pattern 2 and 4 formed in this way
4, a semiconductor element 10 such as a rectifying element is soldered (SF+) to its kissep part 10a.

〔背題技術の問題点〕[Problems with background technology]

しかしながら、このような実装構造にJ3いては半)9
体素子が取イ]けられる銅等の導体パターンは溶DIで
形成されているためにプラズマにJζる加熱処理を受(
)て表面に酸化膜が形成されている。このため、半導体
素子や端子等をは/υだ(lづ−る際に酸化膜のだ−め
にはんだの濡れ性が非常に悪く、はんだイ・1の信頼性
に欠【プる。
However, in such a mounting structure, J3 is half)9
Since the conductor pattern made of copper or other material from which the body element is removed is formed by molten DI, it is subjected to plasma heat treatment.
), an oxide film is formed on the surface. For this reason, when attaching semiconductor elements, terminals, etc., the wettability of solder to the oxide film is very poor, and the reliability of solder I-1 is lacking.

これを解決するために強力なフラックスを用いることが
できるが、十分<’に洗浄が必要と41す]二稈増を招
く。
A strong flux can be used to solve this problem, but requires sufficient cleaning and leads to double culm growth.

はんだ何時の酸化を防由するためにはんだ角界囲気を〕
9元性に1−ることもできるが、十分でなく、これらの
両方法でははんだ(jt 1’!の厳しい外観検査およ
びこの外観検査、13 J:びこの外観検査で不良とさ
れたものの修正に多大の時間を要J゛ることになる。
To prevent oxidation of the solder, use a solder corner surrounding the solder.
Although it is possible to apply 1- to 9-dimensionality, it is not sufficient, and both of these methods require strict visual inspection of the solder (jt 1'! and this visual inspection, 13 J: correction of defects determined by the external visual inspection of This will require a large amount of time.

また、導体パターン表面上の酸化膜を酸を用いて除去す
ることもできるが、溶m層はポーラスな構造となってい
るため有害な酸が内部に浸透しやすく、かつ浸透した酸
は除去しにくいため、後に酸化を生じたり、アルミニウ
ム基板を侵食したりして信頼性を損うという問題がある
In addition, the oxide film on the surface of the conductor pattern can be removed using acid, but since the molten m layer has a porous structure, harmful acids can easily penetrate inside, and the permeated acid cannot be removed. Because of this, there is a problem that oxidation occurs later or corrodes the aluminum substrate, impairing reliability.

〔発明の目的〕[Purpose of the invention]

本発明はこのJ:うな問題を解決覆るためになされたも
ので、はんだイマ1性を向、1コさせた放熱フィンの実
装方法を提供することを目的とする。
The present invention has been made to solve and overcome the above problem, and an object of the present invention is to provide a method for mounting a heat dissipation fin that improves solder immobility and has a single heat dissipation fin.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明においては、溶射で形
成された導体層表面を少なくとも半導体素子のはlυだ
付を行う部分の酸化膜を機械的に除去し、除去後ただち
に除去部分に半導体素子のキセップ部をはんだ伺するよ
うにしており、信頼性の高いはんだ付が可能どなってい
る。
In order to achieve the above object, the present invention mechanically removes the oxide film on the surface of the conductor layer formed by thermal spraying, at least in the part where the semiconductor element is to be exposed, and immediately after the removal, the semiconductor element is placed on the removed part. The kissep part of the product is soldered, making highly reliable soldering possible.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の一実施例を説明する。 An embodiment of the present invention will be described below.

第1図は本発明のかかる放熱フィンの実装方法に使用覆
る放熱フィンの構成を示す平面図であって、従来のt)
のと同様に放熱性の良好/iアルミニウム製の基板1内
に直接銅溶射により形成された素子取付のための第1の
導体パターン2、溶用形成されたアルミナ絶縁層3を介
して銅溶射で形成された素子数イ;1のための第2の導
体パターン4、アルミニウム基板1から電気的接続をど
るための銅溶射にJ:る引出1ツバターンが形成されて
いる。
FIG. 1 is a plan view showing the configuration of a heat dissipation fin used in the heat dissipation fin mounting method of the present invention, and is a plan view showing the structure of a heat dissipation fin used in the heat dissipation fin mounting method of the present invention.
Good heat dissipation as well/i First conductor pattern 2 for mounting the element formed by direct copper spraying on the aluminum substrate 1, copper spraying via the alumina insulating layer 3 formed by melting. A second conductor pattern 4 for the number of elements formed with 1 and a drawer 1 flange turn are formed on the copper spraying for electrical connection from the aluminum substrate 1.

このような溶射ににる層形成は次のように行われる。Layer formation using such thermal spraying is performed as follows.

まず例えば厚さ1.0Mのアルミニウム基板1の表面を
サンドブラスト等にj;り粗面化り−る。この粗面化は
後に溶射を行う部分だ()が露出してプラス1−が噴射
されるようなブラストマスクを用いて行うこともできる
First, the surface of an aluminum substrate 1 having a thickness of 1.0 m, for example, is roughened by sandblasting or the like. This surface roughening can also be carried out using a blast mask that exposes the part () that will be thermally sprayed later and sprays the +1-.

=  4 − 次に、基板から電気的に独立した取付パターンを形成す
るためにアルミナの微粉末をプラズマアーク中で溶融さ
せ液化された微粉末を噴射することにより基板面に約0
.2mmの〃さて堆積させる。
= 4 - Next, in order to form a mounting pattern that is electrically independent from the board, fine alumina powder is melted in a plasma arc and the liquefied fine powder is injected onto the board surface.
.. Now deposit 2mm.

この際所定範囲のみにアルミナ絶縁層3が形成されるJ
:うに基板1上にマスクを置いてプラズマ溶射を行うよ
うにする。
At this time, the alumina insulating layer 3 is formed only in a predetermined area.
: Place a mask on the sea urchin substrate 1 and perform plasma spraying.

次に同様に基板1上にマスクを載置して銅の微粉末をプ
ラズマ中で溶融させて噴射することにより基板上に約0
.15mmの厚さで直接形成された取付パターン2およ
びアルミナ絶縁層3上に形成された約0.15mmの厚
さのパターン4を1qる。
Next, a mask is placed on the substrate 1 in the same manner, and fine copper powder is melted in plasma and sprayed onto the substrate.
.. A mounting pattern 2 formed directly on the alumina insulating layer 3 with a thickness of 15 mm and a pattern 4 with a thickness of about 0.15 mm formed on the alumina insulating layer 3 are 1q.

次に導体パターン2および導体パターン4内の半導体素
子数イ4部を同筒低面に砥面が形成された回転砥石を用
いて半導体素子のキレ91部10aよりも大ぎい直径で
50〜100μmの深さ例えば80μにわたって計6か
所を研削し除去する。
Next, 4 parts of the semiconductor elements in the conductor pattern 2 and the conductor pattern 4 are polished to a diameter of 50 to 100 μm larger than the sharpened part 10a of the semiconductor element using a rotary grindstone with an abrasive surface formed on the lower surface of the cylinder. A total of six locations are ground and removed over a depth of, for example, 80μ.

この研削後、研削部の表面に酸化膜が再形成されないう
ちに研削部に松ヤニ入りはんだプリフオームおよび接合
すべぎ整流素子等を載置し、調度270 ’Cの[i、
7.炉中IJiiりくことIJより、リフ[1−(よん
だイ・1を(イ゛う(′どに。J、り整流素子10がは
ん1、=7 +、、: 、、l、り固旨七\れl、二4
’lXX mj @ I!16゜(−のよ−)4I:実
装方法でLL半導体メ蟻子が取(jl 1.Jられる導
体パターン表i’rijを1(11削(・(入面酸化+
1tiを除去([るようにし、酸化膜が711形成され
る前(、−はΔ。
After this grinding, before the oxide film is re-formed on the surface of the ground part, the solder preform containing pine resin and the rectifying element for bonding, etc. are placed on the ground part, and the temperature is 270'C.
7. In the furnace, from IJii Rikukoto IJ, the riff [1-(read I・1(I)(').J, the rectifying element 10 is 1,=7 Solid idea 7\rel, 24
'lXX mj @I! 16゜(-) 4I: The mounting method removes the conductor pattern surface i'rij of the LL semiconductor (jl 1.J).
1ti is removed before the oxide film 711 is formed (, - is Δ.

だ(N+を行う、1、−)i4二しノているl、二v)
、仁東目11の高い良好イ1はΔ、だイ・1が可能どイ
「る。しL−が−)で不■;!キお51、び修iT率を
10−・・11)%から0.3−・(L7%に大幅に減
少さ1!る(二J−が可能とイYす、ノシックス−1)
弱い1−)の(・0−1分である)、:め洗浄IT稈ノ
)’ l!t’l略化まIζ−は省1gできるように4
L−′)C伯Σ1こ効率0向十−1j  イ) 。
(Do N+, 1, -) i4 2 and do l, 2v)
, Nitome 11's high good A1 is Δ, and D1 is possible. % to 0.3-・(L7%) 1! (2 J- is possible, no six-1)
Weak 1-)'s (・0-1 minutes), :me cleaning IT culm)'l! t'l is abbreviated or Iζ- is 4 so that 1g can be omitted.
L-')

以上の実施例ではう9体層ど1ノで銅を用い、il′l
接ノイル上おJ、びアルミナ絶縁膜を介しで導体層を形
成するようにしているが、これに限ること41<、他の
金属Aゝ)イの合金等を導体層とし・(用い、1)l二
組縁膜に」、り電源系統を分()ること41:クノイン
I−のみ(ご導体層を形成するように1)で1)よい1
、また絶縁層を使用りる際には実施例の、j−うイ=、
酸化アルーミニウムの他、酸化干すゾfン等の熱伝導が
良好イ丁絶縁祠オ′々lを使用するにニどがでンきる3
、さらにを1ホ層は実施例の」、′>(、二フィン−1
−の一部とり−るばか(つC’:’:<、フィン表面の
全面に形成1−るように1−・でし、1、い4.この場
合サンドブ、ラス1−は全面に行われる。
In the above embodiment, copper is used in each of the nine layers, and
A conductor layer is formed on the contact electrode through the alumina insulating film, but this is limited to the conductor layer made of an alloy of 41<, other metals A), etc. (using, 1 41: Separate the power supply system into two sets of membranes () 41: 1) Good 1) with only the Knoin I- (1) to form a conductor layer
, and when using an insulating layer, in the embodiment, j-Ui=,
In addition to aluminum oxide, oxidized drying zone etc. have good heat conductivity.
, furthermore, the first layer is ``,′>(, the second fin-1 layer of the embodiment
A part of the fin is formed on the entire surface of the fin. be exposed.

シした酸化9rの除去範囲は実施例の、1、うに導体層
の−・部だにひ4I:り、Q1体層の全面を例えば平面
1i11削咄を用い−C除去リ−ることもでさる1、ま
た、はんだ付は炉を用いI、:リフ[]−で・行ってい
るが、はんだ鏝、熱板、熱風、ベーパ等の公知の各種の
1ノ法を使用することがCきる。
The removal range of the oxidized 9R is as shown in Example 1. It is also possible to remove -C from the entire surface of the conductor layer by using plane 1i11 abrasion. Also, soldering is done using a furnace, but various known methods such as a soldering iron, hot plate, hot air, vapor, etc. can be used. .

さらには/υだイ]の対象物どしては半導体素子に限る
ことなく各種の能動素子や受動部品ノー)適用される。
Furthermore, the target object of /υday is not limited to semiconductor devices, but can be applied to various active elements and passive components.

〔発明の効果〕〔Effect of the invention〕

以上実施例にもとづいC詳)ホbだように本発明によれ
ば、放熱フィン1〜に形成された溶q・1導体層の表面
酸化膜を機械的に除去1ノ、酸化膜の再形成前に発熱素
子等をはんだ(+t ツるようにしているのて゛信頼性
の高いはんだイ〈1が可能となり、また強いフラックス
ヤ)酸等の処理液を用いる必要が’xrいため洗浄等の
処即が不要どもって一イバ頼刊の白土と1ノ[業効率の
向上を図ることができる。
Based on the above embodiments, according to the present invention, the surface oxide film of the molten conductor layer formed on the heat dissipation fins 1 to 1 is mechanically removed, and the oxide film is re-formed. Soldering the heating element etc. beforehand (+t) makes it possible to use highly reliable soldering (1), and there is no need to use processing liquids such as strong flux, so cleaning, etc. You can improve your work efficiency without having to stutter.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に使用する放熱フィンの構成を承り一5
17面図、第2図【まイの△−△断面図て゛あって部品
取付状態を承りもの、第3図は従来の放熱フィンの構成
を示づ−jri面図、第4図はその[3、−、B断面図
である。 1・・・基板、2,4・・・)υ体層、3・・・絶縁層
、55・・・引出し部、6・・・rdT Ti11部、
7・・・はんだ、10・・・整流素子、10a・・・キ
トツブ。 出願人代哩人  仏  藤  −kjl第1図 第3図 第2図 第4図
Figure 1 shows the configuration of the radiation fin used in the present invention.
17 side view, Fig. 2 is a △-△ cross-sectional view of [my], showing the state in which the parts are installed, Fig. 3 is a -Jri side view showing the configuration of a conventional heat dissipation fin, and Fig. 4 is its [ 3, -, B sectional view. DESCRIPTION OF SYMBOLS 1... Substrate, 2, 4...) υ body layer, 3... Insulating layer, 55... Lead-out part, 6... rdT Ti11 part,
7... Solder, 10... Rectifying element, 10a... Kitotsubu. Applicant's Representative Buddha Fuji -kjlFigure 1Figure 3Figure 2Figure 4

Claims (1)

【特許請求の範囲】 1、放熱性の良好な金属基板よりなる放熱フィン上に導
体層を金属溶射で形成する工程と、この溶射導体層表面
のうち少なくとも発熱部品をはんだ付する部分から表面
酸化膜を機械的に除去する工程と、 この表面酸化膜除去後、酸化膜の再形成前に前記表面酸
化膜除去部分に前記発熱部品をはんだ付する工程と、 を備えた放熱フィンの実装方法。 2、表面酸化膜の機械的除去が研削により行われる特許
請求の範囲1項記載の放熱フィンの実装方法。 3、放熱フィンがアルミニウム板であり、溶射導体が銅
である特許請求の範囲第2項記載の放熱フィンの実装方
法。 4、金属溶射がプラズマ溶射で行なわれる特許請求の範
囲第1項記載の放熱フィンの実装方法。
[Claims] 1. A process of forming a conductor layer by metal spraying on a heat dissipation fin made of a metal substrate with good heat dissipation properties, and surface oxidation of at least a portion of the surface of the sprayed conductor layer to which a heat generating component is soldered. A method for mounting a heat dissipation fin, comprising: mechanically removing a film; and after removing the surface oxide film and before re-forming the oxide film, soldering the heat generating component to the portion from which the surface oxide film has been removed. 2. The method of mounting a heat dissipation fin according to claim 1, wherein the mechanical removal of the surface oxide film is performed by grinding. 3. The method of mounting a heat dissipation fin according to claim 2, wherein the heat dissipation fin is an aluminum plate and the thermally sprayed conductor is copper. 4. The method for mounting a heat dissipating fin according to claim 1, wherein the metal spraying is performed by plasma spraying.
JP15950285A 1985-07-19 1985-07-19 Mounting method for heat sink fin Pending JPS6220361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15950285A JPS6220361A (en) 1985-07-19 1985-07-19 Mounting method for heat sink fin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15950285A JPS6220361A (en) 1985-07-19 1985-07-19 Mounting method for heat sink fin

Publications (1)

Publication Number Publication Date
JPS6220361A true JPS6220361A (en) 1987-01-28

Family

ID=15695167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15950285A Pending JPS6220361A (en) 1985-07-19 1985-07-19 Mounting method for heat sink fin

Country Status (1)

Country Link
JP (1) JPS6220361A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011258764A (en) * 2010-06-09 2011-12-22 Denso Corp Semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011258764A (en) * 2010-06-09 2011-12-22 Denso Corp Semiconductor module

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