JPS6219953A - Recognizing system for packaged storage capacity - Google Patents

Abstract

PURPOSE:To know accurately the storage capacity for each memory chip group by recognizing the presence or absence of packaged storage capacity with signals produced from each memory packaging unit in response to a test address signal. CONSTITUTION:A detector circuit 2 decodes a test address signal 3. When the signal 3 specified a memory chip group 11 of a memory card A, for example, the signal '1' is supplied to an input terminal 12 of the card A. Then the output of a driver 13 is set at '0' and therefore the group 11 is excited. While the signal '1' received by the terminal 12 is delivered to an output terminal 15 via an OR circuit 14. Thus the chip selection signal received once by the group 11, i.e., the packaging unit is delivered again. Then it is decided that the corresponding output signal does not exist if no packaging unit exists. A reading circuit recognizes the presence of the group 11 on a memory card 1 in relation to the signal 3.

Description

[Detailed Description of the Invention] [Summary] A method for recognizing the installed storage capacity of a storage device, in which the installed storage capacity is determined by a signal issued from each memory implementation unit in response to a test address signal for each memory implementation unit. Recognize the presence or absence of

[Industrial application field]

The present invention relates to a method for recognizing the storage capacity installed in a storage device.

Usually, a memory chip group is made up of memory chips in which a large number of unit storage elements are integrated into an integrated circuit, and several memory chip groups are further mounted on a printed circuit board to form a memory card.

Therefore, the storage capacity of a storage device equipped with memory cards is determined by the number of memory cards and the memory capacity and number of memory chips mounted therein.

Then, the data processing device is equipped with a storage device having a storage capacity necessary to process the required business, and the storage capacity is adjusted by the number of memory cards to be installed and the memory chips to be installed.

This method is a reasonable way to increase or decrease the memory capacity according to the required amount, but if you do not make sure that the required number of memory cards or memory chips are inserted in the specified positions, This may result in insufficient storage capacity and no storage element at the specified address, which may cause unexpected trouble.

Therefore, in order to prevent such troubles from occurring,
Before operating the data processing device, it is necessary to confirm in advance that the required number of memory cards and memory chips are installed at predetermined positions.

Alternatively, it is necessary to operate the system after recognizing the number and location of memory cards and memory chips.

Therefore, a simple method for checking these quantities and their positions is required.

[Conventional technology]

Conventionally, the method for recognizing the storage capacity of a storage device was to visually check the required number of memory cards and their predetermined locations.

Since this method involves misperceptions and miscalculations, a method as shown in Figure 3+a1 was devised.

The memory card 1 is assumed to be equipped with up to two groups of memory chips, each group is provided with a constant generation circuit 10, and if a memory chip group is mounted, a signal is output to the output terminal of the corresponding constant generation circuit 10, for example. Make sure that "1" is output.

However, in FIG. 3(a), an inverting driver element is used in the constant generating circuit 10, so the input signal thereof is "0".

The reading circuit 41 has a recognition circuit corresponding to each memory chip group, and if "1" is read, the existence of the memory chip group 11 is confirmed.

FIG. 3(b) shows a driver element lO between the input and output terminals in the memory card 1 for each memory chip group of the memory card 1.
Corresponding terminals of each memory card 1 are connected in cascade by being connected through the terminal or by short-circuiting.

Then, connect a signal source that generates signal “1” to the starting point terminal,
If a signal "1" is output to the reading circuit 42 at the end point, it means that a predetermined number of memory cards are installed at a predetermined position.

Further, if the signal rOJ is output, it indicates that one of the memory cards is not inserted in the predetermined position.

In FIG. 3(c), the signal rlJ from the memory card in FIG. 3(a) is input to an AND circuit (hereinafter referred to as an AND circuit) in the reading circuit 43, and the output signal rlJ of the AND circuit is input to the AND circuit. This is a method of detecting and confirming that the memory card is inserted correctly.

[Problem that the invention seeks to solve]

In FIG. 3A, it is possible to recognize whether or not each memory chip group is mounted in each memory card, but this requires a large number of wiring lines and also requires a large number of input terminals of the reading circuit 41.

The methods shown in Figures 3(b) and 3(C) are methods for checking whether all memory cards are installed.
) In the method shown in the figure, the input/output connection terminal of the memory card is the third (a)
This method requires four terminals, which is twice as many as the method shown in FIG.

Alternatively, the method shown in FIG. 3(C) requires a large number of wiring lines and a large number of input terminals of the reading circuit 43.

The present invention was created in view of these points, and an object of the present invention is to provide a method for recognizing the storage capacity installed in a storage device with a simple configuration.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the implemented storage capacity recognition method of the present invention.

In FIG. 1, ``■'' is a memory card mounted in a storage device, 2 is a decoder circuit, and an address signal 3 specifying a memory chip group 11 of the memory card 1 is input to the decoder circuit 2.

The decoder circuit 2 decodes the address signal 3 and sends a signal "1" to the input terminal 12 of the memory card 1 to which the memory chip group 11 specified by the address signal 3 is connected.

The memory card 1 has an input terminal 12 for a memory chip group 11 to be mounted, and the input terminal 12 is connected to a driver circuit 13, and a signal logically inverted by the driver circuit 13, in this case a signal "0", is input to the memory chip group 11. is input.

On the other hand, the non-inverting output of the driver circuit 13, in this case the signal r
lJ becomes an input to a logical sum circuit (hereinafter referred to as an OR circuit) 14.

Signals from all input terminals 12 of the memory card are connected to the input of this OR circuit via a driver circuit 13.

The output of the OR circuit 14 is connected to the output terminal 15 of the memory card 1, and the output terminal 15 of the memory card 1 is connected to the bus line 16.
A common connection (dot-OR) is made to the reading circuit 44.

[Effect]

To specify a memory chip group of a memory card, an address signal of the specified memory chip group, that is, a test address signal 3 is input to the decoder circuit 2.

The decoder circuit 2 decodes the test address signal 3 and, for example, if the signal specifies the memory chip group 11 of the memory card A, a signal "1" is sent to the input terminal 12 of the memory card.
is input and the output of the driver 13 is set to "0", thereby exciting the memory chip group 11.

On the other hand, the signal "1" received at the terminal 12 is transmitted to the OR circuit 14.
The signal is output to the output terminal 15 via.

By re-outputting the chip select signal once received by the memory chip group 11 which is the mounting unit,
When that mounting unit does not exist, the output signal also does not exist.

The reading circuit recognizes the presence of a memory chip 11 in the memory card 1 in conjunction with the test address signal 3 .

That is, when the test address signal 3 specifies the address of the memory chip group 11, if there is a signal "1" in the reading circuit, it can be confirmed that the memory chip group 11 exists, and the test address signal 3 is sequentially changed. The number of bus lines each time is 16.
The storage capacity can be recognized by checking the above signal.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Note that the same reference numerals indicate the same objects throughout the figures.

In this example, the description will be made assuming that the memory card accommodates two groups of memory chips.

FIG. 2 shows an embodiment of the present invention, in which an access address is normally sent from a control device when accessing a storage device.

In the figure, the upper bit 3° in the access address is a chip select address signal, which is used as a bit for specifying the memory chip group 11 and acts as a single input of the switching circuit 20, and the test address signal 3 created to recognize the mounting capacity is This is the other input.

When accessing the storage device, the output of the switching circuit 20 is the chip select address 3' of the access address.

Further, the output of the switching circuit 20 is switched to the test address signal 3 by the test signal.

The memory card 1 includes an input terminal 12, a driver circuit 13, and a predetermined number of memory chips 101, forming one unit of a memory chip group.

That is, the mounted capacitance is recognized in this unit, and furthermore, the non-inverted output of each driver circuit 13 becomes the input of the OR circuit 14,
The extracted output of the OR circuit is connected to one output terminal 15 of the memory card.

When only one memory chip group is mounted on one memory card, as in memory card A in Figure 1, there is no driver circuit for the chip group that is not mounted, so this chip group is specified by the test address signal. OR circuit 1
4 does not generate a signal "1", so it can be recognized that that chip group is not mounted.

As described above, the address signal specifying the memory chip group 11 can be sent from the control device using the upper focus of the chip select signal, but since the means for separating the recognition from the access data becomes complicated, the present invention is not suitable. The explanation clarified the separation as a test address signal.

In the above description, a group of chips is assumed as a mounting unit, but the present invention is not limited to this, and it goes without saying that a chip or a card may be used as a mounting unit.

〔Effect of the invention〕

As described above, according to the present invention, only the output terminal 15 of each memory card 1 is required, only the bus line 16 is required for wiring, and only one input terminal of the reading circuit is required, resulting in an extremely simple circuit. With this configuration, the storage capacity of the storage device can be accurately grasped in units of memory chip groups, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the mounting capacity recognition system of the present invention, FIG. 2 is a diagram of an embodiment of the present invention, and FIG. 3 is a diagram of a conventional example. In the figure, 1 is a memory card, 2 is a decoder circuit, 11 is a memory chip group (memory mounting unit), 13 is a driver circuit, 14 is an OR circuit, 15 is a memory card output terminal 16 is a bus line, ( C) Arrival 9th figure 3m

Claims (2)

[Claims] (1) In a storage device comprising a means (2) for decoding a memory address and a plurality of memory mounting units (11) selected by a selection signal from the decoding means (2), the memory mounting unit (11) is provided with means (13) for outputting the once received selection signal to the outside again, and means (14, 15, 16, 44) for reading the output of the output means (13) of the plurality of memory implementation units (11). is provided, and when a desired memory address is given, the reading means (1
4, 15, 16, 44), the presence or absence of a memory mounting unit corresponding to the memory address is recognized based on whether a predetermined signal is read or not. (2) The above memory mounting unit (11) is a memory card (
1) A plurality of memory chip groups (11) mounted on the memory card (1); means (14) for calculating the logical sum of the outputs of (13);
A terminal (15) for outputting the output of the OR means (14) to the outside of the memory card (1), and a terminal (15) for outputting the output of the logical sum means (14) to the outside of the memory card (1);
) terminal (15) and multiple memory card (1) terminal (
15) and a bus line (16) that commonly connects the mounted storage capacity recognition method according to claim 1.