SU453685A1 - CONTROL DEVICE INPUT-OUTPUT - Google Patents

Description

one

The invention relates to the field of computer technology and can be used in the construction of computer systems.

Control devices for input and output are known, comprising information output control units, control signals, information and control signal registers, control unit, command, data and status registers, address block, control and sampling circuits. The information and control inputs of the device are connected to the inputs of information registers and control signals. The outputs of the control unit are connected to the inputs of the B1 circuit B1, information output units and control signals.

The disadvantage of the known I / O control devices is the lack of means to provide the native control modes necessary for checking the operation of the channels of the microprocessor, as well as the lack of the possibility of forming different, pre-set 1 byte bytes, and the possibility of changing the speed of irregular data over a wide range.

The purpose of the invention is to eliminate these disadvantages.

The goal is achieved in ycToption by the fact that it contains in its entirety a block that regulates 3x requests, a state indication block and a block of control modes. The output of the control register register is connected to the inputs of the address block, the sampling circuit, the output unit of the control signals, the command register of the control block.

The output of the reception regnstra information is connected to the input of the command register, the address block and the control circuit, the output of which is connected to the command register on the address block. The outputs of the control unit are connected to the inputs of the state indication unit, the mode control unit.

The inputs-outputs of the control unit are connected according to the 5e1u to the unit of regulated resettings on the data register, the output of which is connected to the input of the information output unit. The inputs of the control unit are connected to the outputs of the command register, the sampling circuit, the control signal output unit, and the address block, the output of which is also connected to the input of the information output unit.

The output of the mode control unit is connected to the inputs of the control signal issuing unit, the sampling circuit, and the information transfer unit V111. The output of the output unit of the uni-signals is connected to the inputs of the information issuing unit and the indicated state unit, one output of which is connected to the input of the information outputting unit, and the second output is connected to the status register, the output of which is connected to the input of the outputting unit.

The drawing shows a block diagram of the device.

It contains the control signal output unit 1, the information output unit 2, the control mode block 3, the dai 4 register, the status register 5, the control block 6, the variable command block 7, the status indication block 8, the sampling circuit 9, the command register 10, address block 11, control circuit 12, reception register of control 1, their signals 13, information register 14, input control H 15s, input information buses 16, output control buses 17 and output data H1INs 18.

The device works as follows.

The I / O control unit is connected via input and output control units, their buses 15 and 17, as well as input and output information spikes 16 and 18 to the input / output channels (not shown in the drawing).

The channel sends to the input information buses 16 bytes of the address and accompanies it by the "channel address on the input control ports (15 bytes. The address byte is checked by parity control 12). If the check bit is correct, the address byte is compared in the address block 11 with its own When the addresses in the address block 11 are combined, the signal is generated and the addresses are equal and output through the control unit 6 1 by the sampling circuit 9.

With a delay sufficient to decode the address and compare the address, it drops the cni-sample to the input controllers of PINES 15. This signal, when the addresses match, is received through the receive register of control1, their signals 13 and sampling circuit 9 into control unit 6. If the addresses do not match, then the sigal "channel sampling through the control signal issuing unit} 1al 1 enters the output control lines 17 as the signal" from the device sample.

According to the "channel sampling" signal in the control unit 1, a "device operation that indicates a drop" signal is generated} that the selected device is connected. Then from the block of address 11 through the block of information output 2 is given its own address, and from the block issuing control signals a 1-signal device address.

The channel compares the given normal address and, if they are equal, the address byte from the input information pnp 16 n gives the input control pits 15 sigtal control. The command byte) is checked for the parity in the control circuit. 12, decoded and zanomipatsya in the register kompap 10, with 5TOM prizapak received command is issued in block 6.

By the signal "control kapala, the byte of its own address is removed, the signal" the address of the device is reset,

From the state indication block 8 bytes of state, and on the output control slots 17, a signal for "device control" is set.

If the received command does not require damages, then the I / O device will receive the final byte of the status with the idiom "channel coichil" (the sign "device coichil o may also be signaled).

If, however, a commanding commander requires the transmission of dyne ones, then usually a zero byte of status is issued. Having received a status byte, the channel lowers the command byte from the input spike 16, resets the channel control signal and sets the channel information signal to the input control 15.

Therefore, the signal} is removed from the weekend

information bus 18, the initial status byte and the block of adjustable calls 7 is triggered. If the I / O control device is operating in monoiol mode, the signal "device operation is not removed until the end of the data transfer. In multiplex mode, the signal is reset after the initial sample and set again for the transmission time of each data byte. In multiplex mode, data transfer begins with stapling communication with caial. On the channel on the output of the controllers of the M 17, a "device requirement" signal is output.

On this signal, the channel but the input control unit Yun-1m bus 15 issues a signal “channel sampling, butting into the likeness unit} 6 and the control signal output unit 1, which generates the signals“ device operation ”to the device address.

These signals are output on the output} of the governing 17, and on the output press 18 of the address 11 block is given its own address. The "device request" signal is cleared. In response to

The signals "device operation and" device address; the channel resets the sigal "sampling drop; it sends out a signal" channel adjustment to the input control buses 15, which means in the sequence "to continue." This signal removes its own address, resets the signal "address of the device, and generates a signal" of the device information output to the output control buses 17. Previously

} the data byte 1x1 is terminated on the output informa- tion 1np 18, if the I / O control unit received in the process an initial 1 select read input command. When outputting (indiscriminately) the signal “device information” means that the device-control device is ready to receive the data byte.

.t resets the signal “Capacity Capture,” and it triggers to service the request.

Kapal installs on the input control signals 15 a channel information signal. When reading this, it means that the channel is a single data byte, and when it is underused, the channel has set a data byte.

The I / O control device, having received a "channel information" signal, resets the "device information," device operation, issues a data byte when reading, or receives a data byte when writing. The channel resets the channel information signal.

This sequence is repeated, but for each request of the I / O control unit, the transmission of data transmission units.

If the I / O control device operates in exclusive mode, the data transfer is performed using the signals "device information and" information dripping, as described above, excluding the sequence of sampling signals from the input / output control device, i.e., starting directly with the installation signal information device and on.

Subject invention

An I / O control unit containing information and control sigpals, information and control and receive control registers, control unit, command, data and status registers, address block, control and sampling circuits, the information and control inputs of the device are connected with the inputs of the information receiving registers and control signals, the outputs of the control unit are connected to the inputs of the sampling circuit, the issuing units ipformatsin and UnraV: -1/1 (), which are characterized by. that, in order to expand functionality and increase reliability, it additionally contains a block of adjustable requests, a state indication block and a block of control modes, the output of the control signal receiving register is connected to the inputs of the address block, the sampling circuit, the control output block; 0 signals, the command register and the control unit, and the output of the information reception register is connected to the inputs of the command register, the address block and the control circuit, the output of which is connected to the command register and the address block, the outputs of the control block connects to the inputs of the state indication unit, the coptjg unit, the role of the modes, the inputs / outputs of the control unit are connected respectively to the regulated alarm unit and the data register, the output of which is connected to the input of the information output unit; the inputs of the control unit Q are connected to the outputs of the command register, the sampling circuit, the control signal output unit and the address block, the output of which is also connected to the input of the information output unit; the output of the mode control unit is connected to the inputs of the control output unit for their signals, the sampling circuit, and the output unit; the output of the control signal output unit is connected to the inputs of the information output unit n of the state indication unit, one output of which is connected to the input of the information output unit, and the second output is connected to the status register, the output of which is connected to the input of the G1 unit | 1 tasks for information. five