JPS62196863A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62196863A JPS62196863A JP3870086A JP3870086A JPS62196863A JP S62196863 A JPS62196863 A JP S62196863A JP 3870086 A JP3870086 A JP 3870086A JP 3870086 A JP3870086 A JP 3870086A JP S62196863 A JPS62196863 A JP S62196863A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuit section
- output
- section
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 230000004044 response Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 2
- 230000002159 abnormal effect Effects 0.000 abstract 1
- 238000007689 inspection Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000002950 deficient Effects 0.000 description 3
- 238000003745 diagnosis Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体集積回路の回路構成に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit configuration of a semiconductor integrated circuit.
[従来の技術]
従来この種の半導体集積回路は電子回路パッケージ上に
実装されて使用されるが、その内の一つでも故障した場
合にはその影響は大きく、はとんどの場合はシステムダ
ウンにつながるため、必要以上の信頼性が要求される場
合が多い。また、その故障診断も高額な設備と高度に熟
練した検査員を使用しても多大な工数が必要となってい
た。[Prior art] Conventionally, this type of semiconductor integrated circuit is used mounted on an electronic circuit package, but if even one of them breaks down, the impact is significant, and in most cases, the system will go down. In many cases, reliability is required to be higher than necessary. Moreover, the failure diagnosis requires a large amount of man-hours even if expensive equipment and highly skilled inspectors are used.
[発明が解決しようとする問題点]
従来の半導体集積回路(LSI)が多数、プリント基板
上に実装されて、いわゆる電子回路パッケージが構成さ
れた場合、一つのLSIの故障により装置全体がシステ
ムダウンし、故障診断に多大の工数を要するために、復
旧までの時間が長く、またその回数も多いこと、更に中
間検査工程で必るパッケージ検査において該当パッケー
ジを完全に検査するためには工数的にも検査技術的にも
不可能な状況に近くなって来ていること等を改善する必
要があった。[Problems to be solved by the invention] When a large number of conventional semiconductor integrated circuits (LSI) are mounted on a printed circuit board to form a so-called electronic circuit package, a failure of one LSI can cause the entire device to system down. However, since failure diagnosis requires a large amount of man-hours, it takes a long time to recover, and the number of tests is large.Furthermore, it takes a lot of man-hours to completely inspect the package in the package inspection that is required in the intermediate inspection process. It was necessary to improve the situation, which was becoming close to impossible in terms of inspection technology.
本発明の目的は回路自体に自己判断機能を与えることに
より、故障によるシステムダウンに対ずる迅速な対処を
可能ならしめた半導体集積回路を提供することにおる。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit in which a self-judgment function is provided to the circuit itself, thereby making it possible to quickly deal with a system failure due to a failure.
[問題点を解決するための手段]
本発明は回路部と、入出力端子部と、前記回路部と出力
端子部との間の導通路を開閉し、動作状態が良の場合に
前記回路部と出力端子部とを単純に接続し、否の場合に
前記回路部と出力端子部との導通路を開放して全出力端
子をハイインピーダンスとする端子切換回路部と、前記
回路部への入力信号とそれに応答する前記回路部の出力
信号の両方を予め自己の内部に蓄積されている結果と比
較してその結果によって端子切換回路部への信号を決定
する判断回路部とを1つの半導体チップ内に有すること
を特徴とする半導体集積回路である。[Means for Solving the Problems] The present invention opens and closes a conductive path between a circuit section, an input/output terminal section, and the circuit section and the output terminal section, and when the operating state is good, the circuit section and an output terminal section, and in the case of no connection, a conduction path between the circuit section and the output terminal section is opened to make all output terminals high impedance, and an input to the circuit section. A judgment circuit unit that compares both the signal and the output signal of the circuit unit in response to the signal with a result stored in the circuit in advance, and determines the signal to be sent to the terminal switching circuit unit based on the result. This is a semiconductor integrated circuit characterized in that it has a semiconductor integrated circuit.
[実施例] 次に本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
本発明1は回路部2と、端子切換回路部3と、入出力端
子部A、Bと、判断回路部4と、判断回路部4の結果を
外部に知らせる出力端子Cとで構成される。The present invention 1 is composed of a circuit section 2, a terminal switching circuit section 3, input/output terminal sections A and B, a judgment circuit section 4, and an output terminal C that notifies the result of the judgment circuit section 4 to the outside.
端子切換回路部3は実際は半導体素子で構成されている
が、ここでは簡明化のために単なるスイッチの形で示す
(実際は複数個存在する)。Although the terminal switching circuit section 3 is actually composed of a semiconductor element, it is shown here in the form of a simple switch for the sake of simplicity (actually, there are a plurality of them).
また5は入出力端子部Aに印加された信号(複数本)を
回路部2と判断回路部4へ印加するための導通路である
。6は回路部2より出力された信号(複数本)を判断回
路部4と端子切換回路部3へ印加するための導通路であ
り、7は端子切換回路部3より出力された信号(複数本
)を出力端子部Bに印加するための導通路である。Further, reference numeral 5 denotes a conductive path for applying the signals (a plurality of signals) applied to the input/output terminal section A to the circuit section 2 and the judgment circuit section 4. 6 is a conductive path for applying the signals (multiple signals) output from the circuit section 2 to the judgment circuit section 4 and the terminal switching circuit section 3; 7 is a conductive path for applying the signals (multiple signals) output from the terminal switching circuit section 3; ) is applied to the output terminal portion B.
第1図において、通常入力端子部Aに外部より信号が印
加されると、その信号は導通路5を通して回路部2と判
断回路部4へ伝達される。回路部2ではそれに応じた出
力信号を導通路6に通して出力する。この時、判断世路
部4では回路部2に対する入力信号と出力信号を導通路
5と6を通してモニタし、回路部2の動作が正しく動い
ているかどうかを監視する。判断回路部4は通常マイク
ロコンピュータ−やメモリー等で構成されており、その
メモリー内部には、あらかじめ回路部2の使用される上
でのあらゆる入力信号とそれに対する正しい出力信号が
格納されているため、導通路5の入力に対する正しい出
力信号を格納されているメモリーより選び出し、それと
導通路6の入力に対する値とを比較することによって良
否の判断を行う。その結果が良であれば、導通路8を通
して端子切換回路部3へ閉の信号を出し、また同時に導
通路9を通して外部出力端子Cにも良の信号を出す。結
果が否であればそれぞれ間と否の信号を導通路8,9に
通して出力する。端子切換回路部3は導通路6を通して
出力される回路部2の出力信号を導通路8の信号によっ
てそのまま導通路7に結線したり、ハイインピーダンス
にしたりする機能を持った回路である。In FIG. 1, when a signal is normally applied to the input terminal section A from the outside, the signal is transmitted to the circuit section 2 and the judgment circuit section 4 through the conductive path 5. The circuit section 2 outputs a corresponding output signal through the conduction path 6. At this time, the judgment circuit section 4 monitors the input signal and output signal to the circuit section 2 through the conductive paths 5 and 6 to monitor whether the circuit section 2 is operating correctly. The judgment circuit section 4 is usually composed of a microcomputer, a memory, etc., and all input signals and correct output signals corresponding to the input signals when the circuit section 2 is used are stored in advance in the memory. The correct output signal for the input of the conductive path 5 is selected from the stored memory, and the quality is determined by comparing it with the value for the input of the conductive path 6. If the result is good, a close signal is sent to the terminal switching circuit section 3 through the conduction path 8, and at the same time, a good signal is sent to the external output terminal C through the conduction path 9. If the result is negative, signals indicating the difference and failure are outputted through the conductive paths 8 and 9, respectively. The terminal switching circuit section 3 is a circuit that has the function of directly connecting the output signal of the circuit section 2 outputted through the conduction path 6 to the conduction path 7 according to the signal of the conduction path 8, or making it high impedance.
第1図の状態は回路部2が正しく動作している時の状況
を示した図であり、導通路8の信号によって端子切換回
路部3が動作して導通路6と7が接続され、回路部2の
出力が直接Cに出力されている状態を示すものである。The state shown in FIG. 1 is a diagram showing the situation when the circuit section 2 is operating correctly, and the terminal switching circuit section 3 is operated by the signal of the conduction path 8, the conduction paths 6 and 7 are connected, and the circuit This shows a state in which the output of section 2 is directly output to C.
第2図の状態は回路部2が誤動作している時の状況を示
した図であり、導通路8の信号によって端子切換回路部
3が動作し、導通路6と7が切断されてBは仝てハイイ
ンピーダンスとなり、Cには否の信号が出力されている
状態を示すものでおる。The state shown in FIG. 2 is a diagram showing a situation when the circuit section 2 is malfunctioning, and the terminal switching circuit section 3 is operated by the signal from the conduction path 8, and the conduction paths 6 and 7 are disconnected. This indicates a state in which the impedance becomes high and a negative signal is output to C.
第3諷はこの様な半導体集積回路(LSI)が複数個回
路基板上に実装されて、あるアルゴリズムを有する電子
回路パッケージ1を構成した場合を示す図である。図中
A、Bは入出力端子部、20〜27は本発明のLSI
、 30〜37は図1又は2のCで示される出力端子で
ある。また本図は簡明化のために実際の入出力信号線は
省略しである。第3図において記@Cで示される様なA
ND回路を構成し、その出力40を出力端子部Bに出し
ておけば、この電子回路パッケージ1が正しく動作して
いるかどうかの監視作業は40の信号線をBを通してシ
ステム側よりモニターすることによって可能である。こ
の様な電子回路パッケージが複数枚使用されているとし
ても、上述の方法により、どのパッケージが不良である
か即時にシステム側で判断できシステムダウンの時間が
大幅に短縮される。The third example is a diagram showing a case where a plurality of such semiconductor integrated circuits (LSI) are mounted on a circuit board to configure an electronic circuit package 1 having a certain algorithm. In the figure, A and B are input/output terminal parts, and 20 to 27 are LSIs of the present invention.
, 30 to 37 are output terminals indicated by C in FIG. 1 or 2. Further, in this figure, actual input/output signal lines are omitted for simplicity. A as shown by mark @C in Figure 3.
If an ND circuit is configured and its output 40 is sent to the output terminal section B, monitoring whether this electronic circuit package 1 is operating correctly can be done by monitoring the signal line 40 from the system side through B. It is possible. Even if a plurality of such electronic circuit packages are used, the above-described method allows the system to immediately determine which package is defective, thereby greatly reducing system downtime.
また中間検査工程でおるパッケージ検査においても、各
LSIの内部に判断回路が内蔵されているために、過去
の様にその電子回路パッケージのアルゴリズムの全てを
チェックする様な膨大なテストパターンを印加する必要
がなく、非常に短い基本的なパターンのみを印加して第
3図の出力40のみを監視すればよく、またあるLSI
が不良である場合にはCの入力である端子30〜37の
信号のみのチェックにて不良ICが即座に判明する。Also, during package inspection, which is an intermediate inspection process, since each LSI has a built-in judgment circuit, a huge number of test patterns are applied to check all the algorithms of the electronic circuit package, as in the past. It is not necessary to apply only a very short basic pattern and monitor only the output 40 in FIG.
If the IC is defective, the defective IC can be immediately identified by checking only the signals of terminals 30 to 37, which are the inputs of C.
この様な考え方でパッケージ検査を行えば、パッケージ
検査では主として製造不良の検出のみを目的とした検査
設備のみでよく、設備費や検査員の大幅な低減が可能で
ある。If package inspection is performed based on this concept, package inspection requires only inspection equipment mainly for the purpose of detecting manufacturing defects, and it is possible to significantly reduce equipment costs and the number of inspectors.
[発明の効果]
以上説明した様に本発明は、半導体集積回路の内部に判
断回路部を内蔵させることにより、装置レベルでのシス
テムダウン時間の短縮及びパッケージ検査で最大のネッ
クとなっている検査方式。[Effects of the Invention] As explained above, the present invention reduces system down time at the equipment level and improves inspection, which is the biggest bottleneck in package inspection, by incorporating a judgment circuit inside a semiconductor integrated circuit. method.
検査設備の簡明化、低価格化及び故障診断修理の短縮化
等、従来方法よりもより簡単に、より確実に実行できる
効果がある。This method has the effect of simplifying inspection equipment, reducing costs, and shortening failure diagnosis and repair, which can be performed more easily and reliably than conventional methods.
第1図は本発明の一実施例を示すブロック図、第2図は
回路部が誤動作をして全出力端子がハイインピーダンス
となっている状態を示す図、第3図は第1図に示す実施
例が複数個回路基板上に搭載された状態を示す図である
。
1:本発明の半導体集積回路
A:入力端子部 B:出力端子部2:回路部
、3=端子切換回路部4:判断回路部
5.6,7.8,9:導通路Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a diagram showing a state in which the circuit section malfunctions and all output terminals are in high impedance, and Figure 3 is the same as Figure 1. FIG. 3 is a diagram showing a state in which a plurality of embodiments are mounted on a circuit board. 1: Semiconductor integrated circuit of the present invention A: Input terminal section B: Output terminal section 2: Circuit section
, 3 = terminal switching circuit section 4: judgment circuit section 5.6, 7.8, 9: conduction path
Claims (1)
子部との間の導通路を開閉し、動作状態が良の場合に前
記回路部と出力端子部とを単純に接続し、否の場合に前
記回路部と出力端子部との導通路を開放して全出力端子
をハイインピーダンスとする端子切換回路部と、前記回
路部への入力信号とそれに応答する前記回路部の出力信
号の両方を予め自己の内部に蓄積されている結果と比較
してその結果によつて端子切換回路部への信号を決定す
る判断回路部とを1つの半導体チップ内に有することを
特徴とする半導体集積回路。(1) Open and close the conductive path between the circuit section, the input/output terminal section, and the circuit section and the output terminal section, and simply connect the circuit section and the output terminal section when the operating condition is good. , a terminal switching circuit section that opens the conduction path between the circuit section and the output terminal section and makes all output terminals high impedance when the input signal is input to the circuit section and the output of the circuit section in response to the input signal. A single semiconductor chip is characterized by having a determination circuit section that compares both signals with results stored in the device in advance and determines the signal to be sent to the terminal switching circuit section based on the results. Semiconductor integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3870086A JPS62196863A (en) | 1986-02-24 | 1986-02-24 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3870086A JPS62196863A (en) | 1986-02-24 | 1986-02-24 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62196863A true JPS62196863A (en) | 1987-08-31 |
Family
ID=12532588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3870086A Pending JPS62196863A (en) | 1986-02-24 | 1986-02-24 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62196863A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015149572A (en) * | 2014-02-05 | 2015-08-20 | 京セラドキュメントソリューションズ株式会社 | application specific integrated circuit |
-
1986
- 1986-02-24 JP JP3870086A patent/JPS62196863A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015149572A (en) * | 2014-02-05 | 2015-08-20 | 京セラドキュメントソリューションズ株式会社 | application specific integrated circuit |
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