JPS62193412A - Signal generating circuit - Google Patents

Abstract

PURPOSE:To switch an output frequency at a high speed in response to the change in a frequency division ratio without sacrifycing the resolution by providing an integration circuit and a sample-and-hold circuit, leading a signal from a phase detector and providing a period averaging circuit giving a control signal being the result of the conversion of the signal from the phase detector into a DC signal to a VCO. CONSTITUTION:The titled circuit is provided with the period averaging circuit 40 consisting of an integration circuit 20 and a sample-and-hold circuit 30, leading a signal from a phase detector, converting the said signal into a DC signal as a control signal S0, and giving the signal to a VCO (voltage controlled oscillator). The period averaging circuit 40 uses a parallel circiut comprising a resistor 10 and a capacitor 11 to receive an output signal s3 of the phase detector 3 and leads the said signal to the integration circuit 20 of th next stage. The integration circuit 30 consists of, e.g., an integration capacitor 13, an amplifier 12 and a feedback resistor 18 between an input terminal of the integration circuit and an output terminal of the sample-and-hold circuit 30 explained later.

Description

[Detailed Description of the Invention] A. “Object of the Invention” [Field of Industrial Application] The present invention is based on PLL (phase 1 locked
This invention relates to improving the responsiveness of an output signal in a signal generation circuit using a 1oop).

[Conventional technology]

FIG. 4 shows a conventional signal generation circuit using a PLL. V
CO (Voltaoe Controlled OS)
The oscillator 5 is an oscillation circuit whose frequency changes continuously within a certain range according to the applied control signal sO. This VCO 5 oscillates at a frequency corresponding to the voltage of the applied control signal @SO. Then, output signal S4 of CO5 is divided by N by frequency divider 2 to generate signal S2,
This signal S2 is applied to one input terminal of the phase detector 3.

In this state, when the reference frequency signal (hereinafter referred to as reference signal) Sr is frequency-divided by M by the frequency divider 1 and applied to the other end of the phase detection PS3, a signal S1 based on the frequency of the signal s2 and the reference signal sr is generated. An error voltage signal S3 is generated depending on the frequency difference or phase difference. The loop filter 4 has, for example, a configuration as shown in FIGS. 5(a) to (C),
This error voltage signal s3 is introduced and a smoothed level control signal SO is fed back to CO5.

Here, it is assumed that, for example, in order for the VCO 5 to output the frequency fa, it is necessary to set the voltage of the control signal SO to Ea. If CO5 is currently oscillating at frequency Ib, to change it to frequency /a, use a setting signal (not shown).
is added to the frequency divider 2, and the frequency division ratio N is set to Nb-1Na. Of course, the frequency of the VCO 5 can also be changed by changing the frequency division ratio M of the frequency divider 1, but in this specification, in order to make the operation easier to understand, the case where only the frequency division ratio N of the frequency divider 2 is changed I will explain the following.

By changing the frequency division ratio to Nb-4N, the signal S2
, the phase of which immediately changes, and therefore the output signal s3 of the phase detector 3 and the control signal sO also change. As a result, VCO5
The frequency of P also changes, and this returns to frequency divider 2, so P
The entire loop of the LL circuit changes.

In the signal generation circuit shown in FIG. 4, the polarities and constants of each component (VCO 5, phase detector 3, loop filter 4, etc.) are selected so that the operation is as follows. The operation is that the frequency of the VCO 5 changes rapidly, and as a result, the signals s1 and s2 have the same frequency, and the phase difference between the two signals sl and s2 becomes the same value. This is an operation in which the output frequency becomes fa when the control signal 5O=Ea.

Then, when the control signal sO=E a and the output frequency/a are reached, the PLL is locked and the system is stabilized. Therefore,
f+-7r/M-I2-/a/N
becomes.

Here, fl is the frequency of the signal s1, fr is the frequency of the signal sr, I2 is the frequency of the signal S2, and I4 is the frequency of the signal S4. A desired frequency can be extracted from the VCO 5 by appropriately switching the frequency division ratios M and N using a setting signal.

[Problem that the invention seeks to solve]

However, the above conventional means have the following problems.

In order to change the frequency of the signal generating circuit, the setting signal r applied to the frequency divider 1.2 is changed by changing the dividing ratios M and N, as described above.

However, since the signal generating circuit shown in FIG. 4 has a time delay element of the loop filter 4, even if the division ratios M and N are changed by the setting signal, the signal of the desired frequency can be transmitted to the VCO 5.
There will be a considerable time delay until the output is output. In the applicant's implementation circuit, it took several tens of times the period Ts (=M/fr) of the signal S1 (signal on the reference signal sr side of the phase detector 30).

Furthermore, since the time delay becomes noticeable, M cannot be increased, and as a result, there is a problem that the resolution of the output frequency f4 cannot be increased.

An object of the present invention is to provide a signal generation circuit that can switch the output frequency at high speed according to changes in the frequency division ratios M and N without sacrificing resolution.

``Structure of the Invention'' [Means for Solving the Problems] In order to solve the above problems, the present invention uses a VCO, a signal based on the output (s4) of this VCO, and Standard No. 18 (s4).
a phase detector for detecting a phase difference with a signal based on r);
The PLL circuit is composed of an integrating circuit (20) and a sample-hold circuit (30), which introduces the signal from the phase detector, converts it into a DC signal, and outputs a control signal (s0) to the VCO. It is equipped with an interval averaging circuit.

(Example〕 Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the same figure, 1.2 is a frequency divider, 3 is a phase detector, and 5 is a frequency divider.
is a VCO and has the same function as that explained in FIG.

The difference between FIG. 1 and FIG. 4 is that the loop filter 4 in FIG. 4 has a specific configuration (so-called section averaging circuit 40).
This has resulted in a significant effect.

To describe an example of the configuration of the new loop filter, that is, the section averaging circuit 40, a parallel circuit of a resistor 10 and a capacitor 11 receives the output signal s3 of the phase detector 3, and sends this signal to the next-stage integrating circuit 20. Introduce. The integrating circuit 20 includes, for example, an integrating capacitor 13, an amplifier 12, and a feedback resistor 18 connected between the output terminal of a sample and hold circuit 130, which will be described later, and the input terminal of this integrating circuit.

The output of this integrating circuit 20 is introduced into a sample hold circuit 30 at the next stage. This sample hold circuit 30 is
For example, it is composed of a switch 14 that turns on and off the signal from the integrating circuit 20, an amplifier 17 that receives the signal from this switch 14, and a hold capacitor 15 connected between the input terminal of this amplifier 11 and the circuit ground. .

Before explaining the operation of the (n-th generation circuit) shown in FIG. 1, which is configured as shown in FIG. Nikkei Electronics, 1973.9-24 issue 84~
It is described in detail on page 104. In particular, according to the description in lines 9 to 12 on the left side of page 88, Aτ/′c+
It is stated that if the circuit constants are determined to satisfy the regulation that R+ = 1, the output of the interval averaging circuit will catch up with the fluctuations of the input signal with the second 1 numbering pulse, and a stable output can be obtained. ing. Note that A is the gain of the amplifier 17, τ is the scramble period, C1 is the capacitance 1 fl of the integrating capacitor 13, and R+ is the feedback resistor 18.
is the resistance value of

The operation of the interval averaging circuit 40 will be explained using FIG.
As in (1), when 910 + τ, 2τ, ..., A5
sample pulse is generated. In synchronization with this, the first
Switch 14 in the figure is instantaneous (phono, integrating circuit 2
It operates to read a voltage of 0 into the hold capacitor 15. Assume that in this state, at time τ0, the input S3 of the section averaging circuit 40 suddenly changes from, for example, Qv to E as shown in FIG. 2 (lit).

Therefore, the integrating circuit 20 integrates the voltage E from the time τQ. b) R2 is the resistance value of the resistor 10.

Due to the sample pulse at time τ, the output SO of the interval averaging circuit becomes the above voltage, and furthermore, at the second ripple pulse, that is, at time 2τ, the output SO of the interval averaging circuit becomes
becomes -&·E and becomes stable.

z As described above, the operation of the entire apparatus in FIG. 1 will be explained assuming that the interval averaging circuit 40 has the speed to catch up with the change in the input signal in the second sample pulse.Of course, The present invention can be implemented even if the speed of the section averaging circuit is other than this. Fig. 3 is a time chart of the signals of each part of the first section. The following explanation will be given with reference to this figure. Note that the frequency division The explanation will be given assuming that the frequency division ratio M of the device 1 is not changed.

The phase detector 3 receives signals S1 and (11) shown in FIG.
) is applied, and the PLL circuit is in a locked state. Therefore, the signals S1 and 52 have the same frequency, and the phase difference between the signals S1 and S52 is as shown in FIG.
The pulse width p1 is as follows. The phase detector 3 in FIG. 1 opens the gate and sends a pulse of (ill) (q
I'm here. And since the PLL is locked, this (
The signal S3 is repeatedly output with a pulse width p1 shown in Ill). Therefore, the output pressure of the section averaging circuit 40 which introduces the plane signal S3 and converts it into a DC voltage is a constant value υ!
It is. For example, it is assumed that the sample pulse is generated in synchronization with the rising edge of the signal S1.

In this state, the setting signal (not shown) of the frequency divider 2 changes at time T1, and the frequency division ratio changes from N1 to N2 (for example, Nl
<N2). In this case, it is assumed that setting Nl-lN2 means increasing the frequency of the VCO 5.

At time T1 when the frequency division ratio N is changed, the VC
The frequency of O5 remains the same as before, and the frequency division ratio N of the period of No. 13 S2 has become larger, so the time t2 of (!+) is
It spreads compared to time t1 (tl<t2). In addition, time t
1 is the period of the signal S2 in the locked state.

In this way, during the period shown in (11) (■) in FIG. 3, the signal S
Since the period of 2 is t2, the phase difference between the signals S1 and 32 during this period 3 is the pulse width p2 shown by (iif).

This pulse width p2 is wider than the phase difference p1 in the locked state before time T1 (pl<p2). Therefore, the output SO of the interval averaging circuit 40 increases to v2 as shown by M due to the sample pulse a.

When the output of the interval averaging circuit, that is, the voltage of the control signal SO of the VCO5 increases, vC○5 increases the output frequency f4, so the period of the signal S2 in (11) becomes t3 (t3<
tl<t2>. Therefore, the signal S1 in the period ■
The phase difference between and 82 becomes a pulse width p3 shown by (R1).

This pulse width p3 is narrower than the phase difference p2 of ■ (pl
<13<p2). Therefore, due to the sample pulse b, the output sO of the interval averaging circuit 40 becomes υ3 as shown in (V).
increases to

Here, to explain the reason why the voltage of the output sO of the interval averaging circuit 40 increased even though the pulse width of the signal @S3 decreased from p2 to p3, as mentioned above, in this specification, the second This is because the response characteristic is such that it can catch up with changes in the input signal at the sample pulse time of .

However, in the case of period ■ in Fig. 3, the pulse width p2, which is the input signal of the section i1L equalization circuit, changes further in the second sample pulse b and becomes p3, which is narrower than p2, so the voltage The value of υ3 is low compared to the case where the pulse width p2 is repeatedly added.

In this way, the signal sO shown in FIG. 3 <V> increases from υ2 to v3 due to the sample pulse b, so the output frequency of vC05 becomes even higher than the period ■, so (11)
A': The period of @s2 (4 is smaller than the period of ■) (3 (t4<t3・tl<t2). Therefore, the phase difference between the signals s1 and s2 in the period ■ is as shown in Figure 3. , the width p4 is very small (p4<pl<p3< p
2). Therefore, due to the sample pulse C, the voltage of the signal sO decreases like M to v4. During this period (2), the frequency/4 of the VCO 5 becomes too high than the set value.

As described above, since the voltage of the control 11 signal sO has decreased to 04, the frequency of the VCO 5 has decreased and the period of the signal 32 (11) becomes t5. This t5 satisfies tl<t5 and tsx t2. The phase difference between the signals S1 and S2 during the period (3) has a width p5 as shown in FIG.

Since this p5 satisfies p4<p5 to p3, the voltage read by the sample pulse d slightly increases the VCO control signal sO to v5.

Therefore, the frequency of the VCO 5 increases slightly, and the period of the signal S2 in (11) becomes t6. This period is 6 to 10 seconds, and the PLL circuit enters the lock state. At this time, the signal S
The phase difference between 1 and 52 results in the (III) pulse p6.

After that, due to the sample pulse e, the voltage of the control signal SO of vcO5 increases very slightly to v6.
0), the PLL circuit is completely locked. At this time, the period of signal S2 is t7-tl,
The phase difference between the signals S1 and 52 is the pulse width p1. In addition,
Since pl<p7 and as a result, υ1 and υ6, the frequency output from the VCO 5 has an increased value.

The above explanation is an example of the operation when increasing the frequency of the VCO 5, but since the operation is the same when decreasing the frequency, the explanation thereof will be omitted.

Regarding the period τ and timing of the sample pulse, if a digital phase detector is used as the phase detector 3, if the input signal is constant, the period Tc of the input signal S1 (see Fig. 3 (1)) Since the output is repeated every time, if τ-Tc is used, synchronization can be achieved and the speed can be increased.

In addition, when an analog type (n-type) phase detector is used as the phase detector 3, the duty ratio of the input signal is 1:1.
If so, the output is repeated every Tc/2, so τ-
It is preferable to set it to Tc/2. However, the duty ratio is 1=
If it is not 1, it is set to τ-Tc as described above.

Furthermore, if the period τ of the sample pulse is extremely shortened, it will respond sequentially to the pulse signal of the output S3 of the phase detector, which will actually impair the stability of the VCO 5. Moreover, if the period τ is set very well, the advantage of the present invention is that
The characteristic of responsiveness is lost.

In addition, when changing the frequency division ratio M or the value R1 of the S feedback resistor 18, it is necessary to change A, CI, or R+ in order to satisfy the above-mentioned sample pulse conditions and the immediate response conditions Aτ-C1 and R1 of the interval averaging circuit. There is. FIG. 6 is an example of switching Δ, and FIG. 7 is an example of switching R1.

Further, in FIG. 1, the effect of the capacitor 11 connected in parallel to the resistor 10 will be described. If the capacitance of this capacitor is 02 and the capacitance is set to C2·R2-τ, phase compensation can be performed. That is, it has the effect of tracking the input signal well (no phase delay).

In addition, although the example above has been explained in which the frequency division ratio N of the frequency divider 2 is changed, the above-mentioned operation can also be used when the frequency division ratio M of the frequency divider 1 is changed to extract the output frequency. Since they are similar, their explanation has been omitted.

C. "Effects of the Present Invention" As described above, according to the present invention, the following effects can be obtained.

When switching the frequency division ratios M and N, a desired frequency can be output immediately. Furthermore, by setting the period of the sample pulse to τ-Tc or Tc/2, it is synchronized with the phase detector and the response speed is further increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a signal generating circuit according to the present invention, FIG. 2 is a time chart showing the operation of the section averaging circuit, FIG. 3 is a time chart of signals of each part of the first section, and FIG. is a diagram showing an example of the configuration of a conventional signal generation circuit, FIG. 5 is a diagram showing an example of the configuration of a conventional loop filter, and FIGS.
The figure shows an example of the configuration of the peripheral circuit of the amplifier 17 when the frequency division L and the feedback resistor 18 are changed by [;7J. 1.2... Frequency divider, 3... Phase detector, 5... V
C.O. 20...Integrator circuit, 3o...Sample hold circuit, 4o...Interval average circuit. Figure 4! Figure 5 (a) (b) (C) Figure 6 Figure 7/'7

Claims (1)

[Claims] In a PLL circuit including a VCO and a phase detector that detects a phase difference between a signal based on the output (s4) of the VCO and a signal based on the reference signal (sr), an integrating circuit ( 20) and a sample-and-hold circuit (30), and includes an interval averaging circuit (40) that introduces the signal from the phase detector, converts it into a DC signal, and outputs a control signal (s0) to the VCO. signal generation circuit.