JPH0787363B2 - Phase locked loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a multiplier circuit of a digital communication device,
The present invention relates to a phase-locked loop circuit (hereinafter referred to as a PLL circuit) for converting an input clock signal into an N-fold frequency signal.

(Conventional Technology) Conventionally, as a technology in such a field, for example, "Radio Shack Dictionary of Electronics (Radi Shack Dictionary of Electronics)" edited by Rudolf f.graf.
o Shack DICTIONARY OF electronicf) "(1978)
(US) It was also described on P.524.

Fig. 2 shows a conventional integrated circuit (hereinafter referred to as IC).
It is a figure which shows one structural example of a PLL circuit.

This PLL circuit has an input terminal 1 for an input signal F _i and an output signal F _i .
_It has an output terminal 2 for _o , and between its input and output terminals 1 and 2,
Phase comparator 3 composed of exclusive OR gates (hereinafter referred to as ExOR), loop filter which is a low-pass filter
A voltage-controlled oscillator (hereinafter, referred to as VCO) 20 is connected. A reference voltage generation circuit 4 for generating a reference voltage Vr is connected to the loop filter 10. Further, the output side of the VCO20 is 1 for the feedback signal F _r output
It is feedback-connected to the phase comparator 3 via the / N frequency divider 21. The loop filter 10 outputs its output voltage V _c to VC
It is a circuit that supplies to O20, and includes a differential amplifier 11, resistors 12 and 13
And a capacity of 14.

In the above configuration, when the input signal F _i is supplied to the input terminal 1, the phase comparator 3 divides the output signal F _{o of the} VCO 20 by 1 / N by the 1 / N frequency divider 21 to obtain a feedback signal F _r. And the input signal F
A phase difference φ _d with _i is obtained, and a pulse corresponding to the phase difference φ _d is output. The output pulse waveforms of the phase comparator 3 when the phase difference φ _d is 0 °, 90 °, 180 ° and 270 ° are shown in FIGS. 3 (a), (b), (c) and (d).

The output pulse of the phase comparator 3 is output from the loop filter 10 by
The DC component of the signal is extracted. FIG. 4 shows a relationship diagram of the output voltage V _c of the loop filter 10 with respect to the phase difference φ _d between the input signal F _i and the feedback signal F _r .

The VCO 20 inputs the output voltage V _c and outputs an output signal F _o having a frequency proportional to the output voltage V _c to the output terminal 2 and the 1 / N frequency divider 21. Then, the 1 / N frequency divider 21 frequency-divides the output signal F _o by 1 / N to generate the feedback signal F _r , and supplies the field back signal F _r to the phase comparator 3.

Here, the phase difference φ between the input signal F _i and the feedback signal F _r
Consider the case where _d is -90 ° <φ _d <90 °. At this time, the reference voltage V _r output from the reference voltage generation circuit 4 is in a high band when the output pulse of the phase comparator 3 is V _oh when the logic pulse is “1” and V _ol when the logic pulse is “0”. V _oh and V
midpoint voltage of _ol , that is, Set to. In this case, the DC component V _i of the output pulse of the phase comparator 3 becomes lower than the reference voltage V _r , and the loop filter
The output voltage V _{c of} 10 rises. As a result, the frequency of the output signal F _o of the VCO 20 becomes higher, and the phase difference φ _d moves in the direction of 90 °.

Next, consider the case where the phase difference φ _d is 90 ° <φ _d <270 °. At this time, the DC component V _i of the output pulse of the phase comparator 3 becomes higher than the reference voltage V _r , and the output voltage of the loop filter 10
V _c drops. As a result, the frequency of the output signal F _o of the VCO 20 becomes low, and the phase difference φ _d moves in the direction of 90 °.

Thus, in the conventional PLL circuit, the phase difference φ _d is always 90
The output signal F _{o of the} VCO 20 is controlled as a result.
As a frequency of, a frequency output that is N times the frequency of the input signal F _i will be obtained.

(Problems to be Solved by the Invention) However, the PLL circuit having the above configuration has the following problems.

(1) The midpoint of the output voltage of the phase comparator 3, that is, (V _oh + V
_ol ) / 2 and the reference voltage V _r do not match, the control width of the output voltage V _c of the loop filter 10 is limited, so the PLL
The operating range of the circuit is narrowed, and moreover, the oscillation frequency of the VCO 20 shifts when there is no input signal F _i .

Therefore, in the conventional PLL circuit, when the system is in a steady state (lock state), it is necessary to adjust the reference voltage V _r so that the output DC level of the differential amplifier 11 is set to the midpoint voltage of the amplitude width. . However, because the constants of each element vary during the manufacturing process of the PLL circuit composed of ICs, the PL
There is a problem that the reference voltage Vr needs to be readjusted from the outside of the L circuit by using a variable resistor or the like, and the adjustment work becomes complicated.

(2) When the output frequency of the phase comparator 3 is high, the DC component V _{i of the} output pulse changes due to the difference between the fall time T _r and the fall time T _f of the output pulse of the phase comparator 3. The same problem as (1) occurs. That is, the loop filter
The control width of the output voltage V _c of 10 is limited, which causes the PLL
In addition to narrowing the operating range of the circuit, the oscillation frequency of the VCO 20 shifts when there is no input signal F _i .

The present invention solves, as problems that the above-described conventional art has, the point of deviation between the DC component V _i of the output voltage of the phase comparator 3 and the reference voltage V _r , and the complicated adjustment of the deviation,
Average voltage of reference voltage V _r in locked state (DC component)
Equal to the average voltage (DC component) V _i of the output voltage of the phase comparator, and the average voltage (DC component) V _i and the reference voltage V _r
PLL that prevents deviation from the average voltage (DC component) of the reference voltage, thereby eliminating the need to adjust the reference voltage V _r and enabling high-band operation
The purpose is to provide a circuit.

(Means for Solving the Problem) In order to solve the problem, the invention of claim 1 compares a phase of an input signal with a phase of a feedback signal in a PLL circuit, and outputs a first signal according to a result of the comparison. Signal of the first
A phase comparator for outputting a second signal from the second output node which is the opposite phase of the first signal, a reference node to which a reference voltage is applied, and the first signal Filter which differentially amplifies the voltage of the first voltage and the reference voltage and passes the low frequency component of the first signal, and a voltage controlled oscillator which outputs a third signal having a frequency according to the output of the loop filter. A frequency divider that divides the third signal and outputs the divided signal as the feedback signal; connected to the first output node, the second output node, and the reference node; It is a circuit that divides the difference between the voltage appearing at the first output node and the voltage appearing at the second output node into 1: 1 and outputs the divided voltage to the reference node.

In the invention of claim 2, the capacitor for smoothing the voltage appearing at the reference node is connected to the reference node of claim 1.

(Operation) According to the invention of claim 1, since the PLL circuit is configured as described above, when the input signal is input to the phase comparator, the phase of the input signal and the output from the frequency divider are output. The phase of the feedback signal is compared by the phase comparator, and complementary first and second signals corresponding to the comparison result are first and second.
Are output from the output nodes of. In the reference voltage generation circuit, the voltage difference between the first and second output nodes is divided into 1: 1 and the divided voltage (reference voltage) is output to the reference node. This reference voltage and the first output from the phase comparator
The voltage of the signal is differentially amplified by the loop filter and only the low frequency component of the first signal is output. Then, the oscillation frequency of the VCO changes according to the output of the loop filter, and the third signal corresponding to the oscillation frequency is output from the VCO. The third signal is frequency-divided by the frequency divider and fed back to the phase comparator as a feedback signal.

Here, the average voltage of the reference voltage on the reference node when the system is in the locked state is determined by the reference voltage generation circuit by the first signal itself indicating the phase comparison result and the second signal (that is, the amplitude of the first signal and the second signal). (Equal to the signal of the opposite phase) and the divided voltage, so that it is always equal to the average voltage of the first signal.

According to the second aspect of the present invention, the voltage on the reference node divided by the reference voltage generating circuit is smoothed and stabilized by the capacitor so that the direct current component thereof quickly matches the average voltage of the first signal. Operate. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a block diagram of a PLL circuit showing an embodiment of the present invention.

This PLL circuit is a circuit that consists of an IC and has an input signal F
_{It has} an input terminal 30 for _i and an output terminal 31 for an output signal F _o , and a phase comparator 40 is connected to the input terminal 30.
The phase comparator 30 is a circuit that outputs a pulse according to the phase difference φ _d between the input signal F _i and the feedback signal F _r, and is composed of a bipolar ExOR 41. ExoR41 is an input terminal 41a connected to the input terminal 30, a feedback signal F
It has an input terminal connected to _r , a positive-phase output terminal (first node) 41c, and a negative-phase output terminal (second node) 41d, and is referenced to the positive-phase output terminal 41c and the negative-phase output terminal 41d. The voltage generation circuit 50 and the loop filter 60 are connected.

The reference voltage generation circuit 50 is a circuit that generates a reference voltage V _r from the positive-phase output (first signal) and negative-phase output (second signal) of ExO41, and is connected to the negative-phase output terminal 41d of ExOR41. A first resistor 51 for generating a reference voltage and a second resistor 52 for generating a reference voltage connected to the positive phase output terminal 41c of the ExOR 41, and the first and second resistors 51, 52 thereof. _Are connected to the ground potential V _ss via a node (reference node) N1 and a smoothing capacitor (capacitor) 53. Here, the first and second resistors 5
The value of 1,52 does not affect the input of the loop filter 60 of the next stage, that is, the output impedance of the phase comparator 40 (for example, several hundreds) so that the output level of the phase comparator 40 does not decrease. Ω), for example, set to about 20 KΩ. The resistors 51 and 52 are formed of, for example, an impurity diffusion region formed on a semiconductor substrate or a polysilicon layer for electrodes. In order to stabilize the reference voltage V _r on the node N1, the capacitor 53 is set to, for example, about several tens pF and is formed of a MOS capacitor or the like.

The loop filter 60 is a circuit that differentially amplifies the positive phase output of the phase comparator 40 and the reference voltage V _r , removes the high frequency component of the positive phase output, and outputs the output voltage V _c. 61,
It is composed of resistors 62 and 63 and a capacitor 64. The negative-phase input terminal 61a of the differential amplifier 61 is connected to the positive-phase output terminal 41c of the ExOR 41 via the resistor 62, and the resistor 63 and the capacitor 64 are also connected.
Is connected to the output terminal 61c of the differential amplifier 61, and the positive phase input terminal 61b of the differential amplifier 61 is connected to the node N1.

The output terminal 61c of the differential amplifier 61 is output through the VCO 70 to the output terminal 31c.
The output terminal 31 is field-back connected to the input terminal 41b of the ExOR 41 via the 1 / N frequency divider 71. The VCO 70 is an oscillator whose oscillation frequency is controlled by the output voltage Vc of the loop filter 60, and the 1 / N frequency divider 71 frequency-divides the output signal (third signal) F _o of the VCO 70 by 1 / N and the feedback signal F _r. Is a circuit for generating.

FIG. 6 is a circuit diagram showing a configuration example of the ExOR 41 shown in FIG.

This ExOR41 is an ECL that uses a bipolar transistor.
(Emitter Coupled Logic). That is,
The ExOR 41 includes a first differential amplifier circuit including load resistors 81 and 82, transistors 83 and 84 and a constant current source 85, and a first differential amplifier circuit including the load resistors 81 and 82, transistors 86 and 87 and the constant current source 85. 2, a differential amplifier circuit, transistors 88 and 89 for switching the first and second differential amplifier circuits, and an output transistor 9
0, 91 and output constant current sources 92, 93. In FIG. 6, F _i is an input signal, F _r is a feedback signal, V ₀₁ and V ₀₂ are reference potentials, V _ss is a ground potential, and V _ee is a power supply potential of −5.2 V, for example.

In this ExOR41, when F _i > V ₀₁ , F _r <V ₀₂ , the transistor 8
8 is off, transistor 89 is on, transistor 86 is on, and transistor 87 is off. Therefore, the base voltage of the transistor 90 is low level (hereinafter referred to as “L”) and turned off, and the base voltage of the transistor 91 is high level (hereinafter referred to as “H”) and turned on, and the positive phase output terminal 41
c becomes "H" and the negative-phase output terminal 41d becomes "L". Similarly, F _i <V
_{Even when 01} , F _r > V ₀₂ , the positive phase output terminal 41c becomes “H” and the negative phase output terminal 41d becomes “L”. That is, when F _i ≠ F _r , the positive phase output terminal 41c becomes “H” and the negative phase output terminal 41d becomes “L”.

When F _i <V ₀₁ , F _r <V ₀₂ and F _i > V ₀₁ , F _r > V ₀₂ , the positive phase output terminal 41c is “L” and the negative phase output terminal 41d is “H”.
Becomes

The operation of the PLL circuit of FIG.
A description will be given with reference to FIGS.

In the following description, the output pulse waveform ExOR41, from the rising of the start point to V _oh from V _ol, the time from V _oh and the start of the falling edge of the V _ol, the period of the output pulse of ExOR41 T The case of 1/2 of will be described. This is when there is no input signal F _i to the PLL circuit and when the phase difference φ _d of the feedback signal F _r with respect to the input signal F _{i of the} ExOR41 is 90 °.
These correspond to the case where the operation of the PLL circuit is locked.

First, _let us consider a case where the output pulse of the ExOR 41 for finding the phase difference between the input signal F _i and the feedback signal F _r has a rise time T _r = fall time T _f = 0. The output pulse waveform of the ExOR 41 at this time is shown in FIG. In FIG. 5A, the solid line represents the positive phase output waveform at the positive phase output terminal 41c of the ExOR 41, and the broken line represents the negative phase output waveform at the negative phase output terminal 41d. ExOR41 in locked state
The positive-phase output waveform of is V _{ol for} the T / 2 time in the cycle T, and the rest
T / 2 hours have a voltage level of V _oh . Therefore, the DC component V of the positive phase output pulse output from the positive phase output terminal 41c
_i becomes (V _oh + V _ol ) / 2. In addition, the reverse phase output terminal 41d
The negative-phase output waveform output from is in a relationship opposite to the positive-phase output waveform, but its DC component is equal to V _i . Here, the resistance 51 and the resistance 52 in the reference voltage generating circuit 50 are set to 1: 1.
When the value is set to, the output reference voltage V _r of the reference voltage generation circuit 50 becomes the average value of each DC component of the positive phase output and the negative phase output.

Therefore, V _r = (V _oh + V _ol ) / 2, which coincides with the above V _i .

Next, consider the case where the rising time T _r and the falling time T _f are taken into consideration in the output pulse of the ExOR 41. ExOR 41 at this time
The output pulse waveform of is shown in FIG. 5 (b). Fig. 5 (b)
Therefore, the DC component V _i of the positive phase output pulse of ExOR41 can be expressed by the following equation.

From this equation, when T _r and T _f are considered, the above-mentioned T _r = T _f = 0
V _i is You can see that it only changes. Further, the negative-phase output waveform of ExOR41 is equal to the positive-phase output pulse delayed by T / 2 time, as is apparent from FIG. 5 (b). Therefore, since the DC components of the positive phase output and the DC component of the negative phase output are equal, the output reference voltage V _r of the reference voltage generation circuit 50 matches the DC component V _i of the positive phase output pulse.

As described above, when the rise time _Tr = fall time _Tf , the reference voltage _Vr is always at a constant level regardless of the state of the system. On the other hand, when the rise time T _r ≠ the fall time T _f ,
The reference voltage V _r changes at the rising and falling points of the signal regardless of the state of the system. However, the positive phase output terminal 41c
And the negative-phase output terminal 41d has a voltage difference between these output terminals 41d.
Although it changes according to the state of the voltage of c, 41d, since the resistance value of the resistors 51, 52 does not change, the voltage division ratio of the resistors 51, 52 to the voltage difference of the output terminals 41c, 41d is always 1: 1. become.

Based on such a reference voltage V _r , high frequency components are removed from the positive phase output pulse of the ExOR 41 by the low pass filter 60, and the oscillation frequency of the VCO 70 is controlled by the output voltage V _c of the low pass filter 60. The output signal F _{o of the} VCO 70 is 1 / N by the 1 / N frequency divider 71.
After being divided by N, the feedback signal F _r is fed back to the input terminal 41b of the ExOR 41.

In this embodiment, the voltage difference between the positive-phase output and the negative-phase output of ExOR41 is divided into 1: 1 by the resistors 51 and 52 to generate the reference voltage V _r , so that the PLL circuit is always locked. , The DC component of the input signal of the loop filter 60 and the reference voltage V _r applied as the bias match, and the following advantages are obtained.

(1) Even if the DC component of the ExOR41 output signal changes due to temperature and power supply fluctuations, the reference voltage V _r changes correspondingly, so adjustment is unnecessary and the complexity of reference voltage adjustment is eliminated. it can. Moreover, there is no need for compensation circuits for temperature and power supply.

Further, since the voltage appearing on the node N1 is smoothed and stabilized by the capacitor 53, the DC component of the reference voltage V _r operates so as to quickly coincide with the DC component V _i of the positive phase output pulse, and both DC It is possible to accurately and accurately prevent the component deviation.

(2) The reference voltage generation circuit 50 includes resistors 51 and 52 and a capacitor 53.
Since it is composed of, the circuit configuration is simple, it is suitable for monolithic structure including the above (1), and size reduction is easy.

(3) Even if the output frequency of ExOR40 is high, it is possible to operate in an extremely high band because it is not affected by the rise time T _r and the fall time T _f of the signal.

(4) Since the phase comparator 40 is composed of the bipolar type ExOR 41, high speed operation is possible.

The present invention is not limited to the illustrated embodiment, and various modifications can be made. For example, the ExOR 41 may be composed of a circuit other than that shown in FIG. Now, the reference voltage generation circuit 50 has resistors 51, 5
2 and the capacitor 53, the reference voltage generating circuit of the present invention divides the voltage difference between the positive phase output and the negative phase output of the phase comparator 40 into 1: 1 and divides the voltage. Since it is used as the reference voltage V _r , it may be configured by another circuit by adding a diode for level shift or the like.

(Effect of the Invention) As described in detail above, according to the invention of claim 1,
The reference voltage generation circuit divides the voltage difference between the complementary first and second signals output from the phase comparator to 1: 1 to generate a reference voltage, which is then used as a bias voltage in the loop filter. Since the voltage is supplied, the deviation between the average voltage (DC component) of the output of the phase comparator and the average voltage (DC component) of the reference voltage can be prevented in the locked state.
Therefore, it is not necessary to adjust the reference voltage, a wide operation range of the PLL circuit can be secured, deviation of the VCO oscillation frequency when there is no input signal is prevented, and high band operation at a high frequency is possible.

In the invention of claim 2, since the voltage appearing on the reference node is smoothed and stabilized by the capacitor, the DC component of the reference voltage operates so as to quickly coincide with the DC component of the first signal, The deviation of both DC components can be prevented accurately at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit showing an embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional PLL circuit, FIG. 3 (a), (b),
(C) and (d) are output pulse waveform diagrams of the phase comparator of FIG. 2, FIG. 4 is a relationship diagram of the phase difference φ _d and V _c of FIG. 2, and FIGS. 5 (a) and 5 (b). 1 is an output pulse waveform diagram of the phase comparator of FIG. 1, and FIG. 6 is a circuit diagram of ExOR of FIG. 40 ... Phase comparator, 41 ... ExOR, 50 ... Reference voltage generation circuit, 51,52 ... First and second resistance, 53 ... Capacity, 60 ... Loop filter, 61 ... Differential amplifier , 70 …… VCO, 71 …… 1
/ N divider, F _i …… input signal, F _o …… output signal, F _r …… feedback signal, V _r …… reference voltage.

Claims (2)

[Claims] 1. A phase of an input signal and a phase of a feedback signal are compared with each other, and a first signal corresponding to the comparison result is converted into a first signal.
A phase comparator for outputting from the second output node a second signal, which is the opposite phase of the first signal, from the second output node, a reference node to which a reference voltage is applied, and the first signal A loop filter that differentially amplifies this voltage and the reference voltage to pass a low-frequency component of the first signal, and a third filter having a frequency according to the output of the loop filter.
A voltage-controlled oscillator that outputs the signal, a frequency divider that divides the third signal, and outputs the divided signal as the feedback signal, the first output node, the second output node, and The difference between the voltage appearing at the first output node and the voltage appearing at the second output node connected to the reference node is 1: 1.
And a reference voltage generation circuit for outputting the divided voltage to the reference node. 2. The phase locked loop circuit according to claim 1, wherein a capacitor for smoothing a voltage appearing at the reference node is connected to the reference node.