JPS62193127A - Formation of metallic pattern - Google Patents

Formation of metallic pattern

Info

Publication number
JPS62193127A
JPS62193127A JP3421286A JP3421286A JPS62193127A JP S62193127 A JPS62193127 A JP S62193127A JP 3421286 A JP3421286 A JP 3421286A JP 3421286 A JP3421286 A JP 3421286A JP S62193127 A JPS62193127 A JP S62193127A
Authority
JP
Japan
Prior art keywords
resist
substrate
metal film
lift
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3421286A
Other languages
Japanese (ja)
Inventor
Katsuji Mabuchi
馬淵 勝司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP3421286A priority Critical patent/JPS62193127A/en
Publication of JPS62193127A publication Critical patent/JPS62193127A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible to use resist, which is hard to be deformed and peeled, by providing a process for forming a metal film on a substrate including the resist, and providing a process for applying plasma etching, removing the resist and removing the metal film on the resist by lift-off. CONSTITUTION:Resist 12 is applied on a GaAs substrate 11, on which an N<+> layer 10 is formed. Thereafter, ultraviolet rays are applied through a photomask 13 with a line having a width of 4mum being made to remain, and the resist is exposed. Then the device is rinsed and undergoes post-baking. Thus the pattern of the resist 12 is formed. Thereafter with the resist 12 as a mask, a metal film 15 is formed. Plasma etching using oxygen gas is performed, and the resist 12 is removed. Metallic patterns 14 and 15 are made to remain on the substrate 11. When lift-off is performed, a substrate 23 is set on a substrate holding stage 24. Air in a bell jar 16 is sucked through an exhausting pipe 17 and oxygen gas is supplied. A high frequency electric field is formed between electrodes 18 and 18, and oxygen plasma is yielded. Thus, the resist, which is hard to be deformed and peeled with etching liquid, can be used, and the pattern accuracy of the formed metal film is enhanced.

Description

【発明の詳細な説明】 イ)産業上の利用分野 本発明はリフトオフ法を利用した金属パターンの形成方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention relates to a method for forming a metal pattern using a lift-off method.

口)従来の技術 従来よりの薄膜パターンの形成方法としては。Mouth) Conventional technology As for the conventional method of forming thin film patterns.

(Al基体の上全面に薄膜を形成した後、不必要な部分
を除去するもの、(B)基体の上の薄膜を形成しない部
分に前もって被膜を形成し、その上から全面に薄膜を形
成した後に、被膜を除去することによって薄膜を除去す
るものという大別して2種の方法がある。
(A thin film is formed on the entire surface of the Al substrate, and then unnecessary parts are removed. (B) A film is previously formed on the parts of the substrate where the thin film is not to be formed, and a thin film is then formed on the entire surface. There are two types of methods: one in which the thin film is removed by subsequently removing the coating.

まず囚)の方法であるが第6図乃至第9図を用いて示し
て説明してゆく。シリコン半導体基板(1)上にAI!
膜(2)を蒸着し、その上からレジスト(3)を塗布し
てホトマスク(4)を密着させ、紫外光線(5)により
レジスト(3)を露光させる(第6図)。レジストには
ネガ型とポジ型があるが、この例ではネガ型の場合を示
す。レジスト(3)は現像されると第7図の(6)の形
状になる。その後Al膜(2)ヲリン酸系エツチング液
で除去してAI!配線(7)を形成しく第8図)、レジ
スト(6)を除去する(’49因)。ところがこの方法
ではAI!膜がエツチングされる時に周辺部より内側に
もエツチングされるため、p、!膜のパターンはレジス
トパターンに対して必ず小さくなってしまう。このため
正確な微細パターンを形成することは不可能である。又
、シリコン基板に段差がある場合などにはレジストの除
去が完全にできずに、Al膜がエツチングされないで残
るということもありうる。
First, the method described above will be illustrated and explained using FIGS. 6 to 9. AI on silicon semiconductor substrate (1)!
A film (2) is deposited, a resist (3) is applied thereon, a photomask (4) is adhered thereto, and the resist (3) is exposed to ultraviolet light (5) (FIG. 6). There are two types of resist: negative type and positive type, and this example shows the case of negative type. When the resist (3) is developed, it has the shape shown in (6) in FIG. After that, remove the Al film (2) with a phosphoric acid etching solution and use AI! The wiring (7) is formed (FIG. 8), and the resist (6) is removed ('49 factor). However, with this method, AI! When the film is etched, it is also etched inward from the periphery, so p,! The film pattern is always smaller than the resist pattern. For this reason, it is impossible to form accurate fine patterns. Furthermore, if there are steps on the silicon substrate, the resist may not be completely removed and the Al film may remain unetched.

次にfBlの方法を第10図乃至第13図に基いて説明
する。まずシリコン半導体基板(1)の上にレジスト(
2)を塗布してこれをホトマスク(4)を通した紫外線
(5)により感光させる(第10図)。レジスト(2)
はネガ型を用いて現像すると、第11図の(8)の形状
のレジストが残る。この状態でfi!膜(2)を蒸着さ
せ(第12図)、レジスト(6)を除去することでその
上のAl膜(2)も除去されてp、l配線(7)が残存
される(第13図)。
Next, the fBl method will be explained based on FIGS. 10 to 13. First, a resist (
2) is applied and exposed to ultraviolet light (5) through a photomask (4) (FIG. 10). Resist (2)
When developed using a negative type, a resist having the shape of (8) in FIG. 11 remains. In this state fi! By depositing the film (2) (Fig. 12) and removing the resist (6), the Al film (2) above it is also removed, leaving the p and l wiring (7) (Fig. 13). .

(Blの方法ではレジストで正確なパターンが形成でき
れば、AJ膜はそれとはネガのパターンとして形成され
るので、微細なパターンも作りやすい。
(With the Bl method, if an accurate pattern can be formed with the resist, the AJ film is formed as a negative pattern, making it easy to create fine patterns.

この(ト))の方法は一般にリフトオフ法と言われるも
のであって、このような技術は例えば特公昭58−45
81Q号、特公昭5B−46846号等に記きれている
This method (g)) is generally called the lift-off method, and such a technique was developed, for example, by the Japanese Patent Publication Publication No. 58-45
It is described in No. 81Q, Special Publication No. 5B-46846, etc.

ハ)発明が解決しようとする問題点 ところで、こうしたりフトオフ法ではレジストの享さは
十分厚く6.1μ程度)にしなければ第14図のように
リフトオフすべきA I Iu%(2+と残存させるべ
きAJ配線(9)が分離されない。このためレジストの
厚さを厚くするとボストベーク時の熱や基板表面エツチ
ング用のエツチング液(例えば弗酸、燐酸)の使用時に
変形剥離され易くなる。従って、熱やエツチング液に対
して変形、剥離起さないレジスト(例えば、OMF+−
85,0NNR−22)を用いることが考えられるが、
こうしたレジストはアセトン等の有機溶媒に容易に溶解
しない。
c) Problems to be solved by the invention By the way, in the lift-off method, if the resist is not made sufficiently thick (approximately 6.1μ), the A I Iu% (remains as 2+) that should be lifted off as shown in Figure 14. The AJ wiring (9) that should be used is not separated.For this reason, if the thickness of the resist is increased, it is likely to be deformed and peeled off during the heat during post baking or when using an etching solution (for example, hydrofluoric acid, phosphoric acid) for etching the substrate surface. Resist that does not deform or peel off due to etching solution or etching solution (for example, OMF+-
85,0NNR-22) may be used, but
Such resists do not easily dissolve in organic solvents such as acetone.

二)問題点を解決するための手段 本発明はこのような点に鑑みて為されたものであって、
基板上にレジストを形成する工程と、このレジストを所
望の形状にバターニングする工程と、このレジストを含
む基板上に斂属膜を設ける工程と、プラズマエツチング
を施してレジスト除去し、レジスト上の会戦膜をリフト
オフ除去する工程とを有している。
2) Means for solving the problems The present invention has been made in view of the above points,
A step of forming a resist on a substrate, a step of patterning this resist into a desired shape, a step of providing a resistive film on the substrate including this resist, a step of removing the resist by plasma etching, and a step of patterning the resist into a desired shape. and a step of removing the battle membrane by lift-off.

ホ)作  用 プラズマエツチングを施しているので、熱や基板表面処
理のエツチング液の使用により変形、剥離のしにくいレ
ジストが使用出来、また、リフトオフ法のレジストの除
去が行える。
E) Function Since plasma etching is performed, a resist that is not easily deformed or peeled off by heat or the use of an etching solution for substrate surface treatment can be used, and the resist can be removed using the lift-off method.

へ)実施例 第1図乃至第5図1コ本発明金属膜形成方法の一実施例
を工程順に示した断面図であって、これ等の図を用いて
1本発明を詳述する。まず表面に1μ厚のn+1Nf1
0+が形成されたG & A 8 f板(111上K。
f) Embodiments FIGS. 1 to 5 are cross-sectional views showing an embodiment of the metal film forming method of the present invention in the order of steps, and the present invention will be described in detail using these figures. First, 1μ thick n+1Nf1 on the surface.
G & A 8 f plate with 0+ formed (K on 111).

例えば0NNR−22(東宗応化製)得・のレジス)!
121を塗布した後、ホトマスクα3を通して4μ巾の
ラインを残して紫外線で14秒の感光を行う(第1図)
。続いて、現像60秒、リンスエによる洗浄60秒、リ
ンスHによる洗浄60秒行い160℃で30分のボスト
ベークを行って、巾4μ約1μ厚のレジス)(121の
パターンが形成される(第2図〕。その後このレジスト
(121をマスクとして。
For example, 0NNR-22 (manufactured by Tosou Ohka) (regis)!
After applying 121, it was exposed to ultraviolet light for 14 seconds through a photomask α3, leaving a 4 μ wide line (Figure 1).
. Subsequently, development is carried out for 60 seconds, cleaning is performed for 60 seconds with Rinse H, cleaning is performed for 60 seconds with Rinse H, and a post bake is performed at 160° C. for 30 minutes to form a resist pattern (121) having a width of 4 μm and a thickness of approximately 1 μm. Figure]. Then use this resist (121 as a mask).

CCz 2 F 2ガスを用い、3X10    To
rr。
Using CCz 2 F 2 gas, 3X10 To
rr.

gl桃内1り力0.517−の条件で基板[11)表面
に30秒のエツチングを施し、レジストll7J部以外
ヲ0.5μ窪ませる(第3図)。次にAu+Ge、Ni
Etching is performed on the surface of the substrate [11] for 30 seconds under the condition of a gl Momouchi force of 0.517-, and a depression of 0.5 μ is made in the area other than the resist 117J portion (FIG. 3). Next, Au+Ge, Ni
.

Auを夫々2000A、1000A、 2ooo1の順
に蒸着して金属膜α9を形成しく第4図)、酸素ガスを
用いたプラズマエツチングを施してレジストazを除去
して巾4μの間隔が開けられた金属パターンa41ns
1Fe基板ail上に残存させる(第5図)。
A metal film α9 is formed by depositing Au in the order of 2000A, 1000A, and 2ooo1 (Fig. 4), and the resist az is removed by plasma etching using oxygen gas to form metal patterns with intervals of 4μ in width. a41ns
1Fe substrate ail (FIG. 5).

$15図は本発明リフトオフ方法を実施するのに用いら
れるペルジャーの断面模式図、第16図はペルジャー内
の各部の分解斜視図である。これ等の図においてC61
はペルジャー、σnはこのペルジャー(1b1円の排気
を行う排気管、 (181Qlcは夫々130諷X30
0mの大きさで150mの間隔で対向配置され六平板電
極であって、13.56MHz、250Wの高周波電界
が発生される。rilは上面側の電極aa下に設けられ
、略電極a秒と同形状の大きさの四角形に組まれ念パイ
プに多数の小孔■■を開けて成る1人管を示し、酸素ガ
スを上記平板電極0&Oa間に供給する。C21+はス
リット状に形成された棚であって、上記電極0■a間に
配置される。のは5字状に屈曲された基板保持台であっ
て、基板[有]を電極0■δ面に対して45°〜60°
の角度を保って保持するための係止部Q4Jが設けられ
ている。
FIG. 15 is a schematic cross-sectional view of a Pel jar used to carry out the lift-off method of the present invention, and FIG. 16 is an exploded perspective view of various parts within the Pel jar. In these figures C61
is Pelger, σn is this Pelger (exhaust pipe that exhausts 1b1 circle, (181Qlc is 130x30 respectively)
Six plate electrodes are arranged facing each other with a size of 0 m and an interval of 150 m, and a high frequency electric field of 13.56 MHz and 250 W is generated. ril is a one-man tube that is installed under the electrode aa on the upper surface side, is set in a rectangular shape approximately the same size as the electrode a second, and is made of a pipe with many small holes. Supplied between flat electrodes 0 & Oa. C21+ is a shelf formed in the shape of a slit, and is arranged between the electrodes 0■a. This is a substrate holding stand bent in a 5-shape, and the substrate is held at an angle of 45° to 60° with respect to the electrode 0■δ plane.
A locking portion Q4J is provided to maintain and hold the angle.

このような装置を用いて、リフトオフを行う場合、基板
c!31ヲ基板保持台(241にセットし、この基板保
持台C241を棚に配置すると、基板のは電極0810
81に対して45〜60°の角FIFヲなすようになる
。この状態でペルジャー(lLbl内を排気管σηから
の吸引により0.5〜0.8℃0ヒヒ に引きながら、
酸素ガスを瘍入管α9から供給し、同時に電極[18)
QE9間に16゜56MHz、250Wで高周波電界を
生成して。
When performing lift-off using such a device, the substrate c! When the substrate holding stand C241 is placed on the shelf, the electrodes 0810 on the substrate
81 to form an angle FIF of 45 to 60 degrees. In this state, while pulling the inside of the Pelger (lLbl) to 0.5-0.8℃ by suction from the exhaust pipe ση,
Oxygen gas is supplied from the tumor entry tube α9, and at the same time the electrode [18]
A high frequency electric field was generated at 16°56MHz and 250W between QE9.

酸素プラズマを発生させる。これにより基板囚には斜め
方向からプラズマが供給され金属膜下のレジストのエツ
チング効果が増大される。上記条件で15分のエツチン
グを施すことにより4μ巾のリフトオフが行えた。従っ
てμオーダのリフトオフを行うGaASを用い7’?F
F;Tやショットキーダイオードのビームリード電極の
形成に利用出来る。尚、参考例として上記条件で基板を
傾けずにレジストのエツチングを行つ九場合4μ巾のリ
フトオフを行うのに45分程度要した。
Generates oxygen plasma. As a result, plasma is supplied to the substrate from an oblique direction, increasing the etching effect of the resist under the metal film. By performing etching for 15 minutes under the above conditions, a lift-off of 4 microns width was achieved. Therefore, using GaAS with μ-order lift-off, 7'? F
It can be used to form beam lead electrodes for F;T and Schottky diodes. As a reference example, in a case where the resist was etched without tilting the substrate under the above conditions, it took about 45 minutes to perform a lift-off of 4 microns width.

ト)発明の効果 以上述べた如く本発明金属膜の形成方法は、基板上にレ
ジストを形成する工程と、このレジストを所望の形状に
パターニングする工程と、このレジストを含む基板上に
金属膜を設ける工程と、プラズマエツチングを施してレ
ジスト除去し、レジスト上の金属膜をリフトオフ除去す
る工程と、を有しているので、熱や基板表面処理のエツ
チング液により変形、剥離のしにくいレジストが使用出
来、形成される金属膜のパターン精度が高くなる。
g) Effects of the Invention As described above, the method for forming a metal film of the present invention includes the steps of forming a resist on a substrate, patterning this resist into a desired shape, and forming a metal film on the substrate containing this resist. This method uses a resist that is not easily deformed or peeled off by heat or the etching solution used in substrate surface treatment. The pattern accuracy of the formed metal film is increased.

【図面の簡単な説明】[Brief explanation of drawings]

′1J111図乃至85図は本発明金属膜形成方法を工
程順に示す断面模式図、第6図乃至第9図は従来のエツ
チングによる金属膜形成方法を工程順に示す断面模式図
、第10図乃至第13図は従来のリフトオフにより金属
膜形成方法を工程順に示した断面模式図、第14図はリ
フトオフ工程における不良状態を示す断面模式図、第1
5図は本発明金属膜形成方法を実施するためのペルジャ
ーの断面模式図、第16図はペルジャー内部品の分解斜
視図である。 αト・・G&AB基板、(1z・・・レジスト、031
・・・ホトマスク、 f141(15・・・金属膜、 
(161・・・ペルジャー、 [71・・・排気管、0
&0■・・・電極、α1・・給気管、CA■・・・小孔
、QB・・・棚、榔z・・・基板保持台、c!3・・・
基板、3滲・・・係止部。
1J111 to 85 are schematic cross-sectional views showing the metal film forming method of the present invention in the order of steps, FIGS. 6 to 9 are schematic cross-sectional views showing the conventional method of forming a metal film by etching in the order of steps, and FIGS. Fig. 13 is a schematic cross-sectional view showing the conventional lift-off method for forming a metal film in the order of steps; Fig. 14 is a schematic cross-sectional view showing a defective state in the lift-off process;
FIG. 5 is a schematic cross-sectional view of a Pel jar for carrying out the metal film forming method of the present invention, and FIG. 16 is an exploded perspective view of the internal parts of the Pel jar. α...G&AB board, (1z...resist, 031
... Photomask, f141 (15... Metal film,
(161... Pelger, [71... Exhaust pipe, 0
&0■...electrode, α1...air supply pipe, CA■...small hole, QB...shelf, z...substrate holding stand, c! 3...
Board, 3 leaks...locking part.

Claims (1)

【特許請求の範囲】[Claims] 1)基板上にレジストを形成する工程と、このレジスト
を所望の形状にパターニングする工程とこのレジストを
含む基板上に金属膜を設ける工程と、プラズマエッチン
グを施してレジスト除去しレジスト上の金属膜をリフト
オフ除去する工程とから成る金属パターン形成方法。
1) A step of forming a resist on a substrate, a step of patterning this resist into a desired shape, a step of providing a metal film on the substrate including this resist, and a step of removing the resist by plasma etching and forming a metal film on the resist. A metal pattern forming method consisting of a lift-off removal process.
JP3421286A 1986-02-19 1986-02-19 Formation of metallic pattern Pending JPS62193127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3421286A JPS62193127A (en) 1986-02-19 1986-02-19 Formation of metallic pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3421286A JPS62193127A (en) 1986-02-19 1986-02-19 Formation of metallic pattern

Publications (1)

Publication Number Publication Date
JPS62193127A true JPS62193127A (en) 1987-08-25

Family

ID=12407850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3421286A Pending JPS62193127A (en) 1986-02-19 1986-02-19 Formation of metallic pattern

Country Status (1)

Country Link
JP (1) JPS62193127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006000945A (en) * 2004-06-15 2006-01-05 National Institute Of Advanced Industrial & Technology Plasma etching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006000945A (en) * 2004-06-15 2006-01-05 National Institute Of Advanced Industrial & Technology Plasma etching method
JP4534010B2 (en) * 2004-06-15 2010-09-01 独立行政法人産業技術総合研究所 Plasma etching method

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