JPS62188263A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To operate the titled memory in a stable manner by substantially reducing the potential difference between the earthing point and an earthing wire of the memory cell by a method wherein adjoining word wire or earthing wire arranged in row (or in column) are connected in a crossing form in the center point or in its vicinity between the earthing wires provided for the column (or row) of a plurality of memory cells. CONSTITUTION:One of electrodes of the first and the second read-out and write-in transistors A1-H1 and A2-H2 are connected to memory cells MA-MH respectively, and other electrodes are connected to column, and they are used as the first and the second bit wires (d) and (-d). Then, the memory cells are formed into connection wires 4 and 6 by connecting the earthed points of the memory cells MA-MH for every row, the connection wires 4 and 6 are connected for every column (4 columns here) of the prescribed number of memory cells, and they are formed into earthing wires 1 and 2. Also, the earthing wires 1 and 2 are wires in such a manner that they make a crossing form for every pair of rows adjoining in the center point of the earthing wires 1 and 2, the gates of the first and the second read-out and wirte-in transistors A1-B2, C1-D2, E1-F2 and G1-H2 are connected common in row direction, and they are constituted as word wires 3 and 5.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

Efforts have been made to increase the density of semiconductor memory devices from various aspects such as circuit technology, miniaturization technology, and layout technology.Recently, this trend has progressed further, and the operating characteristics of semiconductor memory devices have improved. We have reached the point where we are trying to avoid duplication and repetition as much as possible without damaging the design, and to further increase the density by reducing the area occupied by wiring and other parts as much as possible.

Conventionally, in this type of semiconductor memory device, the ground points of a plurality of memory cells arranged in a matrix are not directly connected to a ground line for each row (or column), but the ground points of the memory cells are connected to a ground line in each row (or column).
The connection line is connected to a connection line for each column (or column) of a predetermined number of memory cells, and the connection line is connected to a ground line for each column (or row) of a predetermined number of memory cells.

FIG. 2 is a circuit diagram of an example of a conventional semiconductor memory device, and FIG. 3 is a circuit diagram of a memory cell forming the semiconductor memory device.

This semiconductor memory device includes memory cells MA-MH and first and second read/write transistors A1 to H1 and A2 to
H2 are arranged in a matrix, one electrode of each of the first and second read/write transistors A1-H1 and A2-H2 is connected to the memory cells MA-MH, and the first and second read/write transistors A Engineering～H□ and A2～
The other electrodes of H2 are connected to the respective columns to form the first and second bit lines d and 1, respectively, and the ground points of the memory cells are connected to each row to form the connection lines 4 and 6. Connection lines 4 and 6 are connected for each column of memory cells (4 columns in this case), and these are used as ground lines 1 and 2.
read/write transistors A1-H1 and A2-H2 of
The gates of each row are commonly connected and connected to the word line 3'.
and 5'.

That is, by providing a common ground line for multiple columns of memory cells (four columns in this case), it is possible to provide a ground line for each column of memory cells, unlike conventional semiconductor memory devices with relatively small storage capacity. Reduce the area area of the ground wire compared to the configuration,
The degree of integration of semiconductor memory devices could be further improved.

Furthermore, memory cells MA-M included in this semiconductor memory device
As shown in FIG. 3, H constitutes a kind of 7-lip, 70-tub circuit with memory transistors Q1 and Q2.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory device described above, the ground point of the memory cell is connected to the ground line via the connection line, so a current flows between the ground point of the memory cell and the ground line due to the resistance of the connection line. There is a drawback that a potential difference occurs between the ground point of the memory cell and the ground line.

To explain this in detail with reference to FIG. 2, first, a high level potential is applied to the word line 3' to turn on the read/write transistors A1+A2 to D□+D2, and then the memory cells MA to The memory transistors Q1 and Q2 of the MD are connected to the pit lines d and τ and are in a driven state. At this time, currents 1hxe iAz - tpt, tpz flowing from the memory transistors in the on state through the grounding points of the storage cells to the grounding lines 1 and 2 flow as shown in FIG. However, although current also flows in memory cells that are not in the driven state, it is generally much smaller than when the memory cells are in the driven state. Therefore, the potentials vA and vd of the ground points A and B of the memory cells MA and MB are as follows, where the resistance of the ground line is R, VA==RX(i person 1+1B1-1-i01+1D1
) ・”=(1)VB=VA+2RX(tni+io
x+1nt-i personz)-(z).

Here, each current ratio of each memory cell is 1A1/12~i
This is because D1/ID2 is determined by the reciprocal of the ratio of the impedances of the left ground line 1 and the right ground line 2 viewed from each ground point of the memory cells MA-MD.

Also, the sum of the currents of each memory cell iA1+iAz, ~1iDl
+inz are equal iA1+1A2=:1B1-1-iB2:...
=iD1-1-iD2=I, and further assume that grounding wire 1 and grounding wire 2 are symmetrical from the center, then the sum of the current flowing into left grounding wire 1 and the right grounding The total current flowing into line 2 is equal to iAx+...+1D1=i, +u+...
・It can be expressed as +tD2=2I. therefore,
If we set ■=810 and expand equations (1) and (2), we get Vi=16ia R=2IR-...-(31
V B “MA + 16 lo R” 32 io
R= 4 I R..." t4).

(or to) and R can be set to various values depending on the circuit configuration and process conditions, but typical values are I = 200 to 300 μA, R = 20 to 30 Ω.
Using, Vλ=8~18 mV + Vi3 =
It becomes 16-36mV. This value cannot be ignored when considering fluctuations in the threshold voltage of the transistor due to the floating potential of the semiconductor substrate, variations in individual transistors, and the like.

Also, this value is for the case where a ground line is provided for every 4 columns of memory cells, but if a ground line is provided for every 16 columns or every 32 columns in order to further improve the degree of integration, the situation becomes more serious. It becomes a problem.

An object of the present invention is to improve storage density by allowing a plurality of columns (or rows) of memory cells to share a ground line via a connection line, and to reduce the potential difference between the ground point of the memory cell and the ground line. It is an object of the present invention to provide a semiconductor memory device that can operate stably with as little reduction as possible.

[Means for solving problems]

A semiconductor memory device of the present invention includes a plurality of memory cells arranged in rows and columns, a ground line arranged in the column (or row) direction for each column (or row) of a predetermined number of the memory cells, and the ground line a word line that is wired so as to cross each other for each pair of two adjacent rows (or columns) at or near the center between them, and commonly connects the memory cells in the row (or column) direction, or the ground; Wiring is done so that each set of two adjacent rows (or columns) is crossed at or near the center between the lines, and the ground point and ground line of the memory cell are connected in the row (or column) direction. and a connecting line.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the semiconductor memory device of the present invention.

The semiconductor memory device of this embodiment has memory cells MA to MH and first and second read and write transistors Al-Hl and A2 to H2 arranged in a matrix, and first and second read and write transistors A1 to H1. One electrode of each of A2 to A2 to H2 is connected to the memory cells MA to MH, and the other electrode is connected to a column to form the first and second bit lines d and 1. Connect the grounding points for each row and use them as connection lines 4 and 6. Connect the connection lines 4 and 6 for every predetermined number of memory cell columns (here, 4 columns) and use them as grounding lines 1 and 2. The first and second read/write transistors A are wired so as to cross each other in pairs of two adjacent rows at the center between the lines 1 and 20.
l~B2. C, ~D2, E1~F2 and 01~
The gates of H2 are commonly connected in the row direction and are configured as word lines 3 and 5.

Next, the operation of this embodiment will be explained with reference to FIG.

When the word line 3 is set to a high level potential and the word line 5 is set to a low level potential, the first and second read/write transistors A1 to B2 and 01 to H2 are turned on, and the first
and second read/write transistors C□-D2 and E
When l to F2 are in the off state, the memory cell MAaM
B, MG, and MH are connected to bit lines d and d and are in a driven state, but memory cells M□+MD 1MB and M are not connected to bit lines d and τ. In this case, the magnitudes of the currents io1~iD2 and fit~iF2 of the memory cells M()+MDt MB and M, which are not in the driven state, are the same as those of the memory cells M who are in the driven state.

Currents iAt ~inz and tot of MB, MG and MH
Since it is generally very small compared to the magnitude of ~lH,z, the potential vA of the ground points A and B of the memory cell M and MB
and VB is VA=R・(iAt+i+n)=12io R=(3
/2)IR-(5)VB=VA+2R-(1nx-fA
2)=20io R=(5/2)IR-(a), and when compared with the conventional example, it can be expressed that v people=〒V large.

Therefore, the potentials of ground points A and B are 75% and 6% of the conventional example.
2.5%, respectively, and the operation of such a high storage density semiconductor memory device can be made more stable.

In addition, this tendency is more likely to decrease as the spacing between ground wires is increased, such as every 16th or 32nd column, compared to the case where a grounding line is provided every 4th column of memory cells as in this embodiment. The effect becomes more pronounced.

In this embodiment, a ground line is provided for each even-numbered column of memory cells, but it is not necessarily necessary to provide a ground line for each even-numbered column, and it may be provided for each odd-numbered column.

However, if a ground line is provided for each odd-numbered column, the place where the word line is connected cross-wise is offset to the left or right from the center between the ground lines, but the same You can expect good results.

Furthermore, in this embodiment, the word lines are connected so that adjacent rows cross each other at the center between the ground lines, but in place of the word lines, a reed connecting line is connected so that adjacent rows cross each other. It is obvious that there is no problem in connecting it as shown.

〔Effect of the invention〕

As explained above, the present invention connects word lines or connection lines arranged in the row (or column) direction at or near the center between the ground lines provided for each column (or row) of a plurality of memory cells. By cross-connecting the semiconductor memory devices, the potential difference between the ground point and the ground line of the memory cells of a semiconductor memory device intended to be further increased can be reduced as much as possible, resulting in stable operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention;
FIG. 2 is a circuit diagram of an example of a conventional semiconductor memory device, and FIG. 3 is a circuit diagram of a memory cell forming the semiconductor memory device. 1.2...Grounding line, 3,3'...Word line, 4...Connection line, 5,5'...Word line, 6. ...Connection wire, A1+A2~Hl, H
2...Read/write transistor, d, d...
...Bit line, iAl, iA2~iH1, iH
2...Memory cell ground current, MA-MH...
...Memory cell, Q□, Q2...Transistor, R, r...Resistance, vcc...Power supply voltage.

Claims (1)

[Claims] A plurality of memory cells arranged in a matrix, a ground line arranged in the column (or row) direction for each column (or row) of a predetermined number of the memory cells, and a ground line at or near the center between the ground lines. A word line that is wired across each pair of adjacent rows (or columns) and commonly connects the memory cells in the row (or column) direction, or the center or the vicinity thereof between the ground lines. and a connection line that is wired so as to cross each other between two adjacent rows (or columns) and connects the ground point and ground line of the memory cell in the row (or column) direction. A semiconductor storage device.