JPH05174578A - Semiconductor apparatus - Google Patents

Abstract

PURPOSE:To lower a peak current by reducing noises of a power source voltage and a ground voltage which are caused by charging or discharging of a bit line during a sense operation. CONSTITUTION:Power source wires 71 and 72 for sense amplifiers provided at a memory cell array 1 in a mesh and ground wires 61 and 62 are formed in a shape of a comb to be put together mutually so that a parasitic capacitance is generated between the power source wires and the ground wires. The parasitic capacitance arranged between the power source wires and the ground wires acts as decoupling capacitance thereby enabling reduction of noises when the power source and the ground are sensed while allowing the suppression of a peak current as small as possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a semiconductor memory device which reduces power supply noise during a sensing operation.

[0002]

2. Description of the Related Art FIG. 8 shows, for example, ISSCC '91 T.
AM6.3: "A 64Mb DRAM with M
eshed Power Line and Dist
ribbed Sense-Amplifier D
7 is a diagram of the semiconductor memory device showing the mesh-shaped power supply wiring shown in “River” P109, in which 1 is a memory cell array unit (or, hereinafter, also referred to as memory cell block), and each memory cell array unit 1 is 1 2 is a row decoder provided for each memory cell array portion 1, 3 is a column decoder commonly provided for four memory cell blocks, and column selection signals 51 to 5n are provided. The output 4 is a sense amplifier group and an I / O gate group (hereinafter referred to as a sense amplifier group and an I / O gate group) that are commonly provided to the two memory cell blocks.
In some cases, one of the words of the O gate group is used), and the column selection signals 51 to 5n are received to connect the bit line pair and the I / O line pair in the memory array. Reference numeral 6 is a ground pad for supplying a ground level to the sense amplifier group 4, and 7 is a power supply pad for supplying a power supply voltage level to the sense amplifier group 4.

FIG. 9 shows the sense amplifier group and I / O of FIG.
It is the figure which showed the part of the gate group 4 in detail. 81, 82
Is a bit line, and 91 and 92 are inverted bit lines having a bit line capacitance C _B and connected to the memory cell array section 1.
Reference numeral 41 denotes a cross-couple type sense amplifier, which is supplied with power from a sense ground line 61 to which a ground level voltage is supplied and a sense power supply line 71 to which a power supply voltage is supplied, and is activated by a sense amplifier activation signal 10. .. 42
Is an I / O gate, which is an N-channel transistor Q ₁ ,
It is composed of Q _2, and by activating the column selection lines 51 and 52, bit lines and inverted bit lines 81 and 8
2, 91 and 92 are connected to the I / O lines and the inverted I / O lines 43 and 44 which are input / output signal lines between the memory cell array unit 1 and the outside. Further, between the ground pad 6 and the sense ground line 6 and between the power supply pad 7 and the sense power supply line 71, there are parasitic resistances of wirings having resistance values R ₁ and R ₂ , respectively.

Next, the operation will be described. FIG. 10 is a waveform diagram of signals showing the operation of the sense amplifier portion of a normal dynamic RAM. The bit line pair that has been precharged to ½ of the power supply voltage is preset to the time t
_{At 0} , the row decoder 2 activates a word line (row selection line) not shown, so that the information of the memory cell selected by the word line is transmitted to the bit line as shown in FIG. A minute potential difference occurs between the bit line and the inverted bit line. Next, as shown in FIG. 10B, at time t ₁ , the sense amplifier activation signal φ is activated, the sense amplifier operates, and a minute potential difference generated between the bit line and the inverted bit line is generated. , And the potential difference of the power supply voltage level is generated in the bit line pair in due course. Also, a plurality of such sense amplifiers are activated at the same time (for example, 4M
With a dynamic RAM having a bit capacity and a refresh cycle of 1 k, about 4000 sense amplifiers are activated at the same time), and the power supply pad 7 or the ground is supplied to the bit line capacity C _B existing in the bit line pair. Power supply or discharge is performed from the pad 6. At this time,
The power supply line 71 and the ground line 61 have substantially a wiring resistance R.
_{Since 1} and R ₂ are present, noise is generated in the power supply voltage for sensing and the ground voltage as shown in FIG.
In addition, as shown in FIG. 10D, a power supply current having a large peak flows due to the charge / discharge current to the bit line immediately after the sense amplifier is activated.

[0005]

Since the conventional semiconductor memory device is configured as described above, noise is generated in the sense power supply line 61 and the ground line 62 immediately after the sense amplifier is activated, This has been a cause of malfunction of other circuits and a decrease in operating margin. Further, since a large current flows at a time, a large noise is generated on the board on which these semiconductor devices are mounted, which makes the board design itself difficult.

The present invention has been made in order to solve the above problems, and it is to reduce the noise generated in the power supply line and the ground line to stabilize the circuit operation and reduce the peak current of the power supply current. The purpose is to solve the implementation problem.

[0007]

A semiconductor device according to a first invention is, for example, one in which a power supply line and a ground line for feeding or discharging a sense amplifier are arranged in a comb shape so as to generate mutual correlation capacitance, It has the following elements. (A) A semiconductor circuit that performs a predetermined operation by power supply and discharge,
(B) Capacitance holding means in which two conductors having different potentials for feeding and discharging the semiconductor circuit are arranged so as to face each other in a predetermined layout, and the capacitance can be held between the two conductors.

Further, in the semiconductor device according to the second invention, for example, a capacitor connected to the power supply line and the ground line is formed in a circuit unarranged region where the word line lining portion and the band of the sense amplifier intersect. It has the following elements. (A) A semiconductor circuit arranged to perform a predetermined operation by feeding and discharging, (b) two conductors having different potentials for feeding and discharging the semiconductor circuit, and (c) respectively connected to the two conductors. And two conductive layers formed so as to face each other so as to retain the capacitance, in the undisposed portion of the semiconductor circuit.

[0009]

In the semiconductor device according to the first and second aspects of the invention, the decoupling capacitance can be formed between the conductors having different potentials such as the power supply line and the ground line. Cancel the noise of conductors (power line and ground line). This has the effect of reducing noise and prevents malfunction, and the decoupling capacitance absorbs the peak current during power consumption during sensing operation, etc., which reduces the peak current and reduces noise on the mounting. Problems can be avoided.

[0010]

【Example】

 Example 1. An embodiment of the present invention will be described below with reference to the drawings
To do. In FIG. 1, 1 is a memory cell array unit (memory
(Also referred to as a cell block), each memory cell array unit 1
It corresponds to 1/4 of the whole block. 2 is each
Row decoding provided for the memory cell array unit 1 of
D and 3 are provided in common for the four memory cell blocks.
Output column select line signals 51-5n
Force 4 is common to two memory cell array blocks
Group of sense amplifiers and I / O gates provided in
Receives the column selection signals 51 to 5n,
Connect the bit line pair in the ray and the I / O line pair
There is. 6 is for supplying the ground level to the sense amplifier group 4.
Ground pad, 7 is a power supply voltage relay to the sense amplifier group 4.
Power pads for supplying bells, each with a resistance value R
₁ , R ₂ Through the parasitic resistance of the wiring with
It is connected to the ground wire 61 and the sense power supply wire 71.
The details of the sense amplifier group and I / O group 4 are
In FIG. 9, since this is the same as the description of the conventional example, here,
The description is omitted.

The sense ground line 61 and the sense power supply line 71 cross the memory cell block and the column selection line 5
1 to 5n run parallel to the column selection line, and are connected to a reinforcing ground line 62 and a reinforcing power supply line 72, which run vertically in the area of the sense amplifier group and the I / O gate group 4, respectively. Has a mesh structure. Further, a ground line 61 and a power supply line 71 running between two column selection lines (for example, 51 and 52) are arranged in a comb shape so as to be further inserted into each other.

FIG. 2 shows this portion in detail.
Further, FIG. 3 shows a cross section of the portions A and B shown in FIG.
Therefore, the power supply line 71 and the ground line 61 are formed in a comb shape so as to be inserted into each other, so that the correlation capacitance C ₁ can be provided between them. The value of C ₁ is calculated by a simple parallel plate approximation, assuming that the power supply line 71 and the ground line 61 have a film thickness of 1 μm and the distance between them is 0.8 μm and both run in parallel for 10 mm. 1 × 10000/8000) × 0.345 ≒ 0.43
(PF), and in the case of FIG. 3, a capacitance five times C ₁ can be formed between the power supply line 71 and the ground line 61. Further, since it is formed in the same manner between the column selection lines, if the number of column selection lines is 512, a decoupling capacitance of C = 0.43 × 5 × 511≈1100 (pF) is generated by the power supply. Line 71 and ground line 6
It will be formed between 1 and.

Next, the operation will be described. FIG. 4 is an operation waveform diagram of the sense amplifier portion showing one embodiment of the present invention. Since the basic operation is almost the same as that of the conventional one, for comparison, the operation of the conventional example is shown by a dotted line and the operation of one embodiment of the present invention is shown by a solid line for comparison.

At time t ₀ , the selected word line (row selection line) is activated, and as a result, as shown in FIG. 4A, the bit that has been precharged to the value of 1/2 of the power supply voltage in advance. The information of the memory cell is read onto the line pair, and a minute potential difference occurs on the bit line pair.

Next, as shown in FIG. 4B, time t ₁
, The sense amplifier activation signal φ becomes active, the sense amplifier operates, the minute potential difference generated between the bit line and the inverted bit line is amplified, and eventually the amplitude of the bit line reaches the power supply voltage level. ..

At the time of sensing, a plurality of sense amplifiers are simultaneously activated as described in the conventional example (1 of 4MDRAM).
Approximately 4000 pieces are activated at the same time by k refreshing), so the ground pad 6
The current I ₁ flowing out of the sense amplifier group and the current I ₂ flowing into the sense amplifier group from the power supply pad 7 become very large, and wiring resistances R ₁ and R ₂ parasitically generated in the ground line and the power supply line cause Similar to the case, the operation is performed in the direction in which noise is generated in the ground level power supply voltage level in the sense portion. However, in this case, since a large capacitance C is formed between the power supply line 71 and the ground line 61, the currents I ₁ and I flowing (flowing) into the sense amplifier are generated.
₂ all even supply is performed from the decoupling capacitor C instead of being supplied from the power supply pad 7 and ground pads 6. As a result, the maximum values of the currents I ₁ ′ and I ₂ ′ flowing in the parasitic resistances R ₁ and R ₂ become smaller than the maximum values of I ₁ and I ₂ flowing in the sense amplifier portion, as shown in FIG. Thus, the noise generated in the power supply voltage and the ground voltage at the time of sensing becomes small. Also, the fact that I ₁ ′ and I ₂ ′ are small means that the total charge supplied to the sense amplifier does not change as shown in FIG. 4D, but the peak current can be kept low. Shows.

As described above, in this embodiment, the memory cells are arranged in a matrix, and
A plurality of word lines for selecting a row of the memory cell array, a plurality of bit line pairs for transmitting the signal of the memory cell, a plurality of sense amplifiers for amplifying a minute potential difference generated in the plurality of bit line pairs, and a plurality of sense amplifiers. In a semiconductor memory device having a row decoder, a plurality of column decoders, a power supply line for supplying power to the sense amplifier, and a ground line for discharging electric charge to the sense amplifier, the power supply line and the ground line are The semiconductor memory device has been described in which the memory cell array portion is arranged in a mesh shape, and further, the power supply line and the ground line are arranged in a comb shape so as to generate mutual correlation capacitance.

Example 2. In the above embodiment, the power supply line 71 and the ground line 61 arranged in a mesh are arranged in the running direction of the column selection lines 51, 52, ... , The case where the decoupling capacitance is provided between the power supply line and the ground line is shown, but in the second embodiment, the word line staking part (which will be described in detail later), the sense amplifier group and the I /
A case where decoupling capacitors are provided at the cross points of the O gate group 4 by using different conductive layers will be described below.

FIG. 5 is a diagram showing the configuration of the second embodiment. Usually, the word lines 51, 52, ..., 5n are formed of polysilicon or a two-layer structure of refractory metal and polysilicon, and have high resistance. As a result, the rise of the word line is delayed due to the time constant of the resistance and the capacitance of the word line. In order to solve this drawback, it is generally accepted that the word line is lined with a layer having a low resistance on the upper part of the word line, and the lined portion is referred to as a word line piling portion 80. This word line stakeout section 8
Although 0 is usually formed in a band shape so as to be orthogonal to the band of the sense amplifier group 4, the cross point portion 90 where the band of the sense amplifier group 4 and the band of the word line struck portion 80 intersect is formed. In particular, there is no need to arrange circuits. Therefore, two conductive layers respectively connected to the reinforcing ground wire 62 and the reinforcing power supply wire 72 are formed so as to face the cross point portion 90 between the sense amplifier group 4 and the word line struck portion 80, and both conductive layers are formed. A decoupling capacitor is formed between the transfer layers.

FIG. 6 is a cross-sectional view of the decoupling capacitance holding portion formed at the cross point portion 90. In the figure, S1 is a first conductive layer in which a word line is formed, S2 is a second conductive layer in which a bit line is formed, S3 is a third conductive layer in which a power supply line or a ground line is formed, S4 is a fourth conductive layer in which the word line struck portion in which the word line backing wiring is formed is formed. Normally, the first to fourth conductive layers are used for the purpose as described above, but in this figure, the word line struck portion and the crosspoint portion of the sense amplifier group are particularly shown. It is a portion where it is not necessary to wire and the case where two conductive layers for holding the decoupling capacitance are formed at this cross point portion is shown. 91 is a gate electrode formed on the fourth conductive layer, 92
Is a field active region formed in the first conductive layer. Here, the case where an N-channel MOS capacitor (capacitance formed by using the gate electrode 91 and the field active region 92) is used is shown. In this case, the ground line 62 is connected to the field active region 92, and the power line 72 is connected.
Is connected to the gate electrode 91. Since the voltage of the power supply line 72 is sufficiently higher than that of the ground line 62, this gate electrode 9
A surface inversion layer 93 is always formed immediately below the power source line 72.
The decoupling capacitance is always formed between the ground line 62 and the ground line 62.

As shown in FIG. 5, the normal memory cell array portion 1 is divided into many blocks, and there are many cross-point portions 90 between the band of the word line struck portion 80 and the band of the sense amplifier group 4. Therefore, even if the value of one decoupling capacitance shown in FIG. 6 is not so large, the total decoupling capacitance can be made sufficiently large.
The operation in this configuration is the same as that shown in the embodiment.

Embodiment 3. In the second embodiment, the decoupling capacitance is set to the gate electrode 91 and the field active region 92.
Although the case where two conductive layers are used is shown, they may be formed between the polysilicon electrodes 94 as shown in FIG. In this case, the case where the polysilicon electrode 94 is formed on the second and fourth conductive layers S2 and S4 is shown. In this case, one of the ground line and the power line is connected to one of the polysilicon electrodes 94. It suffices to connect them, and the same effect can be obtained by connecting them upside down.

As described above, in the second and third embodiments, a plurality of word lines formed by the memory cell array in which the memory cells are arranged in a matrix and the first conductive layer that selects the row of the memory cell array. And a plurality of bit line pairs formed of a second conductive layer for transmitting the signal of the memory cell, a plurality of sense amplifiers for amplifying a minute potential difference generated in the plurality of bit line pairs, and a plurality of row decoders. A plurality of column decoders, a power supply line formed of a third conductive layer for supplying power to the sense amplifier, and a ground formed of a third conductive layer for discharging electric charges to the sense amplifier. A line and a fourth conductive layer having a resistance lower than that of the first conductive layer, and provided in a strip shape to connect the word line backing wiring formed on the plurality of word lines to the word line. Half with connecting area In the body storage device, the power supply line and the ground line are arranged in a mesh shape in the memory cell array portion, and further in a region where the connection area provided in a strip shape and the sense amplifier provided in a strip shape intersect with each other. The semiconductor memory device has been described in which a capacitor is provided between the power supply line and the ground line by using a wiring layer other than the third conductive layer.

Example 4. In the first embodiment described above, the case where the power supply line and the ground line are arranged in a comb shape has been described. However, the power supply line and the ground line are not limited to the comb shape and are arranged so that the power supply line and the ground line face each other in a predetermined layout. It is only necessary that the correlation capacity be maintained between the two.
Further, the power supply line and the ground line are examples of the two conductors having different potentials in the present invention, and the names of the power supply line and the ground line are not limited to particular ones, and conductors having two different potentials may be present.

Example 5. In the above Examples 2 and 3,
The case where the capacitance can be held by using the word line staking section and the crosspoint section of the sense amplifier has been described.
This cross point portion is an example of a portion in which a semiconductor circuit is not arranged, and if there is another conductive layer in which a circuit is not arranged, a layer capable of holding capacitance may be formed in that portion. ..

Example 6. In the above Examples 1 to 5,
Although the case of the semiconductor memory device has been described, the present invention can be applied to the case where it is desired to reduce the noise generated in the power supply line and the ground line in other semiconductor devices to stabilize the circuit operation. Produce the effect of.

[0027]

As described above, according to the first and second aspects of the present invention, by forming a sufficiently large decoupling capacitance between conductors having different potentials, such as a power supply line and a ground line, electric power is supplied from the conductors. It is possible not only to stabilize the internal circuit operation because it is possible to reduce the noise level that occurs in the conductor when it is consumed, and it is also possible to suppress the peak value of the current. It is also possible to solve the problem of noise in board design when mounting on a board.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a partial detailed view of an embodiment of the present invention.

FIG. 3 is a sectional view of an embodiment of the present invention.

FIG. 4 is an operation waveform diagram of one embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a partial cross-sectional view of another embodiment of the present invention.

FIG. 7 is a partial cross-sectional view of another embodiment of the present invention.

FIG. 8 is a block diagram of a conventional semiconductor memory device.

FIG. 9 is a partially enlarged view of a conventional semiconductor memory device.

FIG. 10 is an operation waveform diagram of a conventional semiconductor memory device.

[Explanation of symbols]

1 Memory Array Section 2 Row Decoder 3 Column Decoder 4 Sense Amplifier Group, I / O Gate Group 51-5n Column Select Line 6 Ground Pad 61, 62 Ground Line 7 Power Pad 71, 72 Power Line 41 Sense Amplifier 42 I / O Gate 81, 82, 91, 92 Bit line, inverted bit line 43, 44 I / O line, inverted I / O line 10 Sense activation signal line 80 Word line Punching portion 90 Cross point portion φ Sense activation signal Q ₁ , Q ₂ N-channel MOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8728-4M H01L 27/10 325 V

Claims (2)

[Claims] 1. A semiconductor device having the following elements: (a) a semiconductor circuit that performs a predetermined operation by feeding and discharging; (b) a predetermined layout of two conductors having different potentials for feeding and discharging the semiconductor circuit. Capacitance holding means arranged so as to face each other so that the capacitance can be held between both conductors. 2. A semiconductor device having the following elements: (a) a semiconductor circuit arranged to perform a predetermined operation by feeding and discharging, (b) two semiconductor circuits having different potentials for feeding and discharging the semiconductor circuit. Conductors, (c) Two conductive layers respectively connected to the two conductors and formed so as to oppose each other in an unarranged portion of the semiconductor circuit so as to retain capacitance.