JPS62188098A - Semiconductor read only memory - Google Patents

Abstract

PURPOSE:To accelerate access, by dividing a MOSFET connected in series to the output line of a memory matrix into plural groups, and synthesizing an output signal from each group. CONSTITUTION:MOSFETs M01 and M02 in ROM circuits 2 and 3 that a MOSFET connected in series is divided into two, are turned on with a clock pulse phix, and pre-charge capacitors C1 and C2 with a negative power source, the inverse of VDD. Next, when the FETs M01 and M02 are turned off, and FETS M11-M1n, and M21-M2m conduct according to the states of input signals A11-A2m, the electric charge of the capacitors C1 and C2 are discharged. Therefore, the same output O3 as the one made by synthesizing the outputs of output terminals O1 and O2 with a NOR circuit 4, and forming all of the MOSFETs in series, can be obtained and also, a time constant is reduced by division, and the access can be made into the high speed.

Description

Detailed Description of the Invention The present invention relates to a semiconductor read-only memory (hereinafter referred to as ROM), in which a plurality of insulated gate field effect transistors (hereinafter referred to as KFET) are connected in series to one output line. This relates to connected ROMs (such a ROM is referred to as a vertical ROM).

For vertical ROM, Japanese Patent Application No. 1973-107350
There is a method similar to that proposed in No. K (Japanese Patent Laid-Open No. 52-30388). An example of this is shown in FIG.

In this example, a capacitor 01 is connected between the output terminal AD0 and the ground, and a capacitor 01 is connected between the negative power supply -VDD and the output terminal KM.
O3FETMO is connected, and MOSFETM to Mn are connected in series in parallel with the capacitor C1 between the output terminal and ground.

MOSFETM acts as a switch to precharge the capacitor CtK, and the MOSFETM connected in series acts as a switch to precharge the capacitor CtK.
SFETM or Mn acts as a switch that receives inputs A1 or AH (in this example, MOSFETM has a depressure M7m, regardless of the potential of the gate electrode receiving input A1 or AH).

It's on. That is, a current path is formed between the source and drain of M. On the other hand, MOSFET
Ml, Mn-5, Mn are enhancement types,
It turns on and off depending on its gate potential. Therefore, the output end is 10 people. The above enhancement type MOS is connected between
If all of the FETs are on, a current path is created; if any one is off, no current path is created.

In this example, as shown in the time chart of FIG. 2, first, when the clock signal φX becomes a negative potential -VDD, the FETMo is turned on and the capacitor CI is charged up. Next, when the level of the clock signal φ returns to the ground potential GND again and as a result, the FETMo is turned off, the series-connected FETM to Mn
If at least one of them is off, it is a capacitor.

The charge of is not discharged. Therefore, the voltage across the capacitor C1 remains as it was when it was precharged.

A current path is created in all of the FETM or Mn, and the charge in the FETM is discharged. This capacitor 01
The voltage across 0 eventually becomes zero.

In this circuit, if one of FETM or M is off, there is no change in the precharged charge of capacitor 01, so after precharging, the output signal from the output terminal D0 is immediately used. It's okay to do that.

However, M, or MnK! When a flow path is formed, the charge of capacitor 01 after precharging does not immediately become VcO. That is, capacitor C3
is the FETM in the off state.

Since the series resistance between the source and drain of M or M is short-circuited, it takes time tt 1 for the potential of the output terminal ADO to reach an appropriate value depending on the input voltage or An.
To: It takes.

Therefore, the next circuit (not shown) connecting the output terminal ADo to the input terminal is turned on to receive the input signal 13 hours after the circuit of FIG. 1 was precharged.

The circuit shown in Fig. 1 selectively connects MOSFETs connected in series between the output terminal D0 and ground to select enhancement type, depressure type, and so on. / By forcing the input person or An
The logic for can be changed arbitrarily.

This method of changing the logic is based on the matrix-arranged M
It is suitable for configuring a ROM using OS FET. For example, among MOSFETs arranged in a matrix, the sources and drains of MOSFETs arranged in a column direction are connected in series, and a plurality of input wirings with gate electrodes in a direction perpendicular to the columns, for example, A to N in FIG. and φ
The MOSFET selected from the above MOSFETs is set to be a depressure 3 type. By doing so, desired logic outputs can be extracted from each column of the matrix arrangement.

In the example of Fig. 1, the clock pulse φ is also connected to the power supply -VDD.
Since current only flows when X becomes a negative potential, power consumption is low.

However, when many MOSFETs are connected in series in order to receive many input signals, this circuit increases the resistance between the source and the four sides of the series-connected MOSFETs. It is necessary to increase the time required to obtain a level signal. In other words, the access time becomes longer.

An object of the present invention is to provide a ROM with faster access time.

Another object of the present invention is to provide a ROM that has a simple configuration and can achieve faster access times.

Another object of the invention is to provide a ROM suitable as an integrated circuit device.
Our goal is to provide the following.

According to the invention, MOSFETs requiring series connection are divided into groups, and the output signals from the groups are later combined. A composition means is placed between the divided groups.

The circuit diagram in FIG. 3 shows the configuration of group division.

In the same figure, 2 is the first ROM circuit, 3 is the second RO
M circuit, 4 is a NOR circuit, and 5 is an inverter.

In the ROM circuit 2, the output terminal O1 and the negative power supply -VD
A MOS FET M o t for precharging the capacitor C0 is connected between the output terminal 01 and the ground.
n are connected in series. The gate of MOSFETMOI is connected to the terminal for clock pulse φX, and the MOS
The gates of the FETMs, . . . , Mln are connected to terminals for receiving input signals All, .

In the ROM circuit 3, the output terminal 02 and the negative power supply -VD
A MOSFET M, t for precharging the capacitor 〇, is connected between the output terminal 0.D and the output terminal 0.D. MOSFETs M*t to M2□ are connected in series between and ground. , MOSFET M0. The gate of is clock pulse φ
Connected to the terminal for X, MOSFET M□ or M
Each of the 2m gates is connected to a terminal for receiving the input signal I or I.

In this example, all MOSFETs are
The ETs are of the P-channel type, and they are fabricated on a single N-type silicon substrate by well-known manufacturing techniques. Among these MOSFETs, M, 3 and M3. are of the deplexity type, and the rest are of the enhancement type.

The ROM circuits 2 and 3 have capacitors C, , connected to their respective output signals o, , O, by a clock pulse φX.
, Ct K MOSFET in ON state from negative power supply -VDD
MO82M0. precharged via. Then M
When OS FET Mor, Mat is turned off, the input signals are
The state of 2m determines whether the charge on capacitors C4 and C1 is discharged by the series path of MOSFETM+t to Mln and M,1 to M2m.

The gate of MOSFET M1 of the NOR circuit 4 is connected to the output terminal 0. of the ROM circuit 2. connected to MO8FETM
S! The gate of is connected to the output terminal 0° of the ROM circuit 3. The output terminal of the NOR circuit 4, that is, the load MO
S F E TMna and MOSFETM.

When at least one of M, I, and Ml is turned off, a negative power supply potential appears at the common connection terminal with.

The inverter circuit 5 inverts the output of the NOR circuit 4.

These circuits 2 to 5 provide the input signals A11 to Aln and the input signals 7 to 7 to the output terminals O5. When at least one of the two series-connected circuits consisting of MOS FET Mrs to Mln and M21 to M2m, which respectively receive signals A2m to A2m, is turned on, a ground potential appears at the output terminal Os.

The circuit of FIG. 3 has inputs 1. Aln and A2mK can respond simultaneously.

If the input signal is an address signal for a memory (not shown) and KL, m=n=12 as shown in the figure, one of An to Aln and person 2. to A2m, for example AII to Al.
n can be used as a decoder for addresses 0 to 2047@, and 1 to A2m can be used as a decoder for addresses 2048 to 4095.

In this way, in the method of dividing m + n MOSFETs into m and n, it is possible to divide into m:n, which is the combined resistance of m -) - n MOSFETs, so the connection between each output terminal OL, OL and ground The combined resistance of MOSFET can be reduced. If Km=n=12 as mentioned above, 24 MOs
The cost can be halved compared to when SFETs are connected in series.

On the other hand, a capacitor C is connected between the drain of MOSFET M1 and the semiconductor substrate. The capacitor C1 is composed of the pn junction capacitance between the source and the semiconductor substrate of l, and the capacitance between the gate and the semiconductor substrate of M□.
source, M2. drain and M5. is formed between the gate of the semiconductor substrate and the semiconductor substrate.

The capacitance values of these capacitors C, , C, are almost the same as C1 in FIG.

Therefore, the time constant of each time constant circuit formed by the source-drain resistance of the MOSFETs connected in series and the capacitors C1, C, in the ROM circuits 2 and 3 in FIG. This is almost half of what it would be without. Therefore, M OS F
Capacitor C,,C by E T Mos 2Mow
, after precharging inputs A11 to A sum and person1. or A2mK these capacitors〇i
, C, is approximately halved compared to the case where the circuit of FIG. 1 is used.

In the configuration shown in Figure 3, the idea of halving the discharging resistance of capacitors C,,C, by dividing K and series-connected MOSFETs in order to speed up the circuit can be further extended to the idea of dividing into three or four. should be obvious.

In FIG. 3, output terminal 0. Or 0. When either one of the terminals becomes ground potential, the output terminal 0. It was designed to output the K ground potential, but depending on the need, the output terminal OI
and Ot are at the same @ busy ground potential output terminal O8
It is also possible to output the K ground potential.

For such a request, a NAND circuit as shown in FIG. 4 can be used in place of the NOR circuit 4 in FIG. 3.

Further, in FIG. 3, for example, in the ROM circuit 3, when precharging the capacitor C2, MOSFET M! 1 to M2m are all on, a DC path is formed between the power supply "-VDD" and the ground. If such a DC path is not desired, K M OS F E as shown in Figure 5 is formed.
T M2 Between m and ground, M that turns off during precharging
OS FET Mos can be inserted.

In FIG. 3, the output 0. and 0. The circuit for synthesizing the two can be further changed to another circuit, and the inverter circuit 3 can be omitted depending on the required IL'.

FIG. 6 shows an example of application in which the configuration shown in FIG. 3 is used in a memory matrix.

In this example, as shown in the figure, the address decoder 3 and main matrix output blocks 4 to 6 are arranged vertically in two directions.
It is divided into parts and pressurized so that each part can be driven individually. That is, the first output block 41 as a memory matrix is connected to 4a and 4b, and the second output block 5 is connected to 53.
and 5bK, and further divides the third output block 6 into upper and lower stages, 6a and 6b, and stores the upper memory matrix (4a to 6b).
a) is driven by one of the two divided address decoders 3a, and the lower memory matrix (4b to 6b)
is driven by address decoder 3b. Then, the corresponding output of each memory matrix (4
The outputs of a and 4b, 5a and 5b, and 6a and 6b) are ORed and the output is V via ~L3. Take out as 1~■o.

In the ROM configured as described above, by selecting one of the two divided address decoders, the output block of either the upper or lower memory matrix can be operated by the selected address decoder. That is, for example, if the address decoder 3a is selected, the memory matrices 4a to 6a existing in the upper stage
You can get information from. If output block 4
When the output of a is 1'', that is, the ground potential, 1 level is taken out to its output line 0., and the output line 0. of the lower block 4b corresponding to this block is taken out. When is not selected, it is at O'' level (that is, negative potential), so it is an OR circuit.

output V. Similarly, when the output of the memory matrix 5a is 0, the OR gate circuit obtains a 0 level at the output v0., and when the output of the memory matrix 5a is 1, the level is V. , the L'' level is obtained.On the other hand, when the address decoder 3b is selected, the output blocks 4b to 6b of the lower memory matrix become operational.

In this way, when either the upper or lower output block is selected, the output of the selected block is obtained as the output of the gate circuit provided at the output point.

As is clear from the above description, the divided output blocks are individually driven.

Then, the number of FET0s connected in series to each divided memory matrix line is halved compared to the case where the memory matrix is not divided. Therefore, the discharge time of the memory matrix circuit is approximately halved, and the access time is therefore approximately doubled. In order to increase the speed, some OR circuits (Ll-, -L in Fig. 5) are added.
, ), and the additional area is almost negligible when viewed as a whole of the ROM, so it does not affect the degree of integration.

According to a preferred embodiment of the present invention, a second address decoder is inserted between the divided memory matrix and the precharge MOSFET. In this case, since the second address decoder can determine which column of the memory matrix is to be enabled or not, one precharge MOSFET can be associated with a plurality of columns of the memory matrix.

This method of using the second address decoder reduces the number of precharge MOSFETs and
The number of R circuits is also reduced.

The circuit using this second address decoder is the following seventh address decoder.
It will be understood by the embodiments shown in the figures.

In the example shown in FIG. 7, an example of a 4-kilogram ROM is shown.

In this figure, the connection relationship between the address decoder and the memory matrix section, which is a characteristic part of the present invention, is mainly shown. Other timing pulse application parts, output signal handling parts, etc. are not shown.

In the figure, the line depth is 0. As shown in Figure 9, an example of
The circle mark indicates that there is a second component ff1M08FET, and the arrow indicates the presence of MOS at the position indicated by this arrow.
Indicates that there is a FET gate line.

This example is written in a format with some parts omitted, but for one address input, 8-bit information vo1 to vo8
outputs.

3a is the first address decoder in the upper stage to which address signals 4 to A11 are applied;
547 ADo ~ MOS F for person D a a K
ETs are each arbitrarily connected in series. 3a□.

3aB is a second address decoder in the upper stage to which four address signals A0 to A are applied, and MO is applied to the data line.
SFETs are each optionally connected in series. Also, 3b
, is the first address decoder in the lower stage to which addresses No. 11 4 to AI8 are applied, and MOSFETs are arbitrarily connected to the address decode lines A D 64 to D , , .
Six rows are connected. 3b□.

3b! ! is a lower-stage second address decoder to which address decoders 0 to A3 are applied, and is composed of MOSFETs arbitrarily connected in series to the data line. Furthermore, 4a, 5
a is the output program of the upper memory matrix, and 4
b and 5b are output blocks of the lower memory matrix corresponding to the above-mentioned 4a and 5a. And output block 4a
, 4b are respectively output from address decoder 3 at+
+3bt+ is applied to the input point of the OR circuit RI, and the outputs of the output blocks 5a and 5b are respectively address decoders 3af2.3b! ! 1 is applied to the input point of the OR circuit RI through the output of the OR circuit RI or L6.
0° to V. Let @ be the ROM output. In addition, I.J.O.
+L and -L6 are inverters, and in particular, Lo is connected to the address line A11K located at the top stage, and is used to switch and operate the address decoders 3a1 and 3b.

The circuit shown in FIG. 7 is formed on the same semiconductor substrate. A plan view of the semiconductor substrate in the vicinity of address decode lines AD, s is shown in FIG. A sectional view taken along the line A-AK in FIG. 8, that is, a cross-section of a portion related to address decoding lines /A D and Is is shown in FIG. 8 BK.

In FIG. 8, the MOSFET is of a P-channel type and is fabricated on an N-type silicon substrate 10. In FIG. 8, the broken line indicates the P sub-region, the two-dot chain line indicates the polysilicon layer, and the solid line indicates the aluminum electrode. The one-dot chain line is an oxide film 31 or a silicon oxide film 3 formed by CVD method.
A hole is provided in 2 to bring the aluminum electrode into contact with the P subregion and the substrate or polysilicon layer.

The sources and drains of MOSFETs Q and Q are arranged horizontally in the drawing (this Q).

to Q are for address decoder 3aH). The source region 11 of Q is connected to the substrate 10 by the electrode 31.
and the drain region 12 is shorted to Q.

It has a common structure with the source area. Each P sub-area 11
There is a MOS on the optical surface of the substrate between the pairs of 30 to 30.
A thin oxide layer for the gate region of the FET is formed and processed. Above each gate area are 11 polysilicon dignitaries.

H+ A 4) φ work, AD, is extended.

In this example, QzQt are depression types and A, respectively. It is always on regardless of the signal level of one person. This depressi! I/WMOSFET is
Matrix 3aI in FIG.

3aH+ 3a*fi+ 3bI + 3J1+ 3b
ttp 4a.

4b, 5a: tct, Lhi5b are placed at intersections other than the intersection indicating the enhanced ff1M08FET marked with a circle.

The source/drain regions of FETQs=Q+s are arranged vertically in the drawing. This Qs *
Qlg is for memory matrices 4a and 5B.

According to the above ROM, the inverter L.

depending on which address decoder (3a1 or 3b
, ) is selected, the other address decoder becomes unselected. In addition, since the signal of one unit block is always read by the OR circuit, the ROM functions as a normal ROM and can achieve faster access time as described above.

As shown in FIG. 7, OR circuits LI and Lm are connected to block 4a.
, 5a, 4b, and 5b, the distance from which the output from block 4a and the output from block 4b are supplied to the OR circuit L1, and the distance from which the output from block 5a and the output from block 5b are provided to the OR circuit the law of nature.

The distance until K is supplied can be shortened.

This configuration reduces coupling noise, especially in so-called ratioless circuit configurations that are susceptible to undesired coupling via capacitance because the signal level is not determined by direct current but by the charge level of the capacitor. It is meaningful. The OR circuit in FIG. 7, IL, is a static circuit,
Each output is less susceptible to coupling noise.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made.

For example, in the above embodiment, each output block is divided into two, but it is also possible to divide it into more than that, and in such a case, the access time will be faster! It will be possible to achieve this goal.

Further, in the above embodiment, an OR circuit is used to select the outputs of the upper and lower output blocks, but the present invention is not limited to this, and the outputs of each block may be directly applied to the output circuit.

Further, as a selection means for the address decoders 3al and 3b, the uppermost address line (2048 bits between 8 and 2048
Although it is assumed that the address line is connected to the bit line A++, the connection is not limited to this and may be connected to other address lines. However, as mentioned above, address line A1. Needless to say, it is easier to divide the data if it is connected to the . That is, when the upper stage address decoders 3a, 3a, are selected, 2
046 bits or less are read out, and when the lower address decoders 3b, 3b are selected, 2046 bits or more are read out.

In addition, in order to obtain an FET that does not need to be switched by the potential of the gate electrode, all of the FETs are of the enhancement type as shown in Fig. 10, instead of the depletion type as shown in Fig. 8, and aluminum electrodes are used as needed. 31.
It is also possible to short-circuit the source/drain regions at 32. The method of FIG. 10 can reduce the resistance because the resistance of aluminum is much lower than that of the semiconductor region.

It goes without saying that the present invention is not only applicable to a 4-bit ROM as in the above embodiment, but also widely applicable to ROMs of other capacities.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional vertical ROM, FIG. 2 is a timing chart for explaining its operation, FIG. 3 is a circuit diagram of a vertical ROM divided into blocks, and FIGS. The figure is a circuit diagram of a modification of the circuit in Figure 3, Figure 6 is a block diagram of an application example of the circuit in Figure 3, Figure 7 is a circuit diagram of an embodiment, Figure 8 is a circuit diagram of a modified example of the circuit in Figure 3, and Figure 8 is a circuit diagram of a modified example of the circuit in Figure 3. Line AD when
, a plan view of the vicinity, FIG. 8B is a cross-sectional view of the person in the figure, FIG. 9 is a circuit diagram of the portion shown in FIG. 7, FIG. 10 is a cross-sectional view of another semiconductor integrated circuit, and FIG. The figure is a timing chart of FIG. 7. 1.3a, 3b, 3a+ +3atl+3a21+3
b,, 3b□, 3b□...Address decoder, 2?4
a+ 5a, 6a+ 4b, 5b+ 6b-"Memory matrix output block, 7...Flip-flop circuit, L0-L6...Gate circuit, Q, ~Q64+M
t~M,. ...FET. 1g: J 2nd Fig. 7m- Fig. 6 Fig. 7

Claims (1)

[Claims] 1. A first memory matrix including a plurality of first input lines, a plurality of first output lines, and a plurality of fixed memory elements, and an address signal of the plurality of first output lines. a first selection means for selecting a designated output line; a second selection means comprising a plurality of second input lines, a plurality of second output lines and a plurality of fixed memory elements;
a memory matrix, a second selection means for selecting an output line designated by the address signal from among the plurality of second output lines, and an output line selected by the first selection means of the first memory matrix and the second output line selected by the first selection means; and combining means for combining signals with the output lines selected by the second selection means of the two memory matrices, and the first and second selection means are connected between the first memory matrix and the second memory matrix. A semiconductor read-only memory characterized in that the synthesis means is arranged between the first selection means and the second selection means. 2. A patent characterized in that each of the output lines of the first and second memory matrices is composed of a plurality of MOSFETs connected in series with each other, and the first and second selection means are each composed of a plurality of switch MOSFETs. A semiconductor read-only memory according to claim 1. 3. Each of the first and second memory matrices is configured to operate as a ratioless circuit;
Common first precharge MOSFET for output line
is coupled to the first output line via the first selection means, and a common second precharge MOSFET for the plurality of second output lines is coupled to the second precharge MOSFET via the second selection means. 3. The semiconductor read-only memory according to claim 2, wherein the semiconductor read-only memory is coupled to an output line. 4. The first input line is coupled to the output of the first address decoding means, and the second input line is coupled to the output of the second address decoding means. Semiconductor read-only memory according to one of clauses 3. 5. According to claim 4, each of the first and second address decoding means is constituted by a plurality of MOSFETs connected in series and each of which is switch-controlled by an input address signal. semiconductor read-only memory. 6. The semiconductor read-only device according to claim 4 or 5, wherein the first and second address decoding means are configured to operate selectively in accordance with a predetermined address signal. memory.