JP2640000B2 - Address decoder - Google Patents

Description

The present invention relates to an address decoder for selecting one of word lines in a storage area such as a ROM by an address signal.

(B) Conventional technology A conventional address decoder will be described with reference to FIGS.

In FIG. 3, the address signal A ₀ .about.An, inverted address signal _A ^{* 0} _~A ^{* n} and the address decoder for inputting for inverting the address signal A ₀ .about.An by the inverter I ₀ ~In (2) Address signal a ₀ of the word lines Wa ₀ ~Waj corresponding to ~An state of activation, the plurality of memory cells connected to the activated word line of ROM matrix (3) (31a)
To (31d) are output in parallel to the bit lines (32a) to (32d). Incidentally, Lom matrix for reasons described later is divided into two parts, ROM matrix (4) by the address signal A ₀ .about.An also selected simultaneously. Therefore, each of the ROM matrices (3) and (4) outputs 4-bit data, or the ROM matrices (3) and (4) input the upper address signals An _{+ 1 to} An _{+ 2} by the selectors (5) and (6). ) And (4), or furthermore, addresses are selected in each ROM matrix, and 8-bit data is output from each of the ROM matrices (3) and (4).

The structure of the address decoder (2) configured as described above will be described focusing on the single word line.

In FIG. 4, a single word line of the address decoder (2) is composed of parallel P-channel MOSFETs (21φ) and (2φ).
1 ₀₎ ~ (21n), the series N-channel MOSFET (22φ) and (22 ₀₎ ~ (22n) and an inverter (23a) ~ (23b)
It is composed of

Parallel P-channel _{MOSFET (21φ), (21 0} ) ~ (21n)
A common drain region (24) of the drawing transversely formed by P ⁺ diffusion is also formed by the P ⁺ diffusion in the drawings laterally, the common source region (25) which is connected to the V _DD line, and the metal lines ( Clock φ supplied by a broken line.
(26φ) connected to the address signal lines A _{0 to} An
And gates (26 ₀ )-(26n) selectively connected to inverted address signal lines A ^* ₀ -A ^* n formed before and after these address signal lines A ₀ -An, respectively. Lines A _{0 to} An and inverted address signal lines A ^* _{0 to} A ^* n
The 2n channels formed underneath are masked so that a predetermined half of the channels are always turned off, and an address signal or an inverted address signal is selectively gated in the remaining half of the channels, and a predetermined address is input. The signal turns off all the parallel MOSFETs connected to the corresponding word line. The figure shows a P-channel MO
The gate of the _{SFET (21 0) (26 0} ) indicates an example that is connected to the inverted address signal lines A _0.

Also, series N-channel MOSFETs (22φ), (22 ₀ )
(22n) is a common source region formed by the P ⁺ diffusion of parallel P-channel MOSFET (24), the metal wiring is formed between the input and the V _SS line of the inverter (23a) via the polysilicon interconnection Masking is performed so that the source and drain of adjacent MOSFETs are common, and the channel below the predetermined half of the gate regions is always on. In this description, the masked portion is not counted as an element.

Next, the operation of the conventional address decoder will be described with reference to the equivalent circuit of FIG.

Given the unit circuits all gates are connected to the address signal lines A ₀ .about.An, thereby the word line in the address decoder is selected when all the address signal lines A ₀ .about.An becomes high level, the Parallel P-channel MOSFET (2
10 ₀ ) to (21n) are turned off simultaneously, and the series N-channel MOSFE
T (22 ₀ ) to (22n) are simultaneously turned on. Therefore, when the MOSFET (21φ) is turned off and (22φ) is turned on in synchronization with the clock φ, the word line is cut off from the _VDD line, and V _SS
Connected to the wire. As a result, the output of the inverter (23a) becomes high level, and the word line of ROM (3) is activated.

The address determination time of the address decoder is mainly governed by the time when the word line of the address decoder is set to low level by the N-channel series MOSFET.
ON resistance of N-channel MOSFET, Parallel P-channel MOSF
It becomes necessary to reduce the P ⁺ diffusion resistance of the source region of the ET and the parasitic capacitance C of the wiring and the load.

Therefore, as seen from the series N-channel MOSFET, the ROM region is divided into two as described above so that the load via the resistance of the source region formed by the P ⁺ diffusion of the parallel P-channel MOSFET does not increase. I have.

However, as a result, the conventional address decoder has a drawback that the address determination time of the ROM (3) and the ROM (4) divided into two parts is different from each other, and the address decoder can cope with an increase in the number of address signal lines for further increasing the capacity. It has disadvantages that cannot be achieved.

(C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and has been made in consideration of the above problem. An object of the present invention is to provide an address decoder which lowers effective resistance and operates at high speed. Another object of the present invention is to provide an address decoder that can cope with an increase in capacity.

(D) Means for Solving the Problems The present invention provides a series MOSFET formed between a word line and a first potential line, and a word line and a second potential line in a first region adjacent to the series MOSFET. A first parallel MO formed between the gates and gate-inputting one of the two divided address signals
It is characterized by comprising an SFET and a second parallel MOSFET formed between a word line and a second potential line in a second region adjacent to the series MOSFET and gate-inputting the other of the two divided address signals. .

(E) Operation The above configuration reduces the diffusion resistance of the common source region of the parallel MOSFET, which is the load of the series MOSFET, by half.
The time constant of the time constant circuit formed by the diffusion resistance and the parasitic capacitance is reduced to one half, so that the address determination time is reduced to approximately one half. Further, it acts to make the address determination time of a plurality of ROM mats equal.

(F) Embodiment One embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the single word line of the address decoder of the present invention is composed of a series N-channel MOSFET (22φ) and (22 ₀ ) to (22n), a first region adjacent to the series N-channel MOSFET. Of the first parallel P in which approximately half are formed
Channel MOSFETs (21 ₀ ) to (21n / ₂ ) and second parallel P-channel MOSFETs (21n / _{2 + 1} ) to (21n) which form the remaining half in the second region adjacent to the series N-channel MOSFET.
n) and (21φ), and inverters (23a) and (23b).

Series N-channel _{MOSFET (22φ), (22 0} ) ~ (22n)
Between the word line and the V _SS line, it is formed so that the source and drain of adjacent MOSFET is common to the gate address lines A ₀ .about.An or inverted address signal lines A ^* ₀ ~
A ^* n is selectively connected. However, a contact method is not a necessary condition in the present invention.

First and second parallel P-channel MOSFETs (21φ),
(21 ₀ ) to (21n) are divided into two and the serial N channels
_{MOSFET (22φ), (22 0} ) ~ formed on two regions adjacent to the (22n), and a common source region (24) formed by the P ⁺ diffusion in the drawings laterally, also the P ⁺ diffusion in the drawings laterally common drain region is formed, it is connected to V _DD by (2
5), and a gate (26φ) connected to a clock line φ formed of a metal line, address signal lines A _{0 to} An, and inverted addresses formed before and after these address signal lines A _{0 to} An, respectively. and it is configured to the signal ^{a _*} 0 ~A _* n from the gates selected connection _{(26 0) ~ (26n)} . An address signal line for supplying an address signal to the gate of the first parallel P-channel MOSFET is A _{0 to} An / ₂ and A
^* _{0 to} A ^* n / ₂ , the second parallel P-channel MOSFET
An address signal line that supplies an address signal to the gate of
/ _{2 + 1 to} An and the address signal line for inverting this are A ^* n /
_{2 + 1 to} A ^* n.

The operation of the embodiment will be described with reference to the equivalent circuit of FIG.

When the gates of all the MOSFET is a unit circuit connected to the address signal lines A ₀ .about.An is that all of the address signals A ₀ .about.An at the high level, the first parallel P-channel MOSFET (21
₀ )-(21n / ₂ ) and second parallel P-channel MOSFET
All the MOSFETs of (21n / _{2 + 1} ) to (21n) are turned off and the series N
All the channel MOSFETs (22 ₀ ) to (22n) are turned on. Here, the MOSFET (21φ) is turned off in synchronization with the clock φ,
(22φ) is by turning on the word line is cut off from the V _DD line, is connected to the V _SS line.

At this time, the electric charge charged to the one line and the parasitic capacitance C of the load is transferred to the first parallel P-channel MOSFET (2
_{1 0) ~ (21n / 2} ) are discharged through the diffusion resistance R of the common source regions of the other it is the second parallel P-channel MOSF
Diffusion resistance R of common source region of ET (21n / _{2 + 1} ) to (21n)
Is discharged through. Therefore, one word line has a parallel P-channel MO
Although the address determination time is longer than that of the conventional example in which no SFET is formed, the other word line has a diffusion resistance of the common source region that is one half, so that the other word line has a half time equal to the former one. The address is determined.

(G) Effects of the Invention As described above, according to the present invention, (1) the effective resistance of a word line can be reduced without performing high-level P ⁺ diffusion, and high-speed operation can be achieved.

(2) Since the effective resistance of the word line can be reduced without increasing the line width of the word line, high integration can be achieved.

(3) The address determination times of the two divided storage areas can be made the same.

Address decoder having such a remarkable effect can be provided.

[Brief description of the drawings]

FIG. 1 is a partial pattern diagram for explaining the structure of one embodiment of the present invention, FIG. 2 is a partial equivalent circuit diagram of one embodiment of the present invention, FIG. 3 is a block diagram of a conventional example, and FIG. FIG. 5 is a partial equivalent circuit diagram of a conventional example, illustrating a partial pattern diagram for explaining the structure of the example. (21φ), (21 ₀ )-(21n) …… Parallel P-channel MOSF
ET, (22φ), (22 ₀ ) to (22n) …… Series N channels
MOSFET, (23a), (23b) …… Inverter, (24) ……
Source region, (25) Drain region, (26φ), (26
₀ ) to (26n) ... gate, A _{0 to} An ... address signal, A
^* _{0 to} A ^* n: inverted address signal, C: parasitic capacitance,
R: diffusion resistance.

Claims (1)

(57) [Claims] 1. A series MOSFET formed between a word line and a first potential line and gate-inputting an address signal;
A first parallel MOSFET formed between a word line and a second potential line in a first region adjacent to the SFET and gate-inputting one of two divided address signals; and a second region adjacent to the series MOSFET An address decoder comprising a second parallel MOSFET formed between a word line and a second potential line and gate-inputting the other of the two divided address signals.