JPH02246095A - Address decoder - Google Patents

Abstract

PURPOSE:To obtain an address decoder which can cope with mass capacity by equalizing the time constant of a time constant circuit forming of a diffused resistor and parasitic capacity to an address determined time. CONSTITUTION:Charge in parasitic capacitor C of wiring and a load is discharged through a diffused resistor R in the common source area of first parallel channel MOSFETs 210 to 21n/2, and the other charge is discharged through the diffused resistor R in the common source area of a second parallel P channel MOSFETs 21n/2+1 to 21n. Consequently although the address determined time of one word line is extended due to the addition of the diffused resistor, for the other word line, since the diffused resistor of the common source area is reduced by half, the address is determined approximately in a half time which is equivalent to the former time. Thus the increase of the address signal lines for the mass capacity can be coped with.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application This invention relates to an address decoder that selects one of the word lines in a storage area such as a ROM based on an address signal.

(b) Prior Art A conventional address decoder will be explained with reference to FIGS. 3 to 5.

In FIG. 3, the address signals A, ~An and the address signals A, ~An are inverted! , ~In inverts the inverted address signal A8. The address signal ``da (2) inputting ~A''n activates the word lines W a and ~Waj corresponding to the states of the address signals A0~An, and activates the activated word line of the ROM matrix (3). The states of a plurality of memory cells (31a) to (31d) (7) connected to each bit line are output in parallel to each bit line (32a) to (32d).

Note that the ROM matrix is divided into two parts for reasons to be described later, and the ROM matrix (4) is also selected at the same time by these address signals A, .about.An. Therefore, each ROM matrix (3), (4) outputs 4-bit data, or the upper address signals An+, ~A tl,
Select ROM matrices (3) and (4) using selectors (5) and (6) that input =, or select addresses within each ROM matrix to select from ROM matrices (3) and (4). Each outputs 8-bit data.

The structure of the address decoder (2) constructed as described above will be explained by focusing on its single word line.

In Figure 4, a single word line of the address decoder (2) is connected to a parallel P-channel MOSFET (21φ) and (21*) to (21n), a series N-channel MOSFET
ET (22, d) and (2L) to (22n) and inverters (23a) and (23b).

Parallel P-channel MOSFET (21φ), (21,)
~(21n) is a common drain region (24) formed by P0 diffusion in the horizontal direction of the drawing, and a common drain region (24) formed by P4 diffusion in the horizontal direction of the drawing.
A common source region (25) formed by diffusion and connected to the vDD line, and a metal line (shown as a dashed line).
Gate (26φ) connected to clock φ supplied by
, address signal lines A, ~An, and this address signal line A
, ~An, respectively, are formed one after the other, and gates (26, 26,
) to (26n), and address signal lines A, to A
n and inverted address signal line A0. The 2n channels formed at the bottom of ~A”n are masked so that a predetermined half of the channels are always turned off, and the remaining half of the channels are selectively gated with an address signal or an inverted address signal. The parallel MOSFETs connected to the corresponding word line are all turned off by a predetermined address signal.The figure shows the P channel M
An example is shown in which the gate (26@) of OS FET (21,) is connected to the inverted address signal line A.

Also, a series N-channel MOSFET (224).

(22*) to (22n) are parallel P channel MO3FE
A common source region (24
), the input of the inverter (23a) and V via the metal wiring and -polysilicon wiring. It is formed between the line and
Adjacent MOSFETs are masked so that their sources and drains are common and the channels under a predetermined half of the gate regions are always on. Note that in this explanation, masked locations are not counted as elements.

Next, the operation of the conventional address decoder will be explained with reference to the equivalent circuit shown in FIG.

Considering a unit circuit in which all gates are connected to address signal lines A, ~An, the word lines in the address decoder that are selected by this are connected to all address signal lines A, ~An.
becomes high level, its parallel P channel M O
S FET (21m) to (21n) are turned off at the same time, and the serial N channel MOS FET (22
*) to (22n) are turned on at the same time. Therefore, MOSFET (214) is turned off in synchronization with clock φ, and MOSFET (22
4") is turned on, the word line is cut off from the v0 line and connected to the VSS line. As a result, the output of the inverter (23a) becomes high level and the word line of the ROM (3) is activated.

The address determination time of the address decoder mentioned above is mainly controlled by the time when the word line of the address decoder is brought to a low level t by the N-channel series MOSFET, and the on-resistance of the N-channel MO3FET and the parallel P
It becomes necessary to reduce the P''' diffusion resistance in the source region of the channel MOSFET and the parasitic capacitance C of the wiring and load.

Therefore, from the perspective of the series N-channel MOSFET, the ROM region is divided into two as described above so that the load through the resistance of the source region formed by P0 diffusion of the parallel P-channel MOSFET does not become large. .

However, as a result, the conventional address decoder has the disadvantage that there is a difference in address determination time between ROM (3) and ROM (4), which are divided into two parts, and it is not possible to cope with an increase in the number of address signal lines required for further increasing the capacity. It has its drawbacks.

(c) Problems to be Solved by the Invention The present invention has been made in view of the above points, and it is possible to solve the problem in the source region of a parallel MOSFET without widening the word line width or high-level diffusion. An object of the present invention is to provide an address decoder that can reduce effective resistance and thereby operate at high speed. Another object of the present invention is to provide an address decoder that can handle increased capacity.

(d) Means for Solving the Problems This invention provides a series MOSFET formed between a word line and a first potential line, and a series MOSFET formed between a word line and a second potential line in a first region adjacent to the series MOSFET. A first parallel MO3FET is formed between the word line and the second potential line in a second area adjacent to the series MO3FET, and the first parallel MO3FET is formed between the word line and the second potential line and is divided into two. It is characterized by comprising a second parallel MOSFET whose gate inputs the other address signal.

(E) Effect The above configuration is a parallel MOS that becomes the charge of the series MOSFET.
By reducing the diffused resistance in the common source region of the FET to 1/2, the time constant of the time constant circuit formed by this diffused resistance and parasitic capacitance is reduced to 1/2, thereby reducing the address determination time to approximately 2 minutes. It acts to make it 1. Furthermore, it acts to equalize the address determination time of a plurality of ROM matrices.

(f) Example Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG.
φ) and <2z, )~(22n), a first parallel P-channel MOS FET (approximately half of which is formed in the first region adjacent to this series Nl channel MOSFET)
21a) to (21n/#), a second parallel P-channel MOSFET (21n/#), the remaining half of which is formed in the second region adjacent to the series N-channel MO8FE, T
/m-t) to (21n) and (214), and inverters (23a) and (23b).

Series N-channel MOSFET (22φ”), (2
2,) to (22n) are word lines and V. Adjacent MOSFETs are formed between the lines so that their sources and drains are common, and an address signal (!) is sent to their gates. ilA.

~An or inverted address signal lines A'' and ~A''n are selectively connected. However, in this invention, the contact method is not a necessary condition.

First and second parallel P-channel MOS FET (
21φ) = (21e) to (21n) are divided into two to form the series Nf”r channel MO3FET (22φ),
A common source region (24) is formed in two regions adjacent to (22v) to (22n) and is formed by P''' diffusion in the horizontal direction of the drawing, and a common source region (24) is also formed by P+ diffusion in the horizontal direction of the drawing and is formed in vo. Common drain region (2
5), a gate (26φ) connected to the clock line φ formed by a metal line, address signal lines A, ~An, and inverted addresses formed one after another on the address signal lines A, ~An, respectively. Signal line A0. ~A''n) (26e) to (26n) selectively connected to A"n. Note that the address signal line that supplies an address signal to the gate of the first parallel P-channel MOSFET is A, ~A"n.
An8 and Ao which inverts this, ~A*n8,
The address signal lines that supply address signals to the gates of the second parallel P-channel MOSFET are Ann+1 to An, and the address signal lines that invert this are A11n8, 1 to
A”n.

The operation of the embodiment will be explained with reference to the equivalent circuit shown in FIG.

The gates of all MOSFETs are connected to the address signal line A~A
The unit circuit connected to n receives all address signals A, ~A
When n becomes high level, the first parallel P-channel MOSFET (21*) to (21n8) and the second parallel P-channel MOSFET (21n8-+)
All MOSFETs ~(21n) are turned off, and the series N-channel MOSFET (22*) ~(22
n) are all turned on. Here, in synchronization with clock φ, M
By turning off OSFET (21φ) and turning on OSFET (22φ), the word line is cut off from the v0 line and connected to the VSS line.

At this time, the charge stored in the parasitic capacitance C of one wiring and the load is transferred to the first parallel P-channel MOSFET.
E T(21=) to (21n8) are discharged through the diffused resistance R of the common source region, and the other one is discharged through the second parallel P
Channel MOS FET (21n/*-t
) to (21n) are discharged through the diffused resistor R of the common source region. Therefore, one word line is connected to a parallel P-channel MO3FE by adding a diffusion resistor.
Although the address determination time is longer than in the conventional example in which T is not formed, the other word line can be fixed in about half the time as the former because the diffusion resistance of the common source region is halved. The address is confirmed.

(G) As described in detail, according to the present invention, (1) the effective resistance of the word line can be lowered without high-level P'' diffusion, and high speed operation can be achieved.

(2) Since the effective resistance of the word line can be lowered without increasing the line width of the word line, it is possible to cope with high integration.

(3) The address determination time of the two divided storage areas can be made the same.

It is possible to provide an address decoder that achieves this remarkable effect.

[Brief Description of the Drawings] Fig. 1 is a partial pattern diagram explaining the structure of an embodiment of this invention, Fig. 2 is a partial equivalent circuit diagram of an embodiment of this invention, and Fig. 3 is a block diagram of a conventional example. 4 are partial pattern diagrams for explaining the structure of the conventional example, and FIG. 5 is a partial equivalent circuit diagram of the conventional example. (211) −(21J~(21n)...Parallel P-channel MOSFET, (22φ), (22=
) ~ (22n) ...Series N channel MOS F
E T , (23a), (23b)” inverter, (24) source region, (25) drain region, (26φ) −(2L) to (26n)=
Gate, A, ~An...address signal, A1. ~
A"n...inverted address signal, C...parasitic capacitance,
R...Diffusion resistance.

Claims (1)

[Claims] (1) A series MOSFET formed between the word line and the first potential line and inputting the address signal to the gate, and this series MOSFET
A first parallel MOSFET formed between a word line and a second potential line in a first region adjacent to the OSFET and inputting one of the two divided address signals as a gate input, and a second region adjacent to the series MOSFET. An address decoder comprising a second parallel MOSFET formed between the word line and the second potential line in which the other divided address signal is input to the gate.