JPS60101798A - Semiconductor read-only memory - Google Patents

Abstract

PURPOSE:To shorten an access time through simple constitution by dividing address decoders and memory matrixes into an optional numbers of blocks, and driving the respective blocks individually. CONSTITUTION:Output blocks of memory matrixes are each divided into two upper and lower stages, i.e. 4a and 4b, 5a and 5b, and 6a and 6b; and the upper- stage memory matrixes 4a-6a are driven by one of two divided address decoders, i.e. 3a, and the lower-stage memory matrixes 4b-6b are driven by the other address decoder 3b. Then, respective outputs of corresponding output blocks of memory matrixes are led out through OR circuits L1-L3 as outputs V01-V03. One address decoder is selected to operate either of the upper and lower output blocks in this ROM.

Description

[Detailed description of the invention]

The present invention relates to a semiconductor read-only memory (hereinafter referred to as 1tOM), and particularly relates to an ItOM in which a plurality of insulated gate field effect transistors (hereinafter simply referred to as FETs) are connected in series to one output line. (Such a system is called a vertical ITOM). As a vertical type ROM, Japanese Patent Application No. 1973-107350
There is something similar to what was proposed. An example of this is shown in Figure 1.
. In this example, a capacitor C1 is connected between the output terminal ADo and ground, and M
MO5FET MI or M is connected in parallel with the capacitor C1 between the output terminal and ground. are connected in series.
The MO8FETM or Mn connected in series acts as a switch for precharging the input A1 (
・Works as a switch that receives ShiAn. In this example, M.O.
8FETM is a depletion type, and is turned on regardless of the potential of the gate electrode receiving input A. That is, a current path is formed between the source and drain of M. On the other hand, M Ob F E T M+
1Mn-32Mn is an enhancement type, and is turned on and off depending on the gate potential. Therefore, output terminal AIJ
Connect the above amplifier type MUSFET between O and ground.
If all of them are on, a current path is created, and if any one is off, a current path is created.

[
stomach. In this example, as shown in the time chart of FIG. 2, first, the clock signal φ8 becomes a negative potential -VI)D, so that p='rMn is turned on, and the capacitor 〇 is charged and amplified. Next, the level of the clock signal φ returns to the ground potential GND. At this time, the level of the clock signal φ returns to the ground potential GND.
If only one of n is off, the charge of capacitor C3 will not be discharged. Therefore, both ends of capacitor C1 maintain the same voltage when precharged. FETM, '/;rl,・If a current path is created in all of Mn, the charge in capacitor 〇 will be discharged.The voltage across this capacitor CI- will eventually become zero.In this circuit, one of F E TM or Mn If it is off, there is no change in the precharged charge of capacitor 〇, so it is okay to use the output signal from output terminal ADO immediately after precharging.However, if there is no current in Ml or M. When a path is formed, the charge of capacitor C1 after precharging does not immediately become 0 (. At this time, the capacitor is connected in series between the source and drain of FET M + -tx and Mn in the on state. The output terminal AD becomes short-circuited due to the resistor connected to the
It takes time t for the number one city of o to reach an appropriate value. Therefore, the next circuit (not shown) connecting the output terminal ADO to the input terminal is made to receive the input signal 11 hours after the circuit of FIG. 1 has been precharged. In the circuit shown in Fig. 1, the logic for the input A or An can be arbitrarily changed by reductively changing the MOSFET connected in series between the output terminal A Do and the ground to an amplifier type or depletion type. . This method of changing the logic is suitable when configuring a ROM using MOSFETs arranged in matrix. For example, among MOSFETs arranged in a matrix, the sources and drains of MOSFETs arranged in a column direction are connected in series, and a plurality of input wirings are used as gate electrodes in the direction of direct firing with this column, for example, A and F in FIG. r Ishi An and φ
8 and select one of the above MO8FETs to be a depression type. In this way, desired logic outputs can be extracted from each column of the matrix arrangement. The example in Figure 1 is also a power source. Since current flows only when the clock pulse φ8 becomes a negative potential, power consumption is low. However, when many MOSFETs are connected in series in order to receive many input signals, this circuit increases the source-drain resistance of the series-connected MO8FETs. It is necessary to increase the amount of time it takes to obtain a signal of sufficient level at the output terminal. In other words, the access time becomes longer. Therefore, it is an object of the present invention to provide a ROM with faster access time. Another object of the present invention is to provide a ROM that has a simple configuration and can achieve faster access times. In order to achieve the above object, the present invention requires series connection of M
The OS FET is divided into groups, and the output signals from the groups are later combined. Examples will be described below. In FIG. 3, 2 is a first tOM circuit, 3 is a second ROM circuit, 4 is a NOR circuit, and 5 is an inverter. The ROM circuit 2 has an MO for precharging the capacitor C8 between the output terminal OI and the negative power supply -vr)D.
S F E T M O+ is connected, and M O S F E T M ++ is connected between output terminal OI and ground.
n are connected in series (・ru. M OS F E TMo
+ is connected to the terminal for clock pulse φ, and the gates of MO8FETM, . It is connected to a terminal for receiving Aln. ROM circuit 3 has MO8FE for precharging capacitor 〇, between output terminal O3 and negative power supply -VDD.
TMoz is connected and MO8F is connected between output terminal O7 and ground.
ETM2. or M2. are connected in series. pJj
The gate of Q S F E T M at is connected to the terminal for clock pulse φ8, MO8FETM, I
The 2m gates are connected to terminals for receiving input signals A41 to A2tn, respectively. In this example, a limitation of the present invention is that the antenna L is
These MOSFETs are of P-channel type and are fabricated on a single N-type silicon substrate using well-known manufacturing techniques.
is is of the depression type, and the rest are of the enhancement type. The ROM circuits 2 and 3 output their respective output signals 0. ．． 0. capacitor C connected to
, C, is turned on from the negative power supply.
Precharged via OI and Mow. Next(·
When MOS FET MOI 1MO2 is turned off, input signals A H1 to Aln and A7 . Depending on the state of A2rn, capacitor 〇, and C2
The charge of MO8FETM, 1. It is determined whether the discharge is caused by a series path of rl, . The gate of MO8FETM of NOR circuit 4 is ItO
Connected to output terminal O1 of M circuit 2, MO8FE T
The gate of M u is connected to the output terminal 02 of the ROM circuit 3 . NO) to the output terminal of circuit 4, i.e. the load MOSFETMss and MO8FETM32
The common connection terminals with M, 1 and M, ! If at least -1 of is off, a negative power supply potential appears. The inverter circuit 5 inverts the output of the NOR circuit 4. These circuits 22. C.5, the output terminal O8 has the following:
Input signals A11 to Am and A7. ℃・shi A2m
MO8FETM, , 7;c and Mlo receiving respectively
When at least -1 of the two series-connected circuits consisting of M21 and M2m is turned on, a ground potential appears at the output terminal 03. This third circuit has inputs All (・Am and A2
．． It is possible to respond to A2m or A2m at the same time. If the input signal is an address signal for a memory (not shown (.) and rn:==n=12 as shown in the figure, then one of A to Aln and A7.L- to A2
For example, by controlling the pair with one of m, A
llna(・しA, n()na l, - 204.7@ for the decoder for ground and [2, A?, una u− then A2Tn for 2
It can be used as a decoder for addresses 048 to 4095. In this way, in the method of dividing man MOSFETs into m and n, the combined resistance of man MOSFETs can be divided into man, so each output terminal 0+
-The combined resistance of the MOS FET between Ot and ground can be reduced. As mentioned above, m-It-12 can be halved compared to the case where 24 MOSFETs are connected in series. On the other hand, capacitor C4 is M OS F E T M
The capacitor C2 is composed of the pn junction capacitance between the drain of u and the semiconductor substrate and the source of MOI and the semiconductor substrate, and the capacitance between the gate of M3I and the semiconductor substrate. , the drain of M21 and the source of M8.
is formed between the gate of the semiconductor substrate and the semiconductor substrate. The capacitance value of each of these capacitors C, , C, is almost the same as CI in FIG. The time constant of each time constant circuit formed by the capacitors C, ,C, and the capacitors C, ,C, is approximately half that of the case where m + n FETs are not divided.Therefore, the MOS
After precharging the capacitors C,, C, by F E T M o+ −M nt, the input A 11
The time it takes for the charges in these capacitors C, , C, to discharge to a desired level is reduced by about half compared to the case where the circuit shown in FIG. 1 is used. In the embodiment shown in FIG. 3, in order to increase the speed of the circuit, the capacitor C is divided by dividing the series-connected MOSFET.
The idea of halving the discharge resistance of ,,C, is to further divide it into three parts,
It will be clear that it can be extended to the idea of four divisions. In FIG. 3, the output terminal OI or 0. Any of -
When the ground potential is reached, the ground potential is output to the output terminal O8, but if necessary, the output terminal 01
and O3 become ground potential at the same time, output terminal 03
It is also possible to output a ground potential to the terminal. In response to such a request, a NAND circuit as shown in FIG. 4 can be used in place of the NOR circuit 4 in FIG. 3. In addition, in FIG. 3, for example, in the tOM circuit 3, KMO8FE'l"M when precharging the capacitor C2
□P, C℃・ShiM 2. n turns on all 1 (・rototS
. - A DC path is formed between vDD and ground. If such a direct current path is not desirable, use the M O
A MOS FET M os that turns off during precharging can be inserted between the S F E T M 2m and the ground. In FIG. 3, the circuit for combining the outputs OI and O7 can be further changed to another circuit, and the inverter circuit 3 can be omitted if necessary. FIG. 6 shows an example of application in which the embodiment of FIG. 3 is used in a memory matrix. In this example, as shown in the same figure, the address decoder 3 and main matrix output blocks 4 to 6 are placed on top 1 and 2, respectively.
Divide them so that they can each be driven individually. That is, the first output block 4 of the memory matrix is
a and 4b, the second output block 5 is divided into 53 and 5b, and the third output block 6 is divided into 6a and 6b into two stages, upper and lower, and the upper memory matrix (48 to 6a) is divided into two stages.
It is driven by 10,000 address decoders 3a among the divided address decoders 3a, and the lower memory matrix (4b to 6b) is driven by the address decoder 3b. Then, the corresponding output blocks of each memory matrix (4a and 4b, 5a and 5b + 6a and 6b
) to the OIL circuit and output v-vo through ~L.
Take it out as 3. In the tOM of the present invention having the above configuration, by selecting one of the 10,000 address decoders divided into two, the output block of either the upper or lower memory matrix is operated by the selected address decoder. I can do it. That is, for example, the address decoder 3a
If is selected, information from the memory matrices 4a to 6a located in the upper row can be obtained. Assuming that the output of the output block 4a is "1", that is, the ground potential, the output line 0. 1” level is taken out, and the output line 02 of the lower block 4b corresponding to this block is
When ℃ is not selected, it is at the "0" level (-f, that is, negative potential) (the output V.1 of the JR circuit L1 is "
°1" level is obtained. Similarly, when memory matrix 5a is 00, 0-
The N On level is obtained at the output Vo of the Itgegoo circuit L2, and when 6a is 1, ■o becomes the "1" level. Furthermore, when the address decoder 3b is selected, the output blocks 4b to 6b of the lower memory matrix become operable. In this way, when one of the upper and lower output blocks is selected, the output of the selected block is obtained as the output of the gate circuit provided at the output point. As is clear from the above, according to the present invention, the divided output blocks are driven individually.Then, the FETs are connected in series to the lines of each divided memory matrix.The number is not divided. Therefore, the discharge time of the memory matrix circuit is approximately halved, and the access time is also approximately doubled. Add some OR circuits (see Figure 5, ~L,) for
The additional cost is negligible when looking at the ROM as a whole, so it does not affect the accumulation history. According to another example of the present invention, a second address decoder is inserted between the divided memory matrix and the precharge MOS 1"ET. In this case, the second address decoder determines which part of the memory matrix Since it is possible to decide whether or not to enable a column, one precharge MO8FET can be associated with multiple columns of the memory matrix.The method of using this second address decoder allows the number of precharge MO3FETs to be While decreasing the above O
The number of RIφJ paths is also reduced. The circuit using this second address decoder is the following seventh address decoder.
The embodiment shown in the figure will be completed. In the example of FIG. 7, a 4 kilobit ROM is shown. In this figure, the connection relationship between the address decoder and the memory matrix section, which is a characteristic part of the present invention, is mainly shown. Other timing pulse marks 〃o parts, output signal handling parts, etc. are shown in the figure (・na℃・. In the figure, an example of the line A D as is shown in FIG. 9, and the circles indicate enhancement type MO8FETs. The arrow indicates that the M OS is present at the position indicated by this arrow.
F E Indicates that there is a 'I' gate line. This example is written in a format with some parts omitted (・For one address input, 8-bit information vn+B I (・V.8 is output. Address signals A4 to A11 are applied to 3al. M(JS FETs are arbitrarily connected in series to the address decode line ADo=AD6A. 3a2... 3a22 is the four address signals A. -A3 is the mark ZIDg.
MOSFETs are connected in series to the data lines, respectively. Further, 3b is a first address decoder in the lower stage to which address signals A4 to A11 are marked 7JD, and MOSFETs are arbitrarily connected in series to address decode lines AIJ64 to AD127. 3b2. . 3b22 is an address decoder of the lower cylinder 2 to which the address signal Ao"Aj is applied, and is composed of MOS F E '1' arbitrarily connected in series to the data line.Furthermore, 4a and 5a are output blocks of the upper stage memory matrix. 4b and 5b are the output blocks of the lower memory matrix corresponding to the above 4a and 5a.The outputs of the output blocks 4a and 4b are respectively sent to the address decoder 3.
a211 3b2. The outputs of the output blocks 5a and 5b are applied to the input point of the OIt circuit via the address decoder ``a22+31)22'', respectively.
applied to the input point of the circuit. OR circuit L1 (・
The output V of Shiri. 1? , C ■. 8 is the output of It OM. Note that L+++L4 to Lo are inverters, and in particular, Lo is the address line All located at the top stage.
℃, address decoder 3a, and 31) 1
This is for switching and operating. The circuit shown in FIG. 7 is formed on the same semiconductor substrate. FIG. 8A is a plan view of the semiconductor substrate near the address decode line AD63. A cross-sectional view of FIG. 8 A, -, A', that is, a cross section of a portion related to the address decode line AD ns is shown in FIG. 8 I]. It is a P-channel type and is fabricated on an N-type silicon substrate.
For Japanese nationals, the dashed line indicates p gal + button area (1,
The two-dot chain line indicates the polysilicon layer, and the solid line indicates the aluminum electrode. The chain line to -7 indicates a portion where a hole is provided in the oxide film 31 or the silicon oxide film 32 formed by the CVD method to bring the aluminum electrode into contact with the P-type head region and the substrate or polysilicon layer. Mo5rETq, the source and drain of Q7 are arranged horizontally in the drawing (Q through Q7 are for the address decoder 3a). The source region 11 of Ql is connected to the substrate 10 by the electrode 31.
When short-circuited, the drain region 12 has a common structure with the source region of Q2. Each P-type head area 11℃・30
MO8FE'l' is on the surface of the substrate between the pair of
A thin oxide film is formed for the gate region. On each gate region there is a polysilicon layer A,..., Al0I
A4 g φ, t AD', 3 is extended. In this example, Q, ,Q7 are depression types, and A, respectively. , A4 are always on, regardless of the signal level. This depression type MO8FET is
Matrix 3a in FIG. 3aH+ 3at2* 3bl t 3b2Iv 3F
1*4at4b, 5a and 5I) are placed at the intersections other than those marked with circles indicating the enhanced MO8FETs. The source and drain regions of F E T Qs and Q10 are arranged vertically in the drawing. This Qa * Q
10 is for the memory matrix 4ae5a. According to the above ROM, the inverter L. Depending on the address decoder (3a or 3)
b1) is selected, the other address decoder becomes non-selected. Also, depending on the OR circuit L and
Since the signals of one unit block are read out, it has the function of a normal tOM, and as mentioned above, it can speed up the access time.
becomes. The present invention is not limited to the above embodiments, and various modifications can be made. For example, in the above embodiment, each output block is divided into two parts, but it is also possible to divide each output block into two parts. In such a case, the access time can be further increased. In addition, in the above embodiment, the circuit 0) is used to select the output of the upper and lower output blocks. Furthermore, address decoder 3a+to 3b, I:Y;
As f4 selection means, inverter L is connected to the topmost address line (8I (line of 2048 bits, which is the middle of bits) A1. with the largest weight, but this is not limited to this, and other addresses can also be connected. However, it goes without saying that connecting to the address line AI+ as described above makes it easier to divide.In other words, when the upper stage address decoder "31w3a2" is selected, the bits of 2046 bits or less is read out,
When the lower address decoders 3b, 3b are selected, 2046 bits or more are read out. Also, there is no need to switch depending on the potential of the gate electrode (
・In order to obtain an FET, everything is not a depression type as shown in FIG. 8, but an enhancement type as shown in FIG. 10, and the aluminum electrode 31 is connected as necessary.
．． It is also possible to short-circuit the source/drain regions at 3'2 to -3-5. The method of FIG. 1O can reduce the resistance because the resistance of aluminum is much lower than that of the semiconductor region. It goes without saying that the present invention is not only applicable to 4-bit ROMs as in the above embodiment, but also widely applicable to ROMs of other capacities.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional vertical LOM;
The figure is a timing chart for explaining its operation, Figure 3 is a circuit diagram of one embodiment of the present invention, Figures 4 and 5 are circuit diagrams of modifications of Figure 3, and Figure 6 is the circuit diagram of a modification of Figure 3. 7 is a block diagram of an application example of the circuit, FIG. 7 is a circuit diagram of another embodiment, and FIG. 8A is a block diagram of an application example of the circuit.
8B is a sectional view taken along A-A' of FIG. 7, and FIG. 9 is a circuit diagram of the portion shown in FIG. 7. The figure is a cross-sectional view of another semiconductor integrated circuit, and FIG. 11 is the timing chart of FIG. 7.
3b1, 3b21- 3b,...address decoder, 2゜4a, 5a* 6a* 4bt 5b, 6b...
・Memory matrix output block, 7°°° flip-flop circuit, Lo "'-Ls"' gate circuit, Q
r ~Q641 MH~M,. ...FET. No. 1121 No. 21°・1

Claims (1)

[Claims] 1. In a semiconductor read-only memory in which an address decoder and a memory matrix formed in a vertical ltOM are formed on the same semiconductor substrate, the address decoder and memory matrix can be formed in any number of pieces. A semiconductor read-only memory characterized by being divided into blocks and driving each block individually. 2. The semiconductor read-only device according to claim 1, characterized in that a gate circuit is provided at the output point of the divided blocks, and the output signal of any one block can be extracted from the gate circuit. memory. 3. Claim 1, characterized in that an inverter is connected to at least one address line Kit column among the address lines connecting the divided address decoders, thereby individually driving the address decoders. Or 1 liter of semiconductor read-only memory as described in paragraph 2.