JPH0320839B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor read-only memory (hereinafter referred to as
In particular, it relates to ROMs in which multiple insulated gate field effect transistors (hereinafter simply referred to as FETs) are connected in series to one output line (such devices are referred to as vertical type ROMs). of
(referred to as ROM).

For vertical type ROM, patent application No. 107350
There is something like the one proposed in JP-A No. 52-30388. An example is shown in FIG.

In this example, capacitor C ₁ is connected between the output terminal AD ₀ and ground, MOSFET M ₀ is connected between the negative power supply -V _DD and the output terminal, and MOSFET M 0 is connected between the output terminal and ground in parallel with the above capacitor C ₁ . MOSFET
M ₁ to M _o are connected in series. MOSFET
M ₀ acts as a switch to precharge the capacitor C ₁ above, and is connected in series.
MOSFETs M ₁ to M _o act as switches receiving inputs A ₁ to A _o . In this example MOSFET
_M2 is of the depletion type and remains on regardless of the potential of the gate electrode that receives input _A2 .
That is, a current path is formed between the source and drain of _M2 . On the other hand, MOSFET M ₁ ,
M _o-1 and M _o are enhancement type, and are turned on and off according to their gate potentials. Therefore, the above enhancement type is connected between output terminal AD ₀ and ground.
If all MOSFETs are on, a current path is created, and if any one is off, no current path is created.

In _this example, as shown in the time chart in Figure ₂ , first _, the clock signal _φ
The charge is increased. Next, when the _level of _{the clock} signal _φ The charge on C ₁ is not discharged. Therefore, the voltage across the capacitor _C1 remains as it was when it was precharged.

If a current path is established in all of FETs M ₁ to M _o , the charge in capacitor C ₁ will be discharged. The voltage across this capacitor _C1 eventually becomes zero.

In this circuit, one of the FETs M ₁ or M _o
If it is off, there is no change in the precharged charge of the capacitor _C1 , so it is okay to use the output signal from the output terminal _AD0 immediately after precharging.

However, when a current path is formed between M ₁ and M _o , the charge of capacitor C ₁ after precharging does not immediately become zero. That is,
Since the capacitor C ₁ is short-circuited by the series resistance between the source and drain of the FET M ₁ or _Mo in the on state, the potential of the output terminal AD ₀ becomes an appropriate value depending on the input A ₁ or A _o . It takes time _t1 .

The next circuit (not shown) connecting the output terminal AD ₀ to the input terminal is therefore made to receive the input signal t ₁ after the circuit of FIG. 1 has been precharged.

The circuit in Figure 1 uses the input voltage by selectively setting the MOSFETs connected in series between the output terminal AD ₀ and ground to the enhancement type or depletion type.
The logic for A ₁ to A _o can be changed arbitrarily.

This method of changing logic is suitable when configuring a ROM using MOSFETs arranged in a matrix. For example, MOSFETs arranged in a matrix
The sources of MOSFETs arranged in the column direction
The drains are connected in series, and a plurality of input wirings serving as gate electrodes, such as A ₁ to A _o and _φ
Among the MOSFETs, the one selected is of the depletion type. In this way, desired logic outputs can be extracted from each column of the matrix arrangement.

The example shown in FIG. 1 also has low power consumption because current only flows to the power supply _-VDD when the clock pulse _φX becomes a negative potential.

However, when many MOSFETs are connected in series to receive many input signals, this circuit increases the source-drain resistance of the series-connected MOSFETs. It is necessary to increase the time required to obtain a level signal. In other words, the access time becomes longer.

An object of the present invention is to provide a ROM with faster access time.

Another object of the present invention is to provide a ROM that has a simple configuration and can achieve faster access times.

Another object of the present invention is to provide a ROM suitable as an integrated circuit device.

According to the invention, MOSFETs requiring series connection
is divided into multiple groups, and the output signals from the multiple groups are later combined. A composition means is placed between the divided groups.

The circuit diagram in FIG. 3 shows the configuration of group division. In the figure, 2 is the first ROM circuit;
3 is a second ROM circuit, 4 is a NOR circuit, and 5 is an inverter.

In the ROM circuit 2, _{a MOSFETM 01 for} pre-charging the capacitor C1 is connected between the output terminal _O1 and the negative power supply _-VDD , and the output terminal _O1
MOSFETM ₁₁ or M _1o are connected in series between and ground. The gate of MOSFETM ₀₁ is connected to the terminal for clock pulse _φ
The gates of MOSFETM ₁₁ to M _1o are connected to terminals for receiving input signals A ₁₁ to A _1o , respectively.

In the ROM circuit 3, a MOSFETM ₀₂ for pre-charging the capacitor _C2 is connected between the output terminal _O2 and the negative power supply _-VDD, and the output terminal _O2
MOSFETs M ₂₁ to M _2o are connected in series between and ground. The gate of MOSFET M ₀₂ is connected to the terminal for clock pulse _φ
The gates of M ₂₁ to M _2n each receive the input signal A ₂₁
It is connected to the terminal for receiving A _2n .

In this example, all
The MOSFETs are of the P-channel type, and they are fabricated on a single N-type silicon substrate by well-known manufacturing techniques. Of these MOSFETs, _M33 and _M35 are depletion type, and the rest are enhancement type.

The ROM circuits 2 and 3 are connected to capacitors C ₁ and C ₂ connected to their respective output signals O ₁ and O ₂ by a clock _{pulse φ}
It is precharged via MOSFETs M ₀₁ and M ₀₂ . Then, when MOSFETs M ₀₁ and M ₀₂ are turned off, the input signals A ₁₁ to A _1o and A ₂₁ to A _2n
The charge on capacitors C ₁ and C ₂ depends on the state of MOSFETs M ₁₁ to M _1o and M ₂₁ to
The series path of M _2n determines whether it is discharged or not.

The gate of MOSFET _M31 of NOR circuit 4 is ROM
Connected to output terminal O ₂ of circuit 2, MOSFET M ₃₂
The gate of is connected to the output terminal _O1 of the ROM circuit 3. The output terminal of NOR circuit 4, that is, the load
A negative power supply potential appears at the common connection terminal of MOSFET M ₃₃ and MOSFET M ₃₂ when at least one of M ₃₁ and M ₃₂ is turned off.

The inverter circuit 5 inverts the output of the NOR circuit 4.

These circuits 2 to 5 provide input signals A ₁₁ to A _1o and A ₂₁ to A _2n at the output terminals O ₃ .
When at least one of the two series-connected circuits consisting of MOSFETM ₁₁ to M _1o and M ₂₁ to M _2n receiving the same voltage is turned on, a ground potential appears at the output terminal O ₃ .

The circuit of FIG. 3 is capable of simultaneously responding to inputs A ₁₁ to A _1o and A ₂₁ to A _2n .
If the input signal is an address signal for a memory (not shown) and m=n=12 as shown in the figure, then
By controlling the pairing of one of A _o to A _1o and one of A ₂₁ to A _2n , e.g.
A ₁₁ to A _1o can be used as decoders for addresses 0 to 2047, and A ₂₁ to A _2n can be used as decoders for addresses 2048 to 4095.

In this way, m+n MOSFETs are divided into m and n MOSFETs.
Since the combined resistance of the MOSFETs can be divided into m:n, the combined resistance of the MOSFETs between the respective output terminals O ₁ and O ₂ and ground can be reduced. If m=n=12 as mentioned above,
This can be halved compared to when 24 MOSFETs are connected in series.

On the other hand, the capacitor C ₁ is constituted by the p-n junction capacitance between the drain of MOSFET M ₁₁ and the semiconductor substrate, between the source of MOSFET M ₀₁ and the semiconductor substrate, and the capacitance between the gate of M ₃₂ and the semiconductor substrate, and similarly the capacitor C ₂ are the source of M ₀₂ , the drain of M ₂₁ and
It is formed between the gate of _M31 and the semiconductor substrate. The capacitance values of these capacitors C ₁ and C ₂ are almost the same as those of C ₁ in FIG. 1 above.

Therefore, in the ROM circuits 2 and 3 of FIG. 3, the time constant of each time constant circuit formed by the source-drain resistance of the MOSFETs connected in series and the capacitors C ₁ and C ₂ is m+n.
This is approximately half compared to the case where the FET is not divided at all. Therefore, after precharging the capacitors C ₁ and C ₂ by MOSFETs M ₀₁ and M ₀₂ ,
The time required for the inputs A ₁₁ to A _1o and A ₂₁ to A _2n to discharge the charges in these capacitors C ₁ and C ₂ to the desired level is approximately halved compared to when the circuit of FIG. 1 is used.

In the configuration shown in Figure 3, the idea of halving the discharging resistance of capacitors C ₁ and C ₂ by dividing the series-connected MOSFETs in order to increase the speed of the circuit can be further extended to the idea of dividing into three or four. should be obvious.

In Fig. 3, the ground potential is output to the output terminal O ₃ when either the output terminal O ₁ or O ₂ becomes the ground potential, but if necessary, the output terminal O ₁ and It is also possible to output the ground potential to the output terminal O ₃ when O ₂ becomes the ground potential at the same time.

For such a request, a NAND circuit as shown in FIG. 4 can be used in place of the NOR circuit 4 in FIG. 3.

In addition, in Figure 3, for example, in ROM circuit 3, when precharging capacitor C ₂ ,
When MOSFETs M ₂₁ to M _2n are all on, a DC path is formed between the power supply -V _DD and ground. If such a DC path is not desired, a MOSFET M ₀₃ that turns off during pre-charging can be inserted between the MOSFET M _2n and the ground as shown in FIG.

In FIG. 3, the circuit for combining the outputs _O1 and _O2 can be further changed to another circuit, and the inverter circuit 3 can be omitted if necessary.

FIG. 6 shows an example of application in which the configuration shown in FIG. 3 is used in a memory matrix.

In this example, as shown in the figure, the address decoder 3 and main matrix output blocks 4 to 6 are each divided into upper and lower halves so that they can be driven individually. That is, the first output block 4 as a memory matrix is divided into 4a and 4b,
Furthermore, the second output block 5 is divided into 5a and 5b, and the third output block 6 is divided into 6a and 6b into two stages, upper and lower.
A) is driven by one of the two divided address decoders 3a, and the lower memory matrix (4b to 6b) is driven by the address decoder 3b. Then, the corresponding output blocks of each memory matrix (4a and 4b, 5a and 5
b, 6a and 6b) are taken out as outputs V ₀₁ to _{V 03} via OR circuits L ₁ to L ₃ .

In the ROM configured as described above, by selecting one of the two divided address decoders, the output block of either the upper or lower memory matrix can be operated by the selected address decoder. That is, for example, if address decoder 3a is selected, information from memory matrices 4a to 6a located in the upper stage can be obtained. Assuming that the output of the output block 4a is "1", that is, the ground potential, the "1" level is taken out to the output line _O1 , and the lower block 4b corresponding to this block outputs the "1" level.
“0” when output line _O2 is not selected.
OR since it is at the level (i.e. negative potential)
A "1" level is obtained at the output _V01 of the circuit _L1 . Similarly, when the output of the memory matrix 5a is 0, a "0" level is obtained at the output _V02 of the OR gate circuit _L2 , and when the output of the memory matrix 6a is 1, a "1" level is obtained at the _V03 . . On the other hand, when address decoder 3b is selected, output blocks 4b to 6b of the lower memory matrix become operable. In this way, when either the upper or lower output block is selected, the output of the selected block is obtained as the output of the gate circuit provided at that output point.

As is clear from the above description, the divided output blocks are individually driven.
The number of FETs connected in series to each divided memory matrix line is halved compared to the case where the memory matrix is not divided. Therefore, the discharge time of the memory matrix circuit is approximately halved, and the access time is therefore approximately doubled. In addition, only a few OR circuits (L ₁ to _{L 3} in Figure 5) are added to increase speed, and the additional area is almost negligible when looking at the ROM as a whole. Since it is a product, it does not affect the degree of integration.

According to a preferred embodiment of the present invention, a second address decoder is inserted between the divided memory matrix and the precharge MOSFET. In this case, the second address decoder can determine which column of the memory matrix is enabled or not, so one precharge MOSFET
can correspond to multiple columns of the memory matrix.

This method of using the second address decoder reduces the number of precharge MOSFETs and also reduces the number of the aforementioned OR circuits.

A circuit using this second address decoder will be understood by the embodiment shown in FIG. 7 below.

The example in FIG. 7 shows an example of a 4 kilobit ROM. In this figure, the connection relationship between the address decoder and the memory matrix section, which is a characteristic part of the present invention, is mainly shown. Other timing pulse application parts, output signal handling parts, etc. are not shown.

In the figure, as shown in FIG. 9, an example of line AD ₆₃ , a circle mark indicates that an enhancement type MOSFET is present, and an arrow indicates that a MOSFET gate line is present at the position indicated by this arrow.

This example is written in a format with some parts omitted, but for one address input, 8 bits of information V ₀₁
Or V ₀₈ output.

_3a1 is an upper stage first address decoder to which address signals _A4 to _A11 are applied, and MOSFETs are arbitrarily connected in series to address decode lines _AD0 to _AD63 , respectively. 3a ₂₁ and 3a ₂₂ are upper stage second address decoders to which four address signals A ₀ to A ₃ are applied;
MOSFETs are arbitrarily connected in series. Further, _3b1 is a first address decoder in the lower stage to which address signals _A4 to _A11 are applied, and MOSFETs are arbitrarily connected in series to address decode lines _AD64 to _AD127 . 3b ₂₁ and 3b ₂₂ are address signals A ₀
~A ₃ is applied to the lower stage second address decoder, which is arbitrarily connected in series to the data line.
Consists of MOSFET. Further, 4a and 5a are output blocks of the upper memory matrix, and 4b and 5a are output blocks of the upper memory matrix.
5b is an output block of the lower memory matrix corresponding to 4a and 5a above. The outputs of output blocks 4a and 4b are applied to the input point of OR circuit _L1 via address decoders 3a ₂₁ and 3b ₂₁ , respectively, and the outputs of output blocks 5a and 5b are applied via address decoders 3a ₂₂ and 3b _22, respectively. is applied to the input point of OR circuit _L3 . OR circuit L ₁ to L ₈
The outputs _V01 to _V08 are the outputs of the ROM. Note that L ₀ , L ₄ to L ₆ are inverters, especially L ₀
is connected to the address line A ₁₁ located at the top stage, and is used to switch and operate the address decoders 3a ₁ and 3b ₁ .

The circuit shown in FIG. 7 is formed on the same semiconductor substrate. A plan view of the semiconductor substrate near the address decode line AD ₆₃ is shown in FIG. 8A. Figure 8A-
A cross-sectional view at A', that is, a cross-sectional view of a portion related to address decode line AD ₆₃ is shown in FIG. 8B.

In FIG. 8, the MOSFET is of a P channel type and is fabricated on an N type silicon substrate 10. In FIG. 8A, the broken line indicates the P-type region,
The two-dot chain line indicates the polysilicon layer, and the solid line indicates the aluminum electrode. The dashed line indicates the oxide film 31 or
A hole is formed in the silicon oxide film 32 by the CVD method to make contact between the aluminum electrode, the P-type region, and the substrate or polysilicon layer.

The sources and drains of MOSFETs Q ₁ to Q ₇ are arranged horizontally in the drawing (Q ₁ to Q ₇ are for the address decoder 3a ₁ ). The source region 11 of Q ₁ is short-circuited to the substrate 10 by an electrode 31, and the drain region 12 has a common structure with the source region of Q ₂ . Each P-type region 11
The part of the substrate surface sandwiched between the pairs of 30 to 30
A thin oxide film is formed for the gate region of the MOSFET. Extending over each gate region are polysilicon layers A ₁₁ , A ₁₀ , ₄ , φ _x , AD′ ₆₃ .

In this example, Q ₂ and Q ₇ are depletion type, and are always on regardless of the signal levels of A ₁₀ and ₄ , respectively. This depression type
The MOSFET has matrices 3a ₁ , 3a ₂₁ , 3a 21 , and
Enhanced types marked with circles 3a ₂₂ , 3b ₁ , 3b ₂₁ , 3b ₂₂ , 4a, 4b, 5a and 5b
Placed at an intersection other than the intersection indicating the MOSFET.

The source/drain regions of FETQ ₈ and Q ₁₃ are arranged vertically in the drawing. These Q ₈ and Q ₁₃ are for memory matrices 4a and 5a.

According to _the above ROM, either address decoder (3a ₁ or 3
b ₁ ) is selected, the other address decoder becomes unselected. In addition, since the signals of one unit block are always read by the OR circuits _L1 and _L2 , it has the function of a normal ROM, and as mentioned above, it is a ROM that can speed up the access time. Become.

As shown in Figure 7, OR circuits L ₁ and L ₈ are connected to block 4.
In the case of a configuration provided between blocks a, 5a and 4b, 5b, the output from block 4a and the output from block 4b are
Distance to supply to OR circuit L ₁ , block 5
The distance between the output from a and the output from 5b to be supplied to the OR circuit _L8 can be shortened. This configuration reduces coupling noise, especially in so-called ratioless circuit configurations, which are susceptible to undesired coupling through capacitance because the signal level is determined not by DC but by the charge level of the capacitor. It is meaningful in that it allows The OR circuits L ₁ and L ₈ in FIG. 7 are
It is a static circuit, and each output is not easily affected by coupling noise.

The divided memory matrix is shown in Figure 6.
When arranged one above the other as shown in FIG. 7, the overall shape of the memory matrices 4a to 6a and 4b to 6b can be adjusted so as not to become too long and narrow. Such an arrangement is especially suitable for the seventh
If the number of series-connected MOSFETs in the memory array is reduced by setting the decoders 3a and 3b as shown in the figure, the number of MOSFET columns will increase accordingly, and the lateral width of the memory matrix will increase. It is recommended that you take this into consideration.

The present invention is not limited to the above embodiments, and various modifications can be made.

For example, in the embodiment described above, each output block is divided into two, but it is also possible to divide it into more than that, and in such a case, the access time can be further increased.

Further, in the above embodiment, an OR circuit is used to select the output of the upper and lower output blocks, but the present invention is not limited to this, and the output of each block may be directly applied to the output circuit.

Furthermore, as a selection means for the address decoders _3a1 and _3b1 , the inverter _L0 is connected to the uppermost address line (2048-bit line, which is between 8K bits) _A11 , which has the largest weight. However, the connection is not limited to this, and may be connected to other address lines. However, it goes without saying that it is easier to divide the signal if it is connected to the address line _A11 as described above. That is, when the upper address decoders 3a ₁ and 3a ₂ are selected, 2046 bits or less are read out, and when the lower address decoders 3b ₁ and 3b ₂ are selected, 2046 bits or more are read out. It turns out.

In addition, in order to obtain an FET that does not need to be switched by the potential of the gate electrode, all of the FETs are of the enhancement type as shown in Figure 10, instead of the depletion type as shown in Figure 8, and the aluminum electrode It is also possible to short-circuit the source/drain regions at 31 and 32. The method of FIG. 10 can reduce the resistance because the resistance of aluminum is much lower than that of the semiconductor region.

The present invention provides 4K bit data as in the above embodiment.
Needless to say, this method can be applied not only to ROM, but also to ROM of other capacities.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional vertical ROM, Figure 2 is a timing chart to explain its operation, and Figure 3 is a vertical ROM divided into blocks.
4 and 5 are circuit diagrams of modified examples of the circuit of FIG. 3, FIG. 6 is a block diagram of an application example of the circuit of FIG. 3, FIG. 7 is a circuit diagram of an embodiment, and FIG. Figure A is a plan view of the vicinity of line AD ₆₃ when Figure 7 is integrated into a semiconductor, Figure 8B is a sectional view taken along line A-A' in Figure A, and Figure 9 is a circuit diagram of the portion shown in Figure 7. , 10th
The figure is a sectional view of another semiconductor integrated circuit, and FIG. 11 is a timing chart of FIG. 7. 1, 3a, 3b, 3a ₁ , 3a ₂₁ , 3a ₂₂ , 3b ₁ ,
3b ₂₁ , 3b ₂₂ ...address decoder, 2, 4a,
5a, 6a, 4b, 5b, 6b...Memory matrix output block, 7...Flip-flop circuit, _L0 to _L6 ...Gate circuit, _Q1 to _Q64 , _M1 to _M10
...FET.

Claims (1)

[Claims] 1. A plurality of input lines extending parallel to each other in the row direction and selectively set to a selected level by an address signal, and a plurality of input lines selectively arranged in rows and columns, with gates in each row. A plurality of fixed memory elements commonly coupled to the corresponding input lines and having sources and drains connected in series in each column.
first and second memory arrays each including a MOSFET and a plurality of output lines respectively corresponding to a group of MOSFET rows each including a plurality of rows of MOSFETs connected in series; and the output line of the first memory array; The above MOSFETs are connected to each other between the reference potential point of the circuit.
A plurality of MOSFETs connected in series with a column of
between the output line of the second memory array and the reference potential point of the circuit, respectively.
Each of the
a second decoder means comprising a plurality of MOSFETs that selects a column of MOSFETs in a MOSFET group; and a second decoder means configured to OR-synthesize the signals of the output line of the first memory array and the corresponding output line of the second memory array, respectively. A semiconductor read-only memory comprising a plurality of logic synthesis means each forming an output signal, wherein the columns of MOSFETs of the first memory array and the second memory array are arranged in the same column direction. and the first memory array and the second memory array are arranged such that the second memory array is located in the direction in which the MOSFET columns of the first memory array extend. Read-only memory. 2. The semiconductor read-only memory according to claim 1, wherein the plurality of logic synthesis means are arranged between the first memory matrix and the second memory matrix. 3. Claims 1 or 2, characterized in that the plurality of input lines of the first memory matrix and the second memory matrix are set to a selection level by an address signal.
Semiconductor read-only memory described in Section 1. 4. A plurality of devices constituting the first decoding means.
Each of the MOSFETs is located on an extension line of the corresponding MOSFET column of the first memory array, and the plurality of address input lines in the first decoding means extend parallel to the plurality of input lines of the first memory array. a plurality of decoding means constituting the second decoding means;
Each of the MOSFETs is located on an extension line of the corresponding MOSFET column of the second memory array, and the plurality of address input lines in the second decoding means extend parallel to the plurality of input lines of the second memory array. A semiconductor read-only memory according to any one of claims 1 to 3, characterized in that: 5 In the first and second memory matrices,
The MOSFET that does not need to be turned off when the input line is set to the selection level is a depletion type MOSFET.
A semiconductor read-only memory according to any one of claims 1 to 4, characterized in that the semiconductor read-only memory is composed of a MOSFET. 6 In the first and second memory matrices,
Claims 1 to 4, characterized in that a MOSFET portion that does not need to be turned off when the input line is set to a selection level has a structure in which the source and drain regions are short-circuited. 1. The semiconductor read-only memory described in 1.