JPS6045509B2 - Semiconductor read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor read-only memory (hereinafter referred to as ROM), and in particular to a semiconductor read-only memory (hereinafter referred to as ROM), in which a plurality of insulated gate field effect transistors (hereinafter simply referred to as FETs) are connected in series to one output line. ROMs such as those shown in FIG. 1 are referred to as vertical ROMs.

As a vertical type ROM, Japanese Patent Application No. 1973-107350
There is something similar to what was proposed.

An example is shown in FIG. In this example, a capacitor C is connected between the output terminal ADo and ground, and a MOSFET is connected between the negative power supply -VDD and the output terminal.

is connected, and the above capacitor C1 is connected between the output terminal and ground.
MOSFETs MI to Mn are connected in series in parallel with . MOSFETMo functions as a switch for precharging the capacitor C1, and the series-connected MOSFETs M to Mn function as switches for receiving inputs Al to An.

In this example, it is MOSFET. is a depletion type and remains on regardless of the potential of the gate electrode that receives input air. That is, a current path is formed between the source and drain of M2. On the other hand, MOSFETM,
, Mn-, , Mn are enhancement type and are turned on and off depending on the gate potential. Therefore, a current path is created between the output terminal ADo and the ground if all of the enhancement type MOSFETs are on, and if any one
If it is off at all times, a current circuit cannot be created. In this example, as shown in the time chart in FIG.
TMo is turned on and the capacitor C1 is charged up.

Then, the level of the clock signal φu returns to the ground potential GND.
Return to At this time, if at least one of the series-connected FETs Ml to Mn is off, the charge in the capacitor C1 is not discharged. Therefore, the voltage across the capacitor C1 remains as it was when it was precharged. If a current path is established in all of FET Ml to Mn, the charge in capacitor C1 will be discharged.

The voltage across this capacitor C1 eventually becomes zero. In this circuit, if one of the FETs Ml to Mn is off, there is no change in the precharged charge of the capacitor C1, so it is okay to use the output signal from the output terminal ADO immediately after precharging. . However, when a current path is formed between Mi and (2), the charge of the capacitor C after precharging does not immediately become zero.

At this time, the capacitor is FET Ml in the on state.
Since the resistors connected in series between the source and drain of Mn to Mn become short-circuited, it takes time for the potential of the output terminal ADO to reach an appropriate value in accordance with the inputs A1 to An. The next circuit (not shown) connecting the output terminal ADO to the input terminal is therefore made to receive the human input signal after a time t1 after the circuit of FIG. 1 has been precharged.

The circuit in Figure 1 is an output terminal pigeon.

By selectively making the MOSFETs connected in series between and ground into enhancement type or depletion type,
The logic for inputs A1 to An can be changed arbitrarily.
This method of changing the logic is based on MOs arranged in a matrix.
Suitable when configuring a ROM using SFETs. For example, among MOSFETs arranged in a matrix, the sources and drains of MOSFETs arranged in a column direction are connected in series, and a gate electrode is connected in series in a direction perpendicular to the columns. A plurality of input wirings serving as ground electrodes, for example A1 to A. ．． and φe, and the selected MOSFET is made into a depletion type MOSFET. In this way, desired logic outputs can be extracted from each column of the matrix arrangement. The example shown in FIG. 1 also has low power consumption because current flows through the power supply -VDD only when the clock pulse φX becomes a negative potential.

However, when this circuit connects many MOSFETs in series to receive many input signals, the source-drain resistance of the series-connected MOSFETs increases.
Therefore, it is necessary to increase the time from when a signal is input until a signal of sufficient level can be obtained at the 7 output terminals.

In other words, the access time becomes longer. Therefore, it is an object of the present invention to provide a ROM with faster access time.

Another object of the present invention is to provide a ROM that has a simple configuration and can achieve faster access times.

In order to achieve the above object, according to the present invention, MOSFETs that require series connection are divided into a plurality of groups, and the output signals from the plurality of groups are later combined.

Examples will be described below.

In FIG. 3, 2 is the first ROM circuit, 3 is the second ROM circuit, and 3 is the second ROM circuit.
4 is a NOR circuit, and 5 is an inverter.

ROM circuit 2 has output terminal 01 and negative power supply -■.

. A MOSFET MOl for precharging the capacitor C1 is connected between the output terminal 01 and the ground, and MOSFETs Mll to Mln are connected in series between the output terminal 01 and the ground. The gate of MOSFET MOl is clock pulse φ8
is connected to the terminal for MOSFET Mll to M
The gates of ln are respectively connected to terminals for receiving input signals All to Aln. The ROM circuit 3 has a capacitor C2 between the output terminal 02 and the negative power supply -DD.
A MOSFET MO2 for precharging is connected, and MOSFETs M2l to M2n are connected in series between the output terminal 02 and ground.

The gate of MOSFET MO2 is connected to the terminal for clock pulse φx, and the gate of MOSFET MO2 is connected to the terminal for clock pulse φx.
．． The gates of are connected to terminals for receiving input signals A2l to A2j, respectively. In this example, without limiting the invention, all MOSFETs are of the P-channel type and are fabricated on a single N-type silicon substrate by well-known fabrication techniques.

Of these MOSFETs, M33 and M35 are of the depletion type, and the rest are of the enhancement type.
The ROM circuits 2 and 3 receive a clock pulse φ.

The on-state MOSFE is connected to the capacitors Cl and C2 connected to the output terminals 01 and 02 from the negative power supply.
It is precharged via TMO1 and MO2.

Then, when MOSFET MOl, MO2 are turned off, input signals All to Aln and A2l to A2j.
Depending on the state of the capacitors C1 and C2, the charges M
OSFETM Mll to Mln and M2l to M2
The series path of n, determines whether it is discharged or not. The gate of MOSFET M3l of NOR circuit 4 is R
It is connected to the output terminal 01 of the OM circuit 2, and the MOSFET
The gate of 32 is connected to the output terminal 02 of the ROM circuit 3.

The output terminal of the NOR circuit 4, that is, the load MOSFET
The common connection terminal between 33 and MOSFET M32 has M3
When at least one of I and M32 is turned off, a negative power supply potential appears. The inverter circuit 5 inverts the output of the NOR circuit 4.

These circuits 2 to 5 output input signals All to A to the output terminal 03. and A2l to A2. MOSFETs Mll to Mln and M each receiving n
, l to M2m, when at least one of the two series-connected circuits is turned on, a ground potential appears at the output terminal 03.

This third circuit has inputs All to ATn and A2
l to A2. ．． can be responded to at the same time.

If the input signal is an address signal for a memory (not shown) and m=n=12 as shown, then A. or A
one of ln and A. l to A2. By controlling the pairing with one of n, for example, All to Al
Let n be a decoder for addresses 0 to 2047, and A
2l to A6 can be used as a decoder for 2048 to 409 fields. Like this m+
In the method of dividing n MOSFETs into m and n, the combined resistance of m+n MOSFETs can be divided into m:n, so the combined resistance of the MOSFETs between each output terminal 01, 02 and ground can be reduced. . m as above
= n = 12, it can be halved compared to the case where 24 MOSFETs are connected in series. On the other hand, capacitor C1 is M
between the drain of OSFETMll and the semiconductor substrate and M.

Pn junction capacitance between the source of l and the semiconductor substrate and M3i
Similarly, capacitor C2 is configured by the capacitance between the gate of r! and the semiconductor substrate. It is formed between the source of 402, the drain of M2i, and the gate of M32 and the semiconductor substrate. The capacitance values of these capacitors Cl and C2 are almost the same as those of C1 in FIG. Therefore, the MOS connected in series in ROM circuits 2 and 3 in FIG.
FET source-drain resistance and capacitor Cl,
The time constant of each time constant circuit formed by C2 is approximately half that of the case where m+n FETs are not divided at all.

Therefore, after precharging the capacitors Cl and C2 by the MOSFETs MOl and MO2, the input Al
The time it takes for the charges in these capacitors Cl and C2 to discharge to a desired level due to I to Aln and A2i to A2m is approximately halved compared to the case where the circuit of FIG. 1 is used. In the embodiment of FIG. 3, the idea of halving the discharging resistance of capacitors Cl and C2 by dividing the series-connected MOSFETs in order to speed up the circuit can be further extended to dividing into three or four. should be obvious.

In Fig. 3, the ground potential is output to the output terminal 03 when either output terminal 01 or 02 becomes the ground potential, but if necessary, the output terminals 01 and 02 may be grounded at the same time. Output terminal when the potential is reached: FO3
It is also possible to output a ground potential to the terminal.

For such a request, a NAND circuit as shown in FIG. 4 can be used in place of the NOR circuit 4 shown in FIG.

Further, in FIG. 3, for example, in the ROM circuit 3, when precharging the capacitor C2, MOSFETs M2l to M2. ．． If all are on, the power -■C. A DC path is formed between D and ground.

If such a DC path is not desirable, a MOSFET MO3 that turns off during precharging can be inserted between the MOSFET M2 and the ground as shown in FIG. In FIG. 3, the circuit for combining outputs 01 and 02 can be replaced with another circuit), and the inverter circuit 3 can be omitted if necessary.

FIG. 6 shows an example of application in which the embodiment of FIG. 3 is used in a memory matrix.

In this example, as shown in the figure, the address decoder 3 and main matrix output blocks 4 to 6 are arranged vertically in two directions.
Divide them so that they can each be driven individually.

That is, the first output block 4 of the memory matrix is connected to 4a and 4b, and the second output block 5 is connected to 5a and 5b.
In addition, the third output block 6 is placed above and below 6a and 6b.
The memory matrices 4a to 6a in the upper stage are driven by one of the two divided address decoders 3a, and the memory matrices 4b to 6b in the lower stage are driven by the address decoder 3b. Then, the outputs of the corresponding output blocks 4a, 4b15a, 5b16a, and 6b of the respective memory matrices are output V via the 0R circuits L1 to L. Take out as l~■o. In the ROM of the present invention having the above configuration, by selecting one of the two divided address decoders, the output block of either the upper or lower memory matrix can be operated by the selected address decoder. I can do it.

That is, for example, if address decoder 3a is selected, information from memory matrices 4a to 6a located in the upper stage can be obtained. If the output of the output block 4a is "゜1", that is, the ground potential, the "1゛2 level will be taken out to the output line 01, and when the output line 02 of the lower block 4b corresponding to this block is not selected, the output line 01 will be "゜゛. Since it is at 0゛ level (that is, negative potential), the output V of 0R circuit L. ``1'' level is obtained at l.Similarly, when memory matrix 5a is 0, the output of 0R gate circuit L2 is V. 2 is obtained at 0'' level, and when 6a is 1, V is output.

3 becomes the "゜r゛ level. Also, the address decoder 3
When b is selected, the output blocks 4b to 6b of the lower memory matrix become operable. When either the upper or lower output block is selected in this way. Then, the output of the selected block is obtained as the output of the gate circuit provided at the output point. As is clear from the above description, according to the present invention, the divided output blocks are individually driven.

The number of FETs connected in series to each divided memory matrix line is halved compared to the case where the memory matrix is not divided. Therefore, the discharge time of the memory matrix circuit is approximately halved, and the access time is therefore approximately doubled. In addition, the present invention only adds a small number of 0R circuits (!~LJ in Figure 5) to achieve its purpose, and the additional area is almost ignored when looking at the ROM as a whole. Since it is possible to do so, it does not affect the degree of integration. According to another example of the invention, the address decoder is divided into two parts.

The second address decoder separated from the first address decoder provided on the input side of the memory matrix is
It is inserted between the memory matrix and its precharge MOSFET. In this way, it can be determined by the first and second address decoders which columns of the memory matrix are to be enabled. A circuit using this second address decoder will be understood by the embodiment shown in FIG. 7 below.

The example of FIG. 7 shows an example of a 4 kilobit ROM.

In this figure, the connection relationship between the address decoder and the memory matrix section, which is a characteristic part of the present invention, is mainly shown. Other timing pulse application parts, output signal handling parts, etc. are not shown. In the figure, the example of line ADs3 is
As shown in the figure, the circles are enhancement type MOSFEs.
The arrow indicates that there is a MOSFET gate line at the position indicated by the arrow.
This example is written in a format with some parts omitted, but for one address input, 8 bits of information V. L or V. 8
outputs. 3a1 is an upper-stage first address decoder to which address signals A, .about.All are applied, and MOSFETs are arbitrarily connected in series to address decode lines ADO-AD63.

3a21, 3a. Reference numeral 22 designates an upper second address decoder to which four address signals A3 to A3 are applied (MOSFETs are arbitrarily connected in series to the data lines, respectively).

Further, 3b1 is the first address decoder of the stage to which the address signals A4 to All are applied, and MOSFETs are arbitrarily connected in series to the address decode lines AD64 to ADl27. 3b21, 3Y) 22 is the address signal A .

This is the second address decoder in the lower stage to which ~A3 is applied, and is composed of MOSFETs arbitrarily connected in series to the data line. Further, 4a and 5a are output blocks of the upper memory matrix, and 4b and 5b are output blocks of the lower memory matrix corresponding to 4a and 5a. The outputs of output blocks 4a and 4b are applied to the input point of 0R circuit L1 via address decoders 3a2, 31), 1, respectively, and the outputs of output blocks 5a and 5b are applied to address decoders 3a22, 3b, 2, respectively. via 0
R circuit! is applied to the input point of 0R circuit! Or L8
output V.

L or V. 8 is the output of the ROM.

Note that LO, L, ~L6 are inverters, and in particular, L
0 is connected to the address line All at the top stage, and is used to switch and operate the address decoders 3a1 and 3b1. The circuit shown in FIG. 7 is formed on the same semiconductor substrate.

A plan view of the semiconductor substrate in the vicinity of address decode line AD63 is shown in FIG. 8A. FIG. 8B shows a cross-sectional view taken along line A-A'' in FIG.
T is a P-channel type and is fabricated on an N-type silicon substrate 10.

In FIG. 8A, the broken line shows the P-type region, the two-dot chain line shows the polysilicon layer, and the solid line shows the aluminum electrode. The one-dot chain line indicates a portion where a hole is provided in the oxide film 31 or the silicon oxide film 32 formed by the CVD method to bring the aluminum electrode into contact with the P-type region and the substrate or polysilicon layer. The sources and drains of MOSFETs Ql and Q2 are arranged horizontally in the drawing (
Q1 to Q7 are for address decoder 3a1).

The source region 11 of Q1 is short-circuited to the substrate 10 by an electrode 31, and the drain region 12 has a common structure with the source region of Q2. A thin oxide film for a gate region of a MOSFET is formed on the surface of the substrate in a portion sandwiched between each pair of P-type regions 11 to 30. On each gate region is a polysilicon layer All9AlO9■9φX9AD563
In this example, Q2 and Q are depletion type, and are always on regardless of the AlO and tile b signal levels, respectively. This depression type M
The OSFETs are arranged in matrices 3a1, 3a21, and 3a21 in FIG.
3a22, 3b1, 3b21, 3Y) 22, 4a, 4b
, 5a and 5b are marked with circles.
It is placed at an intersection other than the intersection indicating the SFET.

The source and drain regions of FETQ8 and Ql3 are arranged vertically in the drawing. These Q8 and Ql3 are for the memory matrices 4a and 5a. According to the above ROM, the inverter L. When either address decoder 3a1 or 3b1 is selected by , the other address decoder becomes non-selected. Also, 0R circuit and!
As a result, the signal of one unit block is always read out, so that the ROM has the function of a normal ROM and can achieve high-speed access time as described above. According to the embodiment shown in FIG. 7, the first address decoder 3a1 (3b1) and the second address decoders 3a21, 3a22... (3b2, 3
b2.

・・・・・・Rito will be established. Each second address decoder e.g. 3! is inserted between memory matrix 4a and a precharge FET driven by signal φY. Therefore, in this case, the time required for precharging each column of the memory matrix increases by an amount corresponding to the FET column constituting the second address decoder. However, by providing the second address decoder, the precharge time can be shortened from the perspective of the ROM as a whole. That is, R.O.
The precharge time in M includes not only the precharge time to the memory matrix 4a by the signal φY, but also
It is determined by the precharging time of the first address decoder 37a1 by the signal φx. In particular, in precharging the first address decoder, in addition to precharging the series of cascaded FETs constituting the first address decoder, 5 is also precharged to the gate capacitance of the FET constituting the memory matrix. must be performed, which requires a relatively long precharge time. As a result, the precharge time in the ROM depends on the precharge time to the first address decoder 3a1. Therefore, as in this embodiment, dividing the address decoder and substantially shortening the precharging time to the first address decoder contributes to shortening the precharging time from the perspective of the entire ROM. It will be possible. The present invention is not limited to the embodiments described above, but various modifications can be made.

For example, in the above embodiment, each output block is divided into two parts, but it is also possible to divide each output block into more parts, and in such a case, the access time can be further increased.

Further, in the above embodiment, the 0R circuit is used to select the output of the upper and lower output blocks, but the present invention is not limited to this, and the output of each block may be directly applied to the output circuit.

Further, an inverter L is used as a selection means for address decoders 3a1 and 3b1. is connected to the uppermost address line (a line of 2048 bits, which is between 8K bits) with the largest weight, but the connection is not limited to this, and may be connected to other address lines. but,
Needless to say, it is easier to divide the signal if it is connected to the address line All as described above. That is, when the upper address decoders 3a1 and 3a2 are selected,
When 2046 bits or less are read and the lower address decoder 3b1, 31) is selected, 204 bits or less are read.
Six or more bits will be read. In addition, F
In order to obtain ET, everything is not a depletion type as shown in FIG. 8, but an enhancement type as shown in FIG. 10, and the aluminum electrode 31,
It is also possible to short-circuit the source/drain regions at 32.

The method of FIG. 10 can reduce the resistance because the resistance of aluminum is much lower than that of the semiconductor region. The present invention provides the RO of the target bit as in the above embodiment.
Needless to say, the present invention is not only applicable to M, but also widely applicable to ROMs of other capacities.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional vertical ROM, FIG. 2 is a timing chart for explaining its operation, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIGS. 4 and 5 is the third
6 is a block diagram of an application example of the circuit in FIG. 3, FIG. 7 is a circuit diagram of another embodiment, and FIG. 8A is a circuit diagram of a modified example of the circuit in FIG. 7. FIG. 8B is a cross-sectional view taken along line A(7)AN in the figure, FIG. 9 is a circuit diagram of the portion shown in FIG. 7, and FIG. 10 is a cross-section of another semiconductor integrated circuit. 11 is a timing chart of FIG. 7. 1, 3a, 3b, 3a1, 3a21, 3a22, 3b1
, 3b21, 3b22...address decoder, 2,
4a, 5a, 6a, 4b, 5b, 6b...Memory matrix output block, 7...Flip-flop circuit~LOp'! o1 game 7 circuit) Q1ゞQ649
MlゞMlO...FET.

Claims (1)

[Claims] 1. A plurality of memory blocks each including a plurality of output points and a plurality of series circuits each having a plurality of FETs connected in series between each of the plurality of output points and a predetermined potential point. and a gate circuit receiving outputs from the plurality of memory blocks, the semiconductor read-only memory comprising: a gate circuit receiving outputs from the plurality of memory blocks, the gate circuit taking out one of the outputs from the plurality of memory blocks; The gate circuit has a plurality of input points that receive outputs from each of the plurality of memory blocks, and each output point of the memory block is connected to the input point of the gate circuit via an FET whose switch is controlled based on an address signal. A semiconductor read-only memory characterized by being coupled to a semiconductor. 2. The semiconductor read-only memory according to claim 1, wherein the gate circuit is configured such that the potential of its output is determined according to the potentials of the plurality of input points.