JPS62188075A - Soft decision decoding system - Google Patents

Abstract

PURPOSE:To simplify a signal processing without deteriorating decoding efficiency, by simply comparing reliability in reproducing signals and setting an eraser. CONSTITUTION:A reproduced signal (a) is converted 2 to a hard decision data (b) and a reliability data (c), and a syndrome is calculated 3 from the data (b), and also, the data (c) decides an undefinite data (e) within a threshold value, and when the number of the data (e) is below a prescribed number, the data (e) is set as it is as an eraser candidate (f). And based on the bits of syndrome and eraser information, two to four errors are found at correction circuits 5-7. At arithmetic circuits 9-11, the twice of the absolute value of the reliability at each error position is subtracted from the total sum of the absolute value of the reliability of the signal (a), and an inner product between a correction code word and the reproducing signal is found and at decision circuits 12-14, decision for the size of each inner product is performed, and one of errors is stored at a memory 15, and the error correction is performed with an EX-OR circuit between the error and the hard decision data delayed 16, then a correction data being sent out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an error correction method, and particularly to a so-called soft-decision decoding method that performs correction using analog information of a received or reproduced signal.

[Background of the invention]

In recent years, with the development of LSI technology, error correction codes have come to be widely applied to everything from various storage devices for computers to home audio equipment. To decode this error correction code, the reproduced signal is turned on or II 1
There is a hard-decision decoding method in which errors are corrected after conversion into pp hard-decision data, and a soft-decision decoding method in which errors are corrected by using the analog value of the reproduced signal as the reliability of the hard-decision data.

Conventionally, hard-decision decoding methods have been widely used because they can be implemented with small-scale hardware. However, in recent years, with advances in semiconductor technology, the amount of hardware has become less of an issue, and soft-decision decoding methods, which have 2 to 3 dB higher decoding efficiency than hard-decision decoding methods, are attracting attention.

Among the many soft-decision decoding methods, GMD (Generalized Minimum Dist
ance) Richard E. Blatt, Theory and Practice of Error Control Course, pages 464-473: Addison Unizuri Publishing Company, 1983 (R
ichard E, Blahut Thory a
ndpracticaof error control
l codes”, P, 464 A′p, 473°Ad
dison-Wesley Publishing
Company.

1983)) is known as a decoding method with relatively simple signal processing and high decoding efficiency. below.

GMD using the flowchart in Figure 5 and the waveform diagram in Figure 2.
The decoding procedure of the decoding method will be explained.

First, by determining whether the output voltage of the reproduced signal a as shown in FIG. 2 is negative or positive, 110 II or It I I
The hard decision data b of I are converted into reliability data C that takes a value in an interval (-1, +1) proportional to the output voltage of the reproduced signal a. Next, for each code word which is a basic unit of error correction consisting of n bits, d-1 pieces of hard decision data are selected from the absolute value of the reliability data and arranged in order of reliability.

However, d indicates the minimum Hamming distance of the error correction code. Then, the two pieces of hard decision data with the lowest reliability (initial value is O) are used as erasures, and a candidate code word Cm is generated by performing error correction and erasure correction. After that, “1” of the code word c℃ is changed to “l It , II
The inner product CJ2'·R of the series CJ2' obtained by converting Q IP into jilt and the reliability data series R of the reproduced signal is determined. Next, it is determined whether the inner product Cβ′ ・R satisfies the inequality % expression %, and if the inequality holds, CJ
2 is output, and if it does not hold, it is output as 11+2 and the same process as above is repeated. If Q exceeds d-1, it is assumed that an error exceeding the error correction ability has occurred.

In the above GMD decoding method, d-
The process of selecting one piece of hard-decision data and arranging it in order of reliability is complicated, and requires a long processing time when processing a soft program using large-scale hardware or a microcomputer. This was a serious obstacle to putting it into practical use.

[Purpose of the invention]

An object of the present invention is to provide a soft-decision decoding method that uses simple signal processing and does not degrade decoding efficiency.

[Summary of the invention]

In the GMD decoding method, hard decision data to be used as erasure is set by comparing the reliability of reproduced signals.

Instead of this, in the present invention, ±θ(0
A threshold value of <θ<1) is set, and all hard-decision data for which the reliability of the reproduced signal falls within the threshold value is treated as uncertain data. When the uncertain data is less than d-1 bits, the uncertain data is directly used as an erasure candidate. When the uncertain data is more than d pit.

An arbitrary d-1 bit is selected as an erasure candidate. Furthermore, the erasure candidates are not ordered based on their reliability, but are ordered according to an arbitrary rule.

For example, if uncertain data of at most d-1 bits in the order of playback are unconditionally taken as erasure candidates and ordered in the order of playback, the signal processing required for decoding becomes extremely simple.

The subsequent processing is similar to the conventional example, by repeating error correction and erasure correction to generate multiple candidate code words, and output the code word whose inner product with the reproduced signal is greater than n-d. do.

According to the above invention, signal processing for decoding becomes extremely simple. Furthermore, by ordering erasure candidate data based on reliability, the probability that a correct codeword becomes a candidate codeword is small, and by setting a threshold so that the average number of uncertain data is d-1 bits. , it is possible to almost eliminate deterioration in decoding efficiency with respect to the GMD decoding method.

[Embodiments of the invention]

Below, the code length n is 15 bits, the number of information points k is 7 bits,
BCH (15, 7,
5) The present invention will be explained in detail using FIGS. 1 to 3, taking the reference numeral as an example.

The reproduced signal a shown in FIG. 2 inputted from the input terminal 1 is A
/D converter 2 converts the hard format data b consisting of 1g 099 or 1'1" into reliability data C indicating its reliability. In the syndrome calculation circuit 3, the 1 of the BCH code
A syndrome is calculated from the hard decision data b for every 15 bits constituting one code word. Eraser position detection circuit 4
First, the reliability data C has a predetermined threshold value (
In this example, the hard decision data within ±T) is defined as uncertain data e (indicated by the symbol Keyaki). Next, if the uncertainty is d-1 (=5-1=4) or less data e.

Let the uncertain data e be the erasure candidate f as it is (indicated by the symbol *), and as shown in Figure 3, if the uncertain data e' is d-
If there are more than one, d-1 of them are selected as erasure candidates according to a certain rule, for example, as shown in f' in FIG. 3, starting from the earliest in the playback order (as shown in the article).

The second error correction circuit 5 detects at most two errors based on the syndrome obtained from the syndrome calculation circuit 3.
Find 3.

In the 1st factory 2nd erasure correction circuit 6, i or lyj (
In Figure 2, i=3. j=8. In Figure 3, i=3. j=7
), at most three errors ei+eje eK are found. However, if erasure is not provided, this error correction circuit is incapable of correction.

4 erasure correction circuit 7, the syndrome and im J
* k or lp j + kp Ω (1=3 in Fig. 2
tj=8tk=15. In Figure 3, i=3. j=7.
ni=8. By using the erasure information of fi=12), at most four errors el+ej+exeeeA are found. However, if only two or less erasures are given, this error correction circuit is rendered incapable of correction.

In addition, the sum γ of the absolute value 1α11 of the reliability of the reproduced signal for each code word consisting of 15 bits (in the example of FIG. 2, γ=1-1.01++1.0++I--l+l-
'? -1+11. OI+1-2-1+1-±1+1 engineering l
+l-1. Ol+ 1-1.01++ 1.01+1-1.01+11.0
1+11.0I+17-1=11.875 in calculation circuit 8
Then, calculation circuits 9, 10, 11
By subtracting twice the absolute value of the reliability of each error position from γ, the inner product of the code word corrected by the error correction circuits 5, 6.7 and the reproduced signal is obtained. However, if the error correction circuits 5.6.7 are unable to correct, the values of the inner product calculation circuits 9 and 10.11 are calculated as n - d (= 15-
5=10) or less.

In the determination circuits 12, 13.14, arithmetic circuits 9,
10. It is determined whether the inner product value obtained in 11 is greater than n - d.

According to the above-mentioned literature, the inner product with the reliability series of the reproduced signal is n
It is guaranteed that there is at most one code word that is larger than -d, and even if there are two or more cases in which the inner product value is larger than nd in the judgment circuit 12.13.14, it is Since they are the same code word, choose one from among them.
The error at that time is stored in the memory 15, and it is combined with the hard decision data output from the delay circuit 16 and E-OR (
The error is corrected by calculating the exclusive OR using the Exclusive OR) gate, and the corrected data is output from the output terminal 20.

If all three inner product values are equal to or less than n-d, this means that an error exceeding the correction ability has occurred.

The error detection signal from the AND gate 18 is output to the terminal 2o.
Output from.

In this embodiment, the present invention is realized by hardware, but 1
For example, it can also be realized by a software program using a microcomputer. Hereinafter, the processing procedure by the software program will be explained using the flowchart shown in FIG.

First, the reproduced signal is converted into hard decision data and reliability data. Next, for each n bits constituting one codeword,
Among the hard decision data whose reliability is within the threshold value, at most d-1 pieces of hard decision data in the order of reproduction are set as erasure candidates and arranged in the order of reproduction. Then, Q pieces of hard decision data (initial value is 0) are used as erasures, and a candidate code word Cu is generated by correcting errors and erasures. After that, El l II of code word cj2 is # + 11j, 11
0 Calculate the inner product (X/・R) of the series Cβ' obtained by converting It to -1 and the reliability data series R of the reproduced signal. Determine whether the inner product cJ2'・R satisfies the inequality % formula % If the inequality holds, then Cβ
Output. If it does not hold, set Q=Q+2, and Ω becomes S+
If it is 2 or more, it means that an error exceeding the error correction capability has occurred, and an error detection signal is output. Q is S+
If it is 1, fi=12-1 and the same process as before is repeated. If Q is less than or equal to S, the same process as before is repeated.

In this embodiment, the present invention has been explained in detail by taking the BCH code, which is a bit error correction code, as an example, but it goes without saying that the present invention can be easily applied to byte error correction codes such as Reed-Solomon codes. .

〔Effect of the invention〕

According to the present invention, since the erasure is set by simply comparing the reliability of the reproduced signal, the circuit scale can be significantly reduced when realized by hardware, and the processing when realized by software. The time can be significantly reduced, and as a result, it has become possible to implement a soft-decision decoding method.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the operation of the embodiment of FIG. 1, FIG. 4 is a flow chart diagram showing the processing process of the present invention, and FIG. The figure shows a conventional example, and FIG. 6 is a diagram showing a state of threshold setting. 1...Signal input terminal, 2...A/D converter, 3...
・Syndrome calculation circuit, 4... Erasure position detection circuit, 5, 6.7... Error correction circuit, 8, 9, 10
゜11... Inner product operation circuit, 12, 13.14... Judgment circuit, 15.16... Memory, 17... Exclusive OR gate, 18... AND gate, 19.20.・
・Signal output terminal Figure 4

Claims (1)

[Claims] 1. In decoding an error correction code to be recorded or transmitted,
Hard-decision data for which the reliability of the reproduced or received signal is less than or equal to a predetermined value is regarded as uncertain data, and when the number of uncertain data is less than or equal to d-1 (d: minimum Hamming distance of error correction code), uncertain data is regarded as uncertain data. By using it as an erasure candidate as it is, and when the number of uncertain data is d or more, any d-1 of them is an erasure candidate, and by ordering the erasure candidates according to an arbitrary rule and performing error correction and erasure correction. Generate multiple candidate code words, and if there is a code word whose inner product with the reproduced signal is larger than n - d (n: code length of error correction code), decode it and determine if it exists. A soft-decision decoding method characterized by outputting an error detection signal indicating that correction is not possible if the correction is not possible. 2. The soft-decision decoding method according to claim 1, wherein when the number of uncertain data is d or more, d-1 pieces of data that are reproduced or received earlier are selected as erasure candidates. 3. The soft-decision decoding system according to claim 1, wherein the erasure candidates are ordered in descending order of reproduction or reception.