JPS62183691A - Synchronizing circuit for video interface - Google Patents

Abstract

PURPOSE:To form a synchronizing clock with a simple constitution and with a low cost by providing an oscillator oscillating by the frequency twice of a video frequency, th first and the second D type flip flops and a gate circuit and obtaining a video frequency signal corresponding to a horizontal synchronizing signal from the Q output of the second D type flip flop. CONSTITUTION:When the horizontal synchronizing signal the inverse of HSYN from a video device is changed from L to H, the Q output CSFL O of the flip flop 7 is inverted from L to H, the inverse of the Q output CSFL 1 is inverted from H to L. Accordingly from the time when the inverse of the Q output is inverted, the output; the inverse of ACLK of an inverter 3 is outputted. Since a signal BCLK is inputted to the clock terminal of the flip flop 8, the flip flop 8 repeats the inverting operation according to the signal BCLK. Accordingly, the Q output CLK of the flip flop 8 is divided in frequency into 1/2 of the frequency of the oscillator 1 and it can be used as the synchronizing clock.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a synchronization circuit for a video interface for obtaining a synchronization clock for sampling video signals of graphic displays, personal computers, and the like.

(9. Technical background of Ming and its problems) When processing and using video signals from graphic displays, personal computers, etc., it is necessary to perform sampling to digitize the output video signals. For sampling, it is necessary to use a synchronous clock synchronized with the output side. By using the synchronization clock, it is possible to establish correspondence with each frame, and it is also possible to determine vertical synchronization and water synchronization for one screen.

In order to obtain such a synchronized clock, PLL (
(Phase Locked Loop) circuit, but this PLL circuit is expensive, and there is a strong demand for a device that can synchronize the clock using inexpensive means.9! It was rare.

(Object of the invention) This invention was made under the above circumstances,
An object of the present invention is to provide a synchronization circuit for a video interface that has a relatively simple configuration and is inexpensive.

(R essential point of the invention) The present invention relates to a synchronization circuit for a video interface, which includes an oscillator that oscillates at twice the video frequency of a video device, and a horizontal synchronization signal from the L video device as a clock signal. A first D-type flip-flop which inputs the clock pulse from the oscillator as the D terminal input, and inputs the horizontal synchronization signal as clear, and
A second D-type free 2 flip-flop whose D terminal input is the Q output, and the Q output of the D-type flip-flop of the above clock pulse and fIS1 are input, and the output thereof is inputted to the second D5 flip-flop. A gate circuit for providing a clock signal is provided, and a video frequency signal corresponding to the horizontal synchronizing signal is obtained from the Q output of the second D-type flip-flop.

(Embodiment of the invention) FIG. 1 is a circuit configuration diagram showing an embodiment of the invention.
The oscillator 1 oscillates at a frequency exactly twice the video frequency of a video device such as a graphic display, and the frequency accuracy is 0.012 or more. The clock pulse fc from the oscillator 1 is input to the waveform shaping circuit 2 and the inverter 3, and is also input to the D terminal input of the D5 flip-flop 7. The output ACLK of the waveform shaping circuit 2 is input to a NAND circuit 4.

The output ACLK of the inverter 3 is input to the NAND circuit 5, the Q output of the flip-flop 7 is input to the NAND circuit 5, and the Q output is input to the NAND circuit 4. and,
The outputs of the NAND circuits 4 and 5 are input to the NOR circuit 6, and the output BCLK of the NAND circuit 6 is input to the 7 lip-flop 8.
is input to the clock terminal of Further, the horizontal synchronizing signal H3YNC from the video device is input to the clock terminal of the flip-flop 7, and is also input to the clear terminal CLR of the clip-flop 8. Note that the Q output of the flip-flop 8 is manually input to its D terminal input.

In such a configuration, its operation is shown in FIGS.
This will be explained with reference to the timing chart of H).

The clock pulse fc from the oscillator 1 is converted by the waveform shaping circuit 2 into a signal ACLK as shown in FIG. 2(A), and the output of the inverter 3 becomes ACLK as shown in FIG. 2(B).

In this state, when the horizontal synchronizing signal H5YNC from the video device changes from "L" to "H" at time tl, the Q output GSFLD of the flip-flop 7 changes as shown in FIG. D), the Q output GSFLI is inverted from “L” to “H” as shown in the figure (D).
As shown in E), it is reversed from H'° to °゛L"°. Therefore, the output port CLK of the NOR circuit 6 is not output until time tl, but at time t1 when the Q output and the Q output of the flip-flop 7 are reversed. Therefore, in this example, the signal where the signal A (:LK rises first) is the output ACLK of the inverter 3 (see FIG. 2 (F)), and this signal BCLK
is input to the clock terminal of the flip-flop 8, so the flip-flop 8 repeats the inversion operation according to the signal BGLK as shown in the second (G). Therefore, the Q output CLK of the clip-flop 8 is as shown in FIG. As shown in (G), the frequency of oscillator l is divided into 172,
This can be used as a synchronization clock. In other words, the gate circuit uses the one of the two signals AGLK and ACLK that rises first after the horizontal synchronization signal H8YNC changes from "L" to "H", and this is input to the flip-flop 8. be able to. Along with this,
The output accuracy of the synchronous clock CLK is within 1/2 of the clock pulse re, that is, 1/4 pixel synchronization at maximum, and there is no particular problem in terms of accuracy. The video signal VS is input at time t2. t3. t4. You can sample as follows.

In the above-described embodiment, the gate circuit is composed of an inverter, a NAND circuit, and a NOR circuit, but it can also be composed of other logic elements.

(Effects of the Invention) As described above, according to the synchronous circuit of the present invention, a synchronous clock can be formed and outputted at low cost with a simple configuration.
Moreover, there is an advantage that the precision of the synchronization clock can be made high.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention, and FIGS. 2(A) to (H) are timing charts showing examples of its operation. ■... Oscillator, 2... Waveform shaping circuit, 3... Inverter, 4.5... NAND circuit, 6... NOR circuit,
7.8...D type flip-flop.

Claims (1)

[Claims] an oscillator that oscillates at twice the video frequency of the video device;
A first D-type flip-flop inputs the horizontal synchronizing signal from the video device as a clock signal and receives the clock pulse from the oscillator as a D terminal input; a second D-type flip-flop whose @output is a D-terminal input;
The clock pulse and the Q output and @Q@ output of the first D-type flip-flop are input, and the output is input to the second D-type flip-flop.
a gate circuit for providing a clock signal to a D-type flip-flop, and a video frequency signal corresponding to the horizontal synchronization signal is obtained from the Q output of the second D-type flip-flop. synchronous circuit.