JPS63275273A - Picture input device - Google Patents

Abstract

PURPOSE:To obtain the same function as that which can be obtained when an oscillation frequency is set twice with using an oscillator such as a liquid crystal oscillator of a high frequency stability and the like as it is by selecting the waveform of a signal which an oscillation circuit supplying a sampling clock has oscillated or frequency-divided and the inversion waveform and setting it as a sampling clock. CONSTITUTION:A sampling clock supply circuit consists of the oscillation circuit 1, flip flops 2 and 3, a buffer 4, a signal inversion circuit 5, a delay circuit 6, a signal selection circuit 7 and the input terminal 8 of a horizontal synchronizing signal. The waveform which the oscillation circuit 1 supplying the sampling clock has oscillated or frequency-divided and the inversion waveform are selected and is set to the sampling clock. Thus, an effect same as that when the oscillation frequency of the oscillator is set twice can be obtained with using the oscillation circuit of high frequency stability such as the liquid crystal oscillator and the like, and the quality of the inputted picture can be secured without complicating the oscillation circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image input device that digitizes a video signal with a certain sampling clock and performs image processing and display using the digital data. Concerning how to create a sampling clock.

[Conventional technology]

FIG. 3 shows a circuit for generating a sampling clock for a conventional image input device. In the figure, 1 is an oscillation circuit such as a crystal oscillator,
9, 10, 11 and 12 are frequency dividing circuits such as flip-flops, 13 is an input terminal for a horizontal synchronizing signal, and 14 is an output signal terminal. As shown in Figure 3, when sampling a video signal, the frequency of the original oscillation of the oscillation circuit is increased, and the clock for sampling the video signal is A clock whose frequency is divided by 1/2, 1/4, etc. of the original oscillation waveform was used to reduce the deviation in sampling position.

In addition, as shown in FIG. 4, as another conventional technique,
A method has been adopted in which the oscillator is stopped during the period when the horizontal synchronization signal is input. In Figure 4, 15, 16 and 17
is a NAND gate, 18 and 19 are resistors, 20 are variable resistors, 21, 22 and 23 are capacitors, 24 is a horizontal synchronization signal input terminal, and 25 is an oscillation clock output terminal.

The operating principle of the circuit shown in FIG. 4 will be briefly explained below. During the period when the horizontal synchronization signal is input to the terminal 24 and is at low level,
Oscillation has stopped. When the input to the terminal 24 is at a high level, that is, when the horizontal synchronizing signal is no longer input, the oscillation circuit shown in FIG. 4 immediately starts oscillating.

The oscillation frequency is determined by resistor 18.19 and capacitor 21.2.
2, 23 and the variable resistor 20 to obtain the output clock.

[Problem that the invention seeks to solve]

However, in the conventional technology shown in Figure 8, even if a highly accurate oscillator such as a crystal oscillator is used, it is necessary to increase the number of frequency divisions in order to reduce the deviation of the sampling position. As the number of cycles increases, the oscillation frequency of the oscillator increases. As the oscillation frequency increases, current consumption increases, radiation noise increases,
There are problems such as complicating the configuration of the oscillator and increasing costs.

In addition, in the conventional technique shown in FIG. 4, oscillation stops during the horizontal synchronization signal period and starts oscillation as soon as the synchronization signal is no longer input.
However, a highly accurate oscillator such as a crystal oscillator cannot be used because the growth of oscillation after the power is turned on is slow and the time required until stable oscillation is obtained varies. Furthermore, as shown in Fig. 4, in an oscillator composed of a logic IC, a resistor R1, and a capacitor C, it is necessary to install a component for adjusting the oscillation frequency (variable resistor 20 in Fig. 4), and it is also necessary to install a component for adjusting the oscillation frequency. There is a problem in that the oscillation frequency tends to change due to the influence of humidity and the like.

The present invention provides one means for solving these problems, and its purpose is to use an oscillator such as a crystal oscillator with high frequency stability, and to reduce the oscillation frequency to the conventional level. The idea is to make the timing at which the video signal is sampled almost the same in every horizontal period, without making it too thick.

[Means for solving problems]

The image input device of the present invention samples a video signal and inputs the sampling data by selecting an original waveform or a frequency-divided waveform of an oscillation circuit that supplies a sampling clock and its inverted waveform. It is characterized in that it is the sampling clock.

[Effect]

In the image input device configured as described above, the sampling clock is supplied by selecting the original waveform or the frequency-divided waveform and its inverted waveform. The period can be set to 1/2 of the frequency to be generated.

〔Example〕

FIG. 1 shows a sampling clock supply circuit according to an image input device of the present invention. In Figure 1, 1 is an oscillation circuit, 2 and 3 are flip-flops, 4 is a buffer,
5 is a signal inversion circuit, 6 is a delay circuit, 7 is a signal selection circuit,
8 is an input terminal for a horizontal synchronizing signal.

FIGS. 2A and 2B show signal waveforms in FIG. 1. In Figure 2, ■, ■, O, and 0 all indicate signals, 0 is a horizontal synchronization signal, ■ and O are the original signal and its inverted signal, and @ is a selected signal (hereinafter referred to as selection signal). It is. Also, ■, 010, and @ in Figure 2 are @ in Figure 1.
, 0, @, and 0 point waveforms are supported. Below is the second
The operation of the signals in the figure will be explained.

When the horizontal synchronizing signal 0 in FIG. 2 is at a low level, the signal O is output as the selection signal 0. Next, when the horizontal synchronization signal ■ rises from low level to high level, the selection signal @ is the one of signal 0 and signal O that falls from high level to low level first after horizontal synchronization signal ■ rises. Outputs the signal. Until then, the selection signal O is
Outputs signal O. In (1) of Fig. 2, after the horizontal open IJA (No. In addition, in (2) of Fig. 2, after the horizontal synchronization signal 0 rises from low level to high level, signal O falls before signal O, so selection signal O The signal ■ is output to the signal O.The signal O is output until either the signal O or the signal O falls.The phase difference between the falling points of the signal O and the signal O is the signal O. This is equal to the phase difference between the rising point and the falling point of , which corresponds to one-half period of the clock of signal A signal waveform is output, and the phase difference with the horizontal synchronization signal is at most 1/2 period of the original oscillation.

When sampling a video signal with an image input device, if there is a phase difference between the sampling clock and the horizontal synchronization signal, the input image will have a shift in each horizontal period, which will cause jitter and degrade the quality of the input image. . To overcome this, there are methods such as increasing the oscillation frequency as described above, but in the present invention, the same function as doubling the oscillation frequency can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the oscillation frequency of the oscillator can be doubled while using an oscillation circuit with high frequency stability such as a crystal oscillator in the circuit that supplies the sampling clock of the image input device. The same effect as above can be obtained, and the quality of the input image can be ensured without complicating the oscillator circuit. In addition, since the oscillation frequency can be kept low, it leads to a reduction in current consumption and radiated noise.
Since the oscillation circuit can also be simplified, it has the effect of reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a sampling clock generation circuit diagram of the image input device of the present invention. 2(A) and 2(B) are signal waveform diagrams explaining FIG. 1. FIG. 3 is a sampling clock generation circuit diagram of a conventional image input device. FIG. 4 is another sampling clock generation circuit diagram of a conventional image input device. 1...Oscillation circuit 2.3...Flip-flop 4...Buffer 5...Signal inversion circuit 6...Delay circuit 7...Signal selection circuit 8.13.24...Horizontal synchronization signal input terminal 9.10
．． 11.12... Frequency divider circuit 14.25... Output signal terminal 15.16.17... NAND gate 18.19...
・Resistance 20...Variable resistor 21.22.23...Capacitor or higher Figure 1

Claims (1)

[Claims] In an image input device that samples a video signal and inputs the sampling data, the waveform of the original oscillation or frequency-divided signal of an oscillation circuit that supplies the sampling clock and its inverted waveform are selected as the sampling clock. An image input device characterized by: