JPS62222731A - Asynchronizing input signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain a detection signal synchronizing with a clock pulse by resetting the 1st and 2nd flip-flops writing an input signal at the leading of the clock pulse by the clock pulse and the input signal. CONSTITUTION:An asynchronizing signal and a clock pulse are inputted respec tively to input lines 1, 2. When the level of a terminal C1 is changed from L to H and H to L, the output of a JK flip-flop FF is changed depending on the state of input terminals A1, B1, the output line 6 is kept to the preceding state when both terminals A1, B1 go th H and the state of the output line 6 is inverted. A FF 10 is operated similarly as the FF 4. The operation above is caused when both reset terminals R1, R2 are at L and the output lines 6, 11 go to L when both terminals R1, R2 go to H. Thus, the input signal changing point is detected at either the leading or trailing point of the clock pulse which comes first. Thus, the time between the signal change and its detection is much decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization circuit that detects changes in a signal input asynchronously to clock pulses and synchronizes them to the clock pulses. .

[Conventional technology]

FIG. 6 is a diagram showing the configuration of a conventional asynchronous input signal synchronization circuit disclosed in, for example, Japanese Patent Publication No. 61-748.
In the figure, (ri) is an asynchronous signal input line.

(2) is an inverter that inverts the clock pulse human power line 131H asynchronous input signal, F41. +5] Flip-flop whose input signal is the H asynchronous input signal and the signal inverted by the inverter (4), (6) is the output line of the flip-flop (4), (71fl flip-flop (5)
output line.

131 is an OR circuit 1 (9) which calculates the logical sum of the output signals of flip-flops (4) and (5), and is an output line of the entire circuit.

(A1), (A2), (B1) + (B2)
are input terminals of flip-flops (4) and (5), (C1) and (C2) are clock pulse input terminals of the flip-flops, and (R1) + (R2) are reset terminals of the flip-flops.

Next, the operation will be explained. The flip-flop (4) has an input terminal (A1ylS low level (abbreviated as below)
, the input terminal (B1) is at high level (hereinafter abbreviated as H)
When the clock pulse input terminal (C1) changes from L to H, the output line (6) becomes H, and the input terminal (A1) becomes H1.When the input terminal (B1) becomes L, the clock pulse input terminal (C1) changes from L to H, the output line (6) becomes L, and when both input terminals (A1) and (B1) become H, the output line (6) is held in the previous state, and the input terminal (A
When both 1) and (B1) become L, the output line (61) becomes the inversion of the previous state.The flip-flop (51) is constructed in the same way as the 7-lip 70-tub (4), and the clock pulse changes from H to L. When the output line (9) changes, it performs the same 'fx operation as the flip-flop (4) except that the potential of the output line (9) changes.The above operation is performed by the reset terminals (R1) and (R2').
are both L, and (R1) and (R2) are both Hf
If i is the output i1 of flip-flops (4) and (5) (
61.

(7) both become L. This operation is similar to that of a known JK type rough flip-flop.

Now, the clock pulse on the clock pulse input line +21 is low.
Suppose that the asynchronous signal input line (11) changes from H to L at this time. tl shown in FIG. 7 is at that point.

At the next rising edge t2 of the clock pulse, flip 70 (41) is inverted and H is output to the output line (6), causing 1
A JLfc detection signal equal to the clock pulse is output to outputs (9) through the OR circuit (8). Output line (6) at the same time
The H signal forcibly resets all flip-flops (5),
Fix the output line (7) to L. Therefore, even if the next clock pulse falls at t3, the flip-flop (5
) is in the reset state, so this is not detected. During this time, the output line (91ttlH) is held.

Conversely, the clock pulse input line (21 clock pulse is H)
Assume that at the time, the asynchronous signal input line (1) changes from H to L, and 14 is at that time as shown in FIG. At the next falling edge t5 of the clock pulse, flip 7
The 0 knob (5) is inverted and H is output to the output line (7), and a detection signal synchronized with the clock pulse is output to the output line (9) through the OR circuit (81).At the same time, the H signal on the output line (5) The flip-flop (41) is forcibly reset and the output line (
6) Fix to iL. Therefore, the next clock pulse is t6
Even if the voltage rises at , the flip-flop (4) remains in the reset state, and the flip-flop (5) is not reset. As a result, H is held on the output line (9).

After detecting a change from H to L of the asynchronous input signal.

That is, when the asynchronous signal input line (1) changes from L to H at tl after the flip-flop (41 to (5) - ten thousand outputs) fGc'fx'':), the inverter (
31 to the input terminal (B1) of the flip-flop (4).
) and the input terminal (B2) of the flip-flop (5).

Therefore, the flip-flop on the side that detects the change from H to L in the asynchronous input signal at the rising edge t8 or falling edge t9 of the next clock pulse (flip-flop (41 in Figure 7, flip-flop 70 (5) in Figure 8) is inverted and L is output to the output line.As a result, a detection signal synchronized with the clock pulse is output to the output line (9).

[Problem that the invention seeks to solve]

Since the conventional asynchronous input signal synchronization circuit is configured as described above, the change from L to H of the asynchronous input signal is determined by the state (rising or rising edge) of the clock pulse that detected the change from H to L of the asynchronous input signal. This results in a problem such as a large error occurring between the change time of the asynchronous input signal and the detection time.

This invention was made to solve the above-mentioned problems, and provides an entire circuit that detects signal changes at both the rising and falling edges of all clock pulses and obtains a detection signal synchronized with the clock pulse. The purpose is to

[Means for solving problems]

An asynchronous input signal synchronization circuit according to the present invention.

The first and second flip-flops, which receive the input signal 1 at the rising edge of the clock pulse, are reset by the clock pulse and the input signal 7'2.

[Effect]

The first and wJ2 flip-flops in this invention are reset by a clock pulse and an input signal.
A detection signal synchronized with the clock pulse is obtained from the output of the second flip-flop.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, (1) is an asynchronous signal input line, (21 is a clock pulse input line, (3) is an inverter that inverts the asynchronous input signal, +41.fi[ll'i asynchronous input signal and this is an inverter. (A JK type flip-flop whose input signal is the signal inverted by 41, +61 fl flip-flop (4) output line,
) and (5).
9) is the output line of the entire circuit, α3U is an inverter that inverts the clock pulse, C3 is an AND circuit that takes the logical product of the asynchronous input signal and the clock pulse, and α41 is the AND circuit that takes the logical product of the asynchronous input signal and the clock pulse (13) Wotoru AND circuit, 051 is a flip-flop (4
1 reset pulse input line, (Ll is the flip 70 reset pulse input line + (AI), (A5)
, (B1)e (Bs) is the input terminal e (C1) of the flip-flop (4) and (1G).

(C3) is the clock pulse input terminal of the flip-flop (CR1'), and (R3) is the reset terminal of the flip-flop.

Next, the operation will be explained. When the clock pulse input terminal (C1) changes from L to H, the output of the flip-flop (4) changes in the state of the input terminals (A1) and (Ih). ) is H
When the output line (6) becomes H, the input terminal (A1) becomes H.
When the 1 input terminal (B1) is L, the output line (6) becomes L, and when the input terminals (A1') - (B1) are both H, the output line (6) is held in the previous state, and the input Terminal (A
1).

When both (B1) become L, the output line (6) becomes an inversion of its previous state. The flip-flop αIU performs the same operation as the flip-flop (4). The above operation is performed when the reset terminals (R+) and (R2) are both low (non-reset state).
If (R1) and (R2) are both H, the outputs of flip-flop (4) and (IG H61, (If)
are both L.

Such operation is similar to the known JK type flip-flop.

Now, suppose that the asynchronous signal input line (11) changes from H to L. As shown in Figure 2, when the clock pulse of the clock pulse input line (2) is LO, the time synchronization signal input line 1) changes from H to L. tlo is at that point. When the asynchronous input signal is L, the reset pulse input line (I9 and αe become L and -
Flip-flop (4), αah, is in a non-reset state. At the next rising edge tll of the clock pulse, the flip-flop (4) is inverted and H is output to the output line (6), and via the OR circuit (8), a ratio detection signal is output to the output line (9) in synchronization with the clock pulse. do.

Further, at the next falling edge t12 of the clock pulse, the flip-flop member is inverted and H is also output to the output line αυ, but at this time, the output line (9) is at H and has no effect. As shown in the third factor, the clock pulse input line (2)
Assume that the clock pulse changes from the HO time synchronization signal input line 01H to L, and t13 is at that point. At the next falling edge t14 of the clock pulse, flip-flop +1CI is inverted, H is output to the output line αυ, and the OR circuit (
81'i, a detection signal synchronized with the clock pulse is output to the output line (9). Furthermore, at the next rising edge t15 of the clock pulse, the flip-flop (4) is inverted and H is also output to the output line (6).

Therefore, the change from H to L of the asynchronous signal input line (1) is as follows.

It will be detected immediately at the change point of the next clock pulse.

Conversely, asynchronous signal input II! (Suppose that 11 changes from L to H.

As shown in FIG. 4, when the clock pulse of the clock pulse input line (2) is L, the asynchronous signal input line changes from L to H, and t16 is the time point. At this time, the AND circuit α] becomes H from the reset pulse input line (IIDFin), and the flip-flop aah is reset and becomes the output line aυHL.
) is the output line +61 HH, and H is output to the output line (9). Rising edge t1 of next clock pulse
7, the input terminal (A1) is H1, the input terminal (B1) is L, or the reset pulse input line (151) goes from L to H, so the output line of the flip-flop (4) is connected to the AND circuit α3. +61flL, and the output line (9
) A detection signal synchronized with the clock pulse is output.

At the falling edge t18 of the next clock pulse, the input terminal (A3
), the H1 input terminal (B3) is at L, or through the AND circuit (t41'e), the reset pulse input line α[D[L goes from L to H, so the flip-flop +1(
The output line υ of I remains at L.

L continues to be output to the output line (9). Further, as shown in FIG. 5, it is assumed that when the clock pulse of the clock pulse input l1i1+21 is H, the asynchronous signal input line changes from L to H, and C19 is at that point. At this time, AND circuit Q
3t- through the reset pulse 51 (I51 goes from L to H, the flip-flop (4) is reset and the output line (6) goes to L. However, the clip-flop a
The output line αυ of C+ remains at H, and the output line (9) is at H.
is being output. C20 at the falling edge of the next clock pulse
The input terminal (A5) is H1 and the input terminal (B3) is L, or the reset pulse input line (Ie changes from L to H through the AND circuit α41, so it becomes the output line αυiL of the flip-flop αG, A detection signal synchronized with the clock pulse is output to the output line (9).At the rising edge C21 of the next clock pulse, the flip-flop (4
) remains at the output 1f61tI'iL, and the output line (9
) continues to output L.

Therefore, a change in the high level of the asynchronous signal input line fll is immediately detected at the change point of the next clock pulse that changes by 1.

In the above embodiment, a JK type flip-flop is used for the flip-flop (4) and αG, but a D-type flip-flop may also be used. In this case, the inverter f
31 t/i becomes unnecessary.

〔Effect of the invention〕

As described above, according to the present invention, the time point at which a signal that is generated asynchronously with a clock pulse changes can be detected at a time point that occurs earlier in time at either the rising point or the falling point of the clock pulse. Therefore, the time between the signal change time and the detection time is extremely short, which has the effect of improving the temporal accuracy when sampling an asynchronous signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an asynchronous input signal synchronization circuit according to an embodiment of the present invention, FIG. 2, and FIG. 4 and 5 are explanatory diagrams of the operation of FIG. 1, FIG. 6 is a configuration diagram of a conventional asynchronous input signal synchronization circuit, and FIG. 7 is a diagram illustrating the operation of FIG. FIG. 8 is an explanation of the operation of FIG. 6. In the figure, (1) is an asynchronous signal input line, and (2) is a clock pulse input line. (3), αX8 is an inverter, +41. (l[I is a clip-flop. f6), the output line of αDμ flip-flop, [8] is the OR circuit, (9) is the output line of the entire circuit, αJ and α-lump are the AND circuit. C1,s, eel h reset pulse input line. Note that the same reference numerals in the two figures indicate the same or equivalent parts.

Claims (1)

[Claims] In a synchronization circuit that synchronizes an input signal that is input asynchronously with a clock pulse, first and second flip-flops write the input signal at the rising edge of the clock pulse, and the first and second flip-flops write the input signal at the rising edge of the clock pulse. 1. An asynchronous input signal synchronization circuit characterized in that it has means for resetting a flip-flop, and obtains a detection signal synchronized with a clock pulse from the first and second flip-flops.