JPS62181031A - Integrating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an integrating circuit equipped with an offset compensation function and suitable for integrating an output signal from a CT scanner radiation detector.

[Background of the invention]

A conventional integration circuit of this type is shown in Figure 3 (Unexamined Japanese Patent Publication +1/r
59-1.83/170). 31.21st item, IN is an input terminal, OUT is an output terminal, 2 is an integrating amplifier, 3 is an integrating capacitor, 4 to 6 are the first to third switches.

7.10 is a resistor, 8 is a capacitor, 9 is a buffer amplifier, and 11 is a current limiting resistor. In addition, e + is the human input signal, 0° is the output signal, and j and Orr are the offset h from the nf stage circuit.
rfi flow, eorr is input offset cell 1 of integrating amplifier 2
~ Voltage. Note that the first to third switches 4 to 6 are operated at the timings shown in FIGS. 4(a) to 4(c).

It turns on and off, and at that time, the output signal el
, eo are as shown in FIGS. 4(d) and (e). Further, in FIG. 4, T] is a discharge mode period of the capacitor 3, T2 is an offset compensation mode period, and T;3 is an integral operation mode period.

Next, the operation of the dual conventional circuit will be explained.

During the discharge mode period T1, only the first switch 4 is ON.
Then, after the integrating capacitor 3 is discharged, a voltage equivalent to eoH is maintained across it.

Enters the compensation mode period T2 and turns off the first switch 4.
At the same time, when the third switch 6 is turned on, a voltage V is applied to the capacitor 8 such that the resistor 10 is energized by 1θ "f".
l+ occurs. This voltage V11 is during the compensation mode period T
At the end of step 2, the third switch 6 is turned off, so that the capacitor 8 holds the signal.

At the same time as the second switch 5 turns on, the third switch 6 turns on.
Integration from compensation mode period T2 by FF ・19
+ Operation mode 1 to period '1'3, but here, first e o r r equivalent 'I'If, pressure or integral capacitor 3
Therefore, when the second switch 5 is turned on, the integral operation starts from zero, that is, the integral operation is performed with eorr corrected. Also, when the third switch 6 is turned off, the voltage VH held in the capacitor 8 causes the resistor 1 to
0 is supplied with a current equivalent to 3-orr, and 1off is corrected over the entire integral operation mode period T3. As a result, the output terminal OUT receives an output signal e that is integrated only with respect to the original input signal e. . will be obtained.

The performance of the conventional circuit described above depends on the accuracy of the negative feedback loop (input offset current correction circuit) that is turned on by closing the third switch 6 during the compensation mode period T2. That is, during the compensation mode period T2, 1off proportional to the leakage output of the previous stage circuit (here, the X-ray detector) is supplied to the input terminal IN, and the capacitor 8 is charged. At this time, the voltage V11 held in the capacitor 8 becomes approximately Vo=-1Xet(on) --(1)R3, assuming that the resistance values of the resistors 1 and 10 are Ri + Rr. However, e+(orr) is the leakage output of the previous stage circuit.

"The accuracy of the voltage V+1 is as long as an oP amplifier with a high open gain is used for the integrating amplifier 2, the negative feedback gain is 10 to lOO
If it is about double that, there is no problem. However, this voltage Vl+
The accuracy of is when the 4iF range of 1off is wide, that is, 1
When orr contains high frequency components, resistor 7 and capacitor 8
Due to the time constant of 2C·R1 ((where Co is the capacity ii of the capacitor 8), the convergence of the voltage V11 in the compensation mode period T2 (in other words, the convergence of the negative feedback loop) is delayed, which causes a problem. .

Therefore, in order to maintain the accuracy of the voltage Vo even when Lorf contains high frequency components, the compensation mode 1 is
It was considered to make the period T2 sufficiently long.

However, this method had the following problems. In other words, in recent years there has been a strong demand for higher speeds in X-ray CT devices, but the higher the speed, the more vibrational energy and frequency components generated by the vibrations of the mechanical system transmitted to the X-ray detector. It's getting expensive. Under such circumstances, even if the compensation mode period T2 is lengthened, there is a problem in that it is difficult to satisfy the accuracy of the voltage vH, and it also goes against the demand for higher speed.

[Object 1 of the Invention] The present invention has been made to solve the above-mentioned problems.
The correction can be made without increasing the time interval, and therefore only the original input signal can be integrated at high speed and with high accuracy t! The object of the present invention is to provide an integrating circuit that can generate IJ.

[Summary of the invention]

In the circuit of the present invention, a fourth switch is provided in parallel to the capacitor that holds the voltage V11 in the negative feedback loop (man-powered offset current correction circuit) in the conventional circuit, and the third switch is connected at the beginning of the offset compensation mode period. With ONt, after the negative 3uI return loop converges, only the fourth switch is turned ON? By charging the capacitor at L and holding the voltage V11, the dual purpose is achieved.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of an integrating circuit according to the present invention.
In the figure, IN denotes a pre-stage circuit (not shown), here an input terminal into which the signal to be integrated (input signal e + ) from the X-ray detector is input, and OUT denotes the integrated output signal e.

An output terminal 2 from which 2 is output is an integrating amplifier consisting of an OP amplifier, and a non-inverting input terminal is grounded, and an inverting input terminal 2 is connected to an input terminal IN via an input resistor 1. 3 is the inverting input terminal of the integrating amplifier 2 and the output terminal OU
4 is the first switch connected between the inverting input terminal and the output terminal of the integrating amplifier 2; 5 is the output terminal and the output terminal OUT of the integrating amplifier 2;
A second switch connected between them, 11 is an output terminal OU
This is a current-limiting resistor for correcting eorr (voltage to the input voltage sensor 1 of the integrating amplifier 2) connected between ゛F and ground.

6. 7, 8, 9. 10 and 12 are a third switch, a resistor, which is located between the output terminal and the inverting input terminal of the integrating amplifier 2 and constitutes a 1off (input offset current) correction circuit;
They are a capacitor, a hesophon amplifier, a resistor, and a fourth switch. In this case, when the fourth switch 12 is OFF and the third switch 6 is turned on, the resistor 7 and the capacitor 8 supply a current corresponding to 1o'[ (hereinafter referred to as 1orr) to the resistor 10.
After the third switch 6 is turned off, the voltage V11 is generated.
This constitutes a CR voltage hold circuit that holds the voltage. Further, the fourth switch 12 is connected in parallel to the capacitor 8 in the CR voltage hold circuit.

The first to fourth switches 4 to 6, 12 are each made of a semiconductor switch such as a transistor, and are turned on and off by a switching means (not shown) at the timings shown in FIGS. 2(a) to 2(d). Also, in Figure 2, T
1 is the discharge mode period of the capacitor 3. T2 is the offset compensation mode period, and the third. Fourth switch 6.12
A first compensation mode period T21 in which both are ONL and a second compensation mode period T2 in which only the third switch 6 is ON.
It consists of 2. T3 is the integral operation mode period.

Next, the operation of the above-mentioned circuit of the present invention will be explained.

In the discharge mode period T1, first, only the first switch 4 is turned on, and after the integrating capacitor 3 is discharged, an eoH equivalent voltage is maintained between its both ends. - When period T21 in compensation mode period lower 2 is entered and the first switch 4 is turned off and the third switch 6 and fourth switch 12 are turned on at the same time, the potential v1 between the third switch 6 and the resistor 7 becomes
The potential is such that 1 orr is passed through the resistor 10.

After a period of time corresponding to when the potential v1 has stabilized, only the fourth switch 12 is turned on and the period 'r2
1 to period T22, CO・R11 (C11 is the capacitance value of capacitor 8 + R
11 is the resistance value of resistor 7).
r Compare. As a result, the voltage V11 is held in the capacitor 8 by turning off the third switch 6 at the end of the mode period T2.

At the same time as switch 5 turns on, third switch 6 turns off.
By doing so, the compensation mode period T2 (period T22) shifts to the integral operation mode 1-period T3, but here, since the voltage equivalent to eorf is previously held in the integral capacitor 3, it is activated at the same time as the second switch 5 is turned on. The integral operation is started from zero, that is, the integral operation is performed with eoff corrected. Further, when the third switch 6 is turned off, a current equivalent to 1 ort is passed through the resistor 10 by the voltage Vl+ held in the capacitor 8, and '1. o(r is corrected over the entire integral operation mode period T3, and as a result of the above, the output terminal O
The UT receives an output signal e which is integrated only for the original input a and e1. will be obtained. In this case, as described above, the initial period T2 during the compensation mode IUj interval ゛■゛2
1, the fourth switch 12 is turned on to short-circuit the capacitor 8, and then the capacitor 8 is charged to obtain the heavy pressure Vl+, so that the convergence of the negative feedback loop is accelerated.

The accuracy of the '1゛ pressure V11 can be maintained without lengthening the compensation mode period T2, and the integration operation becomes faster and more accurate.

〔Effect of the invention〕

As described above, the present invention is particularly effective when the offset current 1orr from the 111j stage circuit contains a high frequency component, and when the CR voltage Hall 1 path capacitor is always connected during the offset compensation moat period 2. The voltage V generated at
The delay in the convergence of l+ (convergence of the negative feedback loop) was prevented by short-circuiting both ends of the second capacitor "at the beginning of the second compensation mode period T2", so the accuracy of the voltage Vl+ was reduced during the compensation mode period T2. It is possible to maintain T2 without increasing it.

Therefore, the input off cell of the integrating amplifier l-? u pressure eor
Together with the correction of f, it is possible to integrate only the original input signal at high speed and with high precision, especially for high-speed type C.
It has great effects when applied to a circuit unit that integrates the output signal from a T-table device radiation detector.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing an embodiment of the circuit of the present invention, FIG. 2 is a timing chart 1 for explaining the operation of the same circuit, and FIG. 3 is a diagram showing a conventional circuit. FIG. 11 is a timing chart for explaining the operation of the same circuit. 1. Input resistance, 2. Integrating amplifier, 3. Integrating capacitor, 4 to 6. First to third switches, 7. lO・
...Resistance, 11. Current limiting resistor for eo r f correction, 12.
...4th switch, 1N...input terminal, OUT...
Output terminal. Patent applicant Hitachi Medical Co., Ltd. Patent attorney
Autumn Masamoto Actual Figure f Tf 121T22 Figure 3 I Tb

Claims (1)

[Claims] 1. An input terminal to which the signal to be integrated is input, an output terminal to which the integral output signal is output, and an integrator whose one input terminal is grounded and the other input terminal is connected to the input terminal via an input resistor. an amplifier, an integrating capacitor connected between the other input terminal and the output terminal of the integrating amplifier, a first switch connected between the other input terminal and the output terminal of the integrating amplifier, and the integrating amplifier. a second switch connected between the output terminal of the integrating amplifier and the other output terminal; a current limiting resistor for correcting the input offset voltage of the integrating amplifier connected between the output terminal and ground; an input offset current correction circuit configured to include at least a third switch between input terminals, a CR voltage hold circuit, and a fourth switch connected in parallel to a capacitor in the CR voltage hold circuit; After turning on, turn on the third and fourth switches at the same time.
and a switching means for outputting an integral output signal from the output terminal by turning on the second switch after turning off a fourth switch and a third switch in that order. Integrating circuit.