JPS62179762A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a reference resistor which can reduce a contact resistance and has high accuracy by uniformly dividing a contact in case of obtaining electrodes or wirings from an arbitrary point of a polycrystalline silicon layer by the number of a plurality of contact windows and optimized, and arranging the divided contacts. CONSTITUTION:When the values of contact resistors R3, R4 formed of a polycrystalline silicon layer and a wiring layer are different in case that a reference voltage is generated to comparators 1, 2, reference voltage correctly divided by reference resistors R1, R2 affect the resistors R3, R4. When the inputs of the comparators 1, 2 by the silicon layer and the wirings are shown by a plan electrode pattern drawing, they are for a polycrystalline silicon layer 3, aluminum wiring layers 4, 5 and a contact window 6. Here, the resistance values of the resistors R3, R4 depend upon the number of the windows. Thus, reference resistors of high accuracy can be obtained by forming the optimum number of the windows.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and in particular, when obtaining an electrode or wiring from an arbitrary point on a polycrystalline silicon resistance layer, contact resistance between the polycrystalline silicon layer and the electrode or wiring is reduced. The present invention provides a semiconductor device in which a highly accurate reference resistance can be obtained by minimizing .

2. Description of the Related Art Conventionally, for example, in manufacturing a reference resistor for an A/D converter, the connection between polycrystalline silicon and an electrode or wiring is formed by random contact windows, thereby obtaining an appropriate reference resistance. ing.

2. Problems to be Solved by the Invention In such conventional technology, when an electrode or wiring is obtained from an arbitrary point on a polycrystalline silicon layer, resistance values vary due to contacts, making it impossible to obtain a highly accurate reference resistance. No offense. This poses an obstacle to application to high-performance A/D converters and the like.

Means for Solving the Problems The present invention provides a method for obtaining an electrode or wiring from any point on a polycrystalline silicon layer by equally dividing the number of contact lines and contact windows into a plurality of optimized numbers. This is an exposed semiconductor device.

According to the present invention, it is possible to reduce the contact resistance that causes variations in the reference resistance, and it is possible to obtain a highly accurate reference resistance.

EXAMPLES The present invention will be described in detail below with reference to FIGS. 1 to 3.

FIG. 1 is a schematic equivalent circuit diagram showing a method of applying an analog human power v1 and a reference voltage v23/, :-, which are input to a comparator 1.2 of an A/D converter. When generating a reference voltage for each comparator 1, 2, reference resistors R1 and R2 formed of polycrystalline silicon layers must have the same resistance value. Here, if the values of the contact resistances R3 and R4 formed in the polycrystalline silicon layer and the wiring layer are different, the reference resistances R1 and R4 of each other are different.
If the reference voltage correctly divided by 2 is affected by the respective contact resistances R3 and R4, it will not be equally input to the comparator, and normal operation as an A/D converter will not be achieved.

FIG. 2 shows the input of a comparator using a polycrystalline silicon layer and aluminum wiring as a turn diagram of a plane electrode. - The resistance value of each contact resistor R3 and R4 depends on the number of contact windows.

FIG. 3 is an enlarged view illustrating the portion A in FIG. 2 in detail. Here, a indicates the dimension of one side of the contactable area, xf indicates the dimension of the contact window on the same side, and b indicates the interval between the contact windows.

When n contact windows are formed on the side of dimension a, the dimension x of the contact window side can be calculated using the following formula.

is the area of the contactable region or a, and when the area of a single contact window is x2, it can be expressed by the following equation.

S = n2X x2= (a - (n-1) b) 2L
= 44 Therefore, in FIG. 3, a=5. Taking b-1 as an example, the total area S and total perimeter length I4- can be determined as follows.

S = (5(n-1)')2=(e-n)2L
=4n(5-(n-1))=4n(6-n)5 When page n = 1 5=25 L=20 When n = 2 5=16 L=32 When n = 3 S=9
In the case of L = 36n = 4, 5 = 4L = 32 In this example, it is possible to reduce the contact resistance value and reduce the variation by increasing the number of contact windows to nine.

In this way, by creating the optimal number of contact windows,
A highly accurate reference resistance can be obtained.

Although the present invention has been described above in the case of polycrystalline silicon, it is also applicable to use of a diffusion layer in which opposite impurities are diffused into a -conductivity type semiconductor substrate.

Effects of the Invention According to the present invention, contact resistance and variation can be reduced, and a highly accurate reference resistance can be realized.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of the comparator section of the A/D converter according to the embodiment of the present invention, Fig. 2 is a planar electrode pattern diagram in a state equivalent to Fig. 1, and Fig. 3 is a diagram of the open planar electrode pattern 6. This is a partially enlarged view. 1.2... Comparator, 3... Polycrystalline silicon layer, 4.6... Aluminum wiring layer, 6...
...Contact window. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4.2-m-4/I), 7-nno “-Guku p Koten 11 2nd
figure

Claims (1)

[Claims] A semiconductor device in which the number of contact windows for wiring that comes into contact with a semiconductor resistance region is selected to maximize the total peripheral length of the windows, and is equally divided and arranged.