JPS6218731A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6218731A JPS6218731A JP15862185A JP15862185A JPS6218731A JP S6218731 A JPS6218731 A JP S6218731A JP 15862185 A JP15862185 A JP 15862185A JP 15862185 A JP15862185 A JP 15862185A JP S6218731 A JPS6218731 A JP S6218731A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistance value
- analog
- insulating film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にアナログ型或いはアナ
ログ内蔵型ゲートアレイに適用して好適な半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for application to an analog type or analog built-in type gate array.
一般に、ゲートアレイは半導体基板に形成した不純物拡
散層を主体に素子要素を構成し、これら素子要素間を接
続するアルミニウム等の配線パターンをユーザーの希望
機能、性能に応じて変えることにより、任意の回路を構
成することができる。In general, gate arrays consist of element elements mainly composed of impurity diffusion layers formed on a semiconductor substrate, and the wiring pattern of aluminum etc. that connects these element elements can be changed according to the user's desired function and performance. A circuit can be constructed.
このゲートアレイは、これまでデジタル回路に使用され
てきたが、近年ではアナログ要素も半導体装置内に取り
絹む必要が生じ、アナログ用途或いはアナログ内蔵のゲ
ートアレイ (アナログマスターと称する)が提案され
てきている。This gate array has so far been used in digital circuits, but in recent years it has become necessary to incorporate analog elements into semiconductor devices, and gate arrays for analog applications or gate arrays with built-in analog (referred to as analog masters) have been proposed. ing.
ところで、この種のゲートアレイでは、回路の一部を構
成する抵抗を半導体基板に形成した不純物拡散層で構成
し、この不純物拡散層に配線を接続した構成を採用して
いる。例えば、第5図<a)のように、半導体基板21
のエピタキシャル層22内に不純物を拡散させた抵抗層
23を形成し、その表面に形成した絶縁膜24に複数個
のコンタクト孔25を開設し、このコンタクト孔25を
通してアルミニウム等の配線26を接続することにより
、抵抗Rを構成し、これによりアナログ回路を構成して
いる。Incidentally, this type of gate array employs a configuration in which a resistor that constitutes a part of the circuit is constructed from an impurity diffusion layer formed on a semiconductor substrate, and wiring is connected to this impurity diffusion layer. For example, as shown in FIG. 5<a), the semiconductor substrate 21
A resistive layer 23 with impurities diffused therein is formed in the epitaxial layer 22 of the resistor layer 23, a plurality of contact holes 25 are formed in the insulating film 24 formed on the surface of the resistive layer 23, and a wiring 26 made of aluminum or the like is connected through the contact holes 25. This constitutes a resistor R, which constitutes an analog circuit.
上述した従来の半導体装置では、ゲートアレイの共通構
成要素として、前記コンタクト孔25までは用意されて
いるため、アルミニウム配線26のパターンを変えるこ
とにより抵抗Rの値の設定を行っている。例えば、同図
(a)の状態から抵抗値を減らす場合には同図(b)の
ようにアルミニウム配線26の一方を延ばして接続用と
してのコンタクト孔25を変更し、これにより抵抗層2
4の実質的な長さを短くして抵抗値を低減させている。In the conventional semiconductor device described above, since the contact hole 25 is provided as a common component of the gate array, the value of the resistance R is set by changing the pattern of the aluminum wiring 26. For example, in order to reduce the resistance value from the state shown in Figure (a), one side of the aluminum wiring 26 is extended to change the contact hole 25 for connection as shown in Figure (b).
4 is shortened to reduce the resistance value.
しかしながら、この構成では、抵抗値は離散的(ステッ
プ的)な値にしか設定することができないため、アナロ
グ回路の最適な設計を実現することは困難である。特に
、前述のようなアナログ型のゲートアレイでは、アナロ
グ回路の一部を構成する抵抗がアナログ性能を決定する
重要な要素となっており、例えば増幅器のバイアス及び
利得、或いは比較器のしきい値電圧、更にA/D、D/
Aコンバータの精度等がこの抵抗値によって直接的に決
定されいる。このため、抵抗値を自由に設定できないと
、回路性能を十分に発揮させることが困難になり、半導
体装置の性能低下を招くことになる。However, with this configuration, the resistance value can only be set to discrete (stepwise) values, so it is difficult to realize an optimal design of the analog circuit. In particular, in the analog gate array mentioned above, the resistance that forms part of the analog circuit is an important element that determines the analog performance, such as the bias and gain of the amplifier, or the threshold value of the comparator. Voltage, further A/D, D/
The accuracy of the A converter is directly determined by this resistance value. Therefore, if the resistance value cannot be set freely, it becomes difficult to fully demonstrate the circuit performance, resulting in a decrease in the performance of the semiconductor device.
また、この従来構成では、抵抗値を連続的に変化させる
場合には、共通構成要素からコンタクト孔25を除外し
なければならず、同図(c)のように、ユーザーからの
要求の都度、夫々異なる位置にコンタクト孔25を開設
形成する必要があり、応答時間、つまりTAT (ター
ン・アラウンド・タイム)が長くなり、ゲートアレイの
利点が低減される問題も生ずる。In addition, in this conventional configuration, if the resistance value is to be continuously changed, the contact hole 25 must be excluded from the common components, and as shown in FIG. It is necessary to form the contact holes 25 at different positions, which increases the response time, that is, TAT (turn around time), and reduces the advantage of the gate array.
本発明の半導体装置は、アナログ回路を構成する抵抗値
を連続的に変更設定しかつTATの短縮を図るために、
この抵抗を上面が露呈した状態で絶縁膜上に形成した薄
膜抵抗体で構成し、この薄膜抵抗体上に形成する配線の
オーバラップ量を任意に変更設定して抵抗値の設定を行
い得るように構成している。In the semiconductor device of the present invention, in order to continuously change and set the resistance value constituting the analog circuit and shorten the TAT,
This resistor is composed of a thin film resistor formed on an insulating film with the top surface exposed, and the resistance value can be set by arbitrarily changing the overlap amount of the wiring formed on this thin film resistor. It is composed of
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図乃至第3図は本発明をアナログ型ゲートアレイに
適用した実施例を示しており、第3図の平面図のように
、このゲートアレイ1は、トランジスタ領域2、抵抗領
域3及び周辺領域4で構成し、抵抗領域3に複数本の真
直な短冊状の抵抗体5を配列形成している。1 to 3 show an embodiment in which the present invention is applied to an analog gate array. As shown in the plan view of FIG. 3, this gate array 1 includes a transistor region 2, a resistance region 3, and the surrounding A plurality of straight strip-shaped resistors 5 are arranged in the resistor region 3.
これら抵抗体5は、第1図にAA線断面構造を示すよう
に、半導体基板6の表面に形成した二酸化シリコン等の
絶縁膜7上に、金属抵抗材料の薄膜を被着し、かつこれ
を真直な短冊状にパターン形成したものである。この抵
抗体5は、金属抵抗材料をスパッタ法或いは真空蒸着法
等によって被着した後、フォトリソグラフィ技術等を用
いてバターニングすることにより容易に形成できる。ま
た、その薄膜の材料や厚さ或いは幅寸法を任意に設定し
て最大抵抗値を任意に設定できる。そして、この抵抗体
5上に形成される眉間絶縁膜8は、この抵抗体5の上面
を露呈させるようにパターン形成している。図中、9は
トランジスタ領域2や周辺領域4を構成する不純物拡散
層である。These resistors 5 are made by depositing a thin film of a metal resistance material on an insulating film 7 such as silicon dioxide formed on the surface of a semiconductor substrate 6, as shown in the cross-sectional structure taken along line AA in FIG. The pattern is formed into straight strips. This resistor 5 can be easily formed by depositing a metal resistance material by sputtering, vacuum evaporation, or the like, and then patterning it using photolithography or the like. Moreover, the maximum resistance value can be arbitrarily set by arbitrarily setting the material, thickness, or width of the thin film. The glabellar insulating film 8 formed on the resistor 5 is patterned to expose the upper surface of the resistor 5. In the figure, reference numeral 9 denotes an impurity diffusion layer forming the transistor region 2 and the peripheral region 4.
このように構成したゲートアレイ1では、第2図に示す
ように、抵抗体5上に直接被着するようにアルミニウム
等の配線10をパターン形成する。In the gate array 1 constructed in this way, as shown in FIG. 2, wiring 10 made of aluminum or the like is patterned so as to be directly deposited on the resistor 5. As shown in FIG.
そして、このとき配線10の少な(とも一方が抵抗体5
上に重なる量(オーバラップする1)Laを変化調整し
て対をなす配線間の距離Lbを設定することにより、任
意の抵抗値を得ることができる。したがって、図外のア
ナログ回路の一部を構成する抵抗の値を連続的に変更設
定でき、増幅器のバイアス、利得や、比較器のしきい値
電圧や、A/D、D/Aコンバータの精度等を高精度に
設計でき、アナログ回路の性能を十分に発揮させること
ができる。At this time, if the wiring 10 is small (both sides are connected to the resistor 5),
An arbitrary resistance value can be obtained by changing and adjusting the overlapping amount (overlapping 1) La and setting the distance Lb between the pair of wirings. Therefore, it is possible to continuously change the value of the resistor that constitutes a part of the analog circuit (not shown), and adjust the bias and gain of the amplifier, the threshold voltage of the comparator, and the accuracy of the A/D and D/A converter. etc. can be designed with high precision, and the performance of analog circuits can be fully demonstrated.
また、この構成では配線10のパターンを変更して配線
IOが抵抗体5にオーバラップする量Laを変更するだ
けで任意の抵抗値を得ることができるので、これまでの
ゲートアレイと全く同様に取扱うことができ、回路構成
に際してのTATの増大を防止することもできる。In addition, in this configuration, any resistance value can be obtained by simply changing the pattern of the wiring 10 and changing the amount La by which the wiring IO overlaps the resistor 5. It is also possible to prevent an increase in TAT when configuring a circuit.
また、第4図はアナログ内蔵ゲートアレイ11を示して
おり、12はアナログ領域、13はデジタル領域、14
は周辺領域であり、このアナログ領域12内に抵抗体1
5を配列しである。この抵抗体15は前例と同じであり
、金属抵抗材料を薄膜に形成し、この上に被着する配線
のオーバラップ量を変更設定することにより連続的に変
化可能な任意の抵抗値を得ることができる。Further, FIG. 4 shows the analog built-in gate array 11, where 12 is an analog area, 13 is a digital area, and 14 is an analog area.
is the peripheral area, and the resistor 1 is placed in this analog area 12.
5 is arranged. This resistor 15 is the same as the previous example, and a metal resistance material is formed into a thin film, and an arbitrary resistance value that can be continuously changed can be obtained by changing and setting the amount of overlap of the wiring deposited thereon. I can do it.
ここで、前記各実施例では抵抗体を金属抵抗材料で構成
しているので、相対値比、温度特性、電源電圧特性の点
において優れている。また、金属抵抗材料に代えてポリ
シリコンを抵抗体として用いてもよい。更に、抵抗体の
平面パターン形状は真直な短冊状に限らず、L字状ある
いはコ字状等種々の形状に形成してもよい。Here, in each of the above embodiments, since the resistor is made of a metal resistance material, it is excellent in terms of relative value ratio, temperature characteristics, and power supply voltage characteristics. Further, polysilicon may be used as the resistor instead of the metal resistive material. Further, the planar pattern shape of the resistor is not limited to a straight strip shape, but may be formed in various shapes such as an L-shape or a U-shape.
以上説明したように本発明は、アナログ型或いはアナロ
グ内蔵のゲートアレイの抵抗を、半導体基板の絶縁膜上
に形成した薄膜抵抗体で構成し、この抵抗体の上に被着
する配線のオーバラップ量を変化設定することにより連
続変化可能な任意の抵抗値を得ることができるので、ア
ナログ回路の性能を最適かつ高精度に実現することがで
きるとともに、ゲートアレイのTATの増大を防止する
こともできる。As explained above, the present invention configures the resistor of an analog type gate array or a gate array with built-in analog by a thin film resistor formed on an insulating film of a semiconductor substrate, and overlaps the wiring deposited on the resistor. Since it is possible to obtain an arbitrary resistance value that can be continuously changed by changing the amount, it is possible to realize the optimal and highly accurate performance of analog circuits, and it is also possible to prevent an increase in the TAT of the gate array. can.
第1図は本発明の半導体装置の断面図、第2図は配線を
施した状態の第1図と同様の図、第3図はその平面レイ
アウト図、第4図は変形例の平面レイアウト図、第5図
(a) 、 (b) 、 (c)は従来構造およびその
問題点を説明するための断面図である。
1.11・・・ゲートアレイ、2・・・トランジスタ領
域、3・・・抵抗領域、4・・・周辺領域、5・・・抵
抗体、6・・・半導体基板、7・・・絶縁膜、8・・・
層間絶縁膜、9・・・不純物拡散層、10・・・配線、
12・・・アナログ領域、13・・・デジタル領域、1
4・・・周辺領域、15・・・抵抗体、21・・・半導
体基板、22・・・エピタキシャル層、23・・・抵抗
層、24・・・層間絶縁膜、25・・・コンタクト孔、
26・・・配線、L a・・・オーバラップ量。
代理人 弁理士 内 原 晋 ・・j、・・、1
・7゛・・・パ
ど−
第1図FIG. 1 is a cross-sectional view of the semiconductor device of the present invention, FIG. 2 is a similar view to FIG. 1 with wiring, FIG. 3 is a plan layout thereof, and FIG. 4 is a plan layout of a modified example. , FIGS. 5(a), 5(b), and 5(c) are sectional views for explaining the conventional structure and its problems. 1.11... Gate array, 2... Transistor region, 3... Resistance region, 4... Peripheral region, 5... Resistor, 6... Semiconductor substrate, 7... Insulating film , 8...
Interlayer insulating film, 9... Impurity diffusion layer, 10... Wiring,
12...Analog domain, 13...Digital domain, 1
4... Peripheral region, 15... Resistor, 21... Semiconductor substrate, 22... Epitaxial layer, 23... Resistance layer, 24... Interlayer insulating film, 25... Contact hole,
26...Wiring, L a...Overlap amount. Agent Patent Attorney Susumu Uchihara...j,...,1
・7゛・・・Pad- Figure 1
Claims (1)
レイ等の半導体装置において、前記アナログ回路の一部
を構成する抵抗を、半導体基板表面の絶縁膜上に上面を
露呈した状態で形成した薄膜抵抗体で構成し、かつこの
薄膜抵抗体上に被着する配線のオーバラップ量を任意に
変更設定して抵抗値を連続的に変化設定できるように構
成したことを特徴とする半導体装置。1. In a semiconductor device such as a gate array that constitutes at least a part of an analog circuit, a thin film resistor in which a resistor that constitutes a part of the analog circuit is formed on an insulating film on the surface of a semiconductor substrate with its upper surface exposed. What is claimed is: 1. A semiconductor device characterized in that the resistance value can be continuously changed by arbitrarily changing and setting the amount of overlap of wirings deposited on the thin film resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15862185A JPS6218731A (en) | 1985-07-17 | 1985-07-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15862185A JPS6218731A (en) | 1985-07-17 | 1985-07-17 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6218731A true JPS6218731A (en) | 1987-01-27 |
Family
ID=15675709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15862185A Pending JPS6218731A (en) | 1985-07-17 | 1985-07-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6218731A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6476735A (en) * | 1987-09-17 | 1989-03-22 | Nec Corp | Semiconductor integrated circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4858787A (en) * | 1971-11-22 | 1973-08-17 | ||
JPS55141748A (en) * | 1979-04-20 | 1980-11-05 | Sony Corp | Thin film resistor for mos field effect transistor |
JPS5772364A (en) * | 1980-10-24 | 1982-05-06 | Matsushita Electric Ind Co Ltd | Integrated circuit |
JPS59211246A (en) * | 1983-05-17 | 1984-11-30 | Nec Corp | Analog ic master slice system |
-
1985
- 1985-07-17 JP JP15862185A patent/JPS6218731A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4858787A (en) * | 1971-11-22 | 1973-08-17 | ||
JPS55141748A (en) * | 1979-04-20 | 1980-11-05 | Sony Corp | Thin film resistor for mos field effect transistor |
JPS5772364A (en) * | 1980-10-24 | 1982-05-06 | Matsushita Electric Ind Co Ltd | Integrated circuit |
JPS59211246A (en) * | 1983-05-17 | 1984-11-30 | Nec Corp | Analog ic master slice system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6476735A (en) * | 1987-09-17 | 1989-03-22 | Nec Corp | Semiconductor integrated circuit |
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